64M DDR SDRAM
K4D62323HA
- 1 -
Rev. 1.1 (Feb. 2001)
64Mbit DDR SDRAM
Revision 1.1
February 2001
512K x 32Bit x 4 Banks
with Bi-directional Data Strobe and DLL
Double Data Rate Synchronous DRAM
Samsung Electronics reserves the right to change products or specification without notice.
64M DDR SDRAM
K4D62323HA
- 2 -
Rev. 1.1 (Feb. 2001)
Revision History
Revision 1.1 (February 1, 2001)
Removed K4D62323HA-QC50
Revision 1.0 (August 16, 2000)
Revision 0.5 (July 12, 2000)
Removed Block Write function. Accordingly pin number 52 must be connected to low ( MCL only )
Removed Write Interrupted by Read function.
Changed I
CC1
/I
CC2N
/I
CC3N
/I
CC5
of K4D62323HA-* in "DC Characteristics" table.
Changed VIH/VIL of AC operating conditions from V
REF
+ 0.31 to V
REF
+ 0.35
Revision 0.4 (May 18, 2000) - Preliminary Spec
Changed tCDLR from 1tCK to 2tCK
Changed tDOSCK/tAC of K4D62323HA-QC50/55 from +/-0.6ns to 0.75ns
Replaced tDV with tOH in accordance with JEDEC
Changed DC operating conditions
- V
REF
from 1.15V(min)/1.35V(max) to 0.49*V
DDQ
/0.51*V
DDQ
- V
IH
/V
IL
from V
REF
+0.18(min)/V
REF
-0.18(max) to V
REF
+0.15(min)
/
V
REF
-0.15(max)
Changed VIH/VIL of AC operating conditions from V
REF
+ 0.35 to V
REF
+ 0.31
Revision 0.3 (March 17, 2000)
Define DC spec.
Revision 0.2 (February 17, 2000)
Add K4D62323HA-QC50
Removed K4D62323HA-QC66
Changed tRCD and tRP of K4D62323HA-QC55/60 from 4tCK to 3tCK
Removed tHZQ and tDIPW from the spec.
Changed tWPST from 0.25tCK to 0.4/0.6tCK
Changed tDQSCK and tAC of K4D62323HA-QC55 from 0.75ns to 0.6ns
Changed tCDLR from 2tCK to 1tCK
Revision 0.1 (January 6, 2000) - Target Spec
Defined Target Specification
64M DDR SDRAM
K4D62323HA
- 3 -
Rev. 1.1 (Feb. 2001)
The K4D62323H is 67,108,864 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 524,288 words by 32
bits, fabricated with SAMSUNG
s high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 1.5GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety
of high performance memory system applications.
3.3V
5% power supply for device operation
2.5V
5% power supply for I/O interface
SSTL_2 compatible inputs/outputs
4 banks operation
MRS cycle with address key programs
-. Read latency 3 (clock)
-. Burst length (2, 4, 8 and Full page)
-. Burst type (sequential & interleave)
Full page burst length for sequential burst type only
Start address of the full page burst should be even
All inputs except data & DM are sampled at the positive
going edge of the system clock
Differential clock input
Data I/O transactions on both edges of Data strobe
DLL aligns DQ and DQS transitions with Clock transition
GENERAL DESCRIPTION
FEATURES
Edge aligned data & data strobe output
Center aligned data & data strobe input
DM for write masking only
Auto & Self refresh
16ms refresh period (2K cycle)
100pin TQFP package
Maximum clock frequency up to 183MHz
Maximum data rate up to 366Mbps/pin
FOR 512K x 32Bit x 4 Bank DDR SDRAM
512K x 32Bit x 4 Banks Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
ORDERING INFORMATION
Part NO.
Max Freq.
Max Data Rate
Interface
Package
K4D62323HA-QC55
183MHz
366Mbps/pin
SSTL_2
100 TQFP
K4D62323HA-QC60
166MHz
333Mbps/pin
K4D62323HA-QC70
143MHz
286Mbps/pin
64M DDR SDRAM
K4D62323HA
- 4 -
Rev. 1.1 (Feb. 2001)
PIN CONFIGURATION
(Top View)
PIN DESCRIPTION
CK,CK
Differential Clock Input
BA
0
, BA
1
Bank Select Address
CKE
Clock Enable
A
0
~A
10
Address Input
CS
Chip Select
DQ
0
~ DQ
31
Data Input/Output
RAS
Row Address Strobe
V
DD
Power
CAS
Column Address Strobe
V
SS
Ground
WE
Write Enable
V
DDQ
Power for DQ
s
DQS
Data Strobe
V
SSQ
Ground for DQ
s
DM0~DM3
Data Mask
MCL
Must Connect Low
RFU
Reserved for Future Use
-
-
DQ29
VSSQ
DQ30
DQ31
VSS
VDDQ
N.C
N.C
N.C
N.C
N.C
VSSQ
RFU
DQS
VDDQ
VDD
DQ0
DQ1
VSSQ
DQ2
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
D
Q
3
V
D
D
Q
D
Q
4
D
Q
5
V
S
S
Q
D
Q
6
D
Q
7
V
D
D
Q
D
Q
1
6
D
Q
1
7
V
S
S
Q
D
Q
1
8
D
Q
1
9
V
D
D
Q
V
D
D
V
S
S
D
Q
2
0
D
Q
2
1
V
S
S
Q
D
Q
2
2
D
Q
2
3
V
D
D
Q
D
M
0
D
M
2
W
E
C
A
S
R
A
S
C
S
B
A
0
B
A
1
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
A7
A6
A5
A4
VSS
A9
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
A10
VDD
A3
A2
A1
A0
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
100 Pin TQFP
20 x 14 mm
2
0.65mm pin Pitch
D
Q
2
8
V
D
D
Q
D
Q
2
7
D
Q
2
6
V
S
S
Q
D
Q
2
5
D
Q
2
4
V
D
D
Q
D
Q
1
5
D
Q
1
4
V
S
S
Q
D
Q
1
3
D
Q
1
2
V
D
D
Q
V
S
S
V
D
D
D
Q
1
1
D
Q
1
0
V
S
S
Q
D
Q
9
D
Q
8
V
D
D
Q
V
R
E
F
D
M
3
D
M
1
C
K
C
K
C
K
E
M
C
L
A
8
(
A
P
)
8
0
7
9
7
8
7
7
7
6
7
5
7
4
7
3
7
2
7
1
7
0
6
9
6
8
6
7
6
6
6
5
6
4
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
64M DDR SDRAM
K4D62323HA
- 5 -
Rev. 1.1 (Feb. 2001)
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
For any applications using the single ended clocking, apply V
REF
to CK pin.
Symbol
Type
Function
CK, CK
*1
Input
The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except
DQ
s and DM
s that are sampled on both edges of the DQS.
CKE
Input
Activates the CK signal when high and deactivates the CK signal
when low. By deactivating the clock, CKE low indicates the Power
down mode or Self refresh mode.
CS
Input
CS enables the command decoder when low and disabled the com-
mand decoder when high. When the command decoder is disabled,
new commands are ignored but previous operations continue.
RAS
Input
Latches row addresses on the positive going edge of the CK with
RAS low. Enables row access & precharge.
CAS
Input
Latches column addresses on the positive going edge of the CK with
CAS low. Enables column access.
WE
Input
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQS
Input/Output
Data input and output are synchronized with both edge of DQS.
DM
0
~ DM
3
Input
Data In mask. Data In is masked by DM Latency=0 when DM is high
in burst write. DM
0
for DQ
0
~ DQ
7,
DM
1
for DQ
8
~ DQ
15,
DM
2
for
DQ
16
~ DQ
23,
DM
3
for DQ
24
~ DQ
31.
DQ
0
~ DQ
31
Input/Output
Data inputs/Outputs are multiplexed on the same pins.
BA
0
, BA
1
Input
Selects which bank is to be active.
A
0
~ A
10
Input
Row/Column addresses are multiplexed on the same pins.
Row addresses : RA
0
~ RA
10
, Column addresses : CA
0
~ CA
7
.
Column address CA
8
is used for auto precharge.
V
DD
/V
SS
Power Supply
Power and ground for the input buffers and core logic.
V
DDQ
/V
SSQ
Power Supply
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
V
REF
Power Supply
Reference voltage for inputs, used for SSTL interface.
MCL
MCL
Must connect to low
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