64M DDR SDRAM

K4D64163HF

- 3 -

Rev. 1.1(Aug. 2002)

The K4D64163H is 67,108,864 bits of hyper synchronous data rate Dynamic RAM organized as 4 x1,048,576 words by 16

bits, fabricated with SAMSUNG

s high performance CMOS technology. Synchronous features with Data Strobe allow

extremely high performance up to 1.2GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of

operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of

high performance memory system applications.

· 3.3V + 5% power supply for device operation

· 2.5V + 5% power supply for I/O interface

· SSTL_2 compatible inputs/outputs

· 4 banks operation

· MRS cycle with address key programs

-. Read latency 3 (clock)

-. Burst length (2, 4 and 8)

-. Burst type (sequential & interleave)

· All inputs except data & DM are sampled at the positive

going edge of the system clock

· Differential clock input

· No Wrtie-Interrupted by Read Function

GENERAL DESCRIPTION

FEATURES

· 2 DQS's ( 1DQS / Byte )

· Data I/O transactions on both edges of Data strobe

· DLL aligns DQ and DQS transitions with Clock transition

· Edge aligned data & data strobe output

· Center aligned data & data strobe input

· DM for write masking only

· Auto & Self refresh

· 64ms refresh period (4K cycle)

· 66pin TSOP-II

· Maximum clock frequency up to 300MHz

· Maximum data rate up to 600Mbps/pin

FOR 1M x 16Bit x 4 Bank DDR SDRAM

1M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL

ORDERING INFORMATION

Part NO.

Max Freq.

Max Data Rate

Interface

Package

K4D64163HF-TC33

300MHz

600Mbps/pin

SSTL_2

66 pin TSOP-II

K4D64163HF-TC36

275MHz

550Mbps/pin

K4D64163HF-TC40

250MHz

500Mbps/pin

K4D64163HF-TC50

200MHz

400Mbps/pin

K4D64163HF-TC60

166MHz

333Mbps/pin

64M DDR SDRAM

K4D64163HF

- 4 -

Rev. 1.1(Aug. 2002)

PIN CONFIGURATION

(Top View)

PIN DESCRIPTION

CK,CK

Differential Clock Input

, BA

Bank Select Address

CKE

Clock Enable

Address Input

Chip Select

~ DQ

Data Input/Output

RAS

Row Address Strobe

Power

CAS

Column Address Strobe

Ground

Write Enable

DDQ

Power for DQ

LDQS,UDQS

Data Strobe

SSQ

Ground for DQ

LDM,UDM

Data Mask

No Connection

66 PIN TSOP(II)

(400mil x 875mil)

(0.65 mm Pin Pitch)

DDQ

SSQ

DDQ

SSQ

RAS

CAS

LDM

DDQ

AP/A

LDQS

SSQ

DDQ

SSQ

DDQ

CKE

UDM

REF

SSQ

UDQS

64M DDR SDRAM

K4D64163HF

- 5 -

Rev. 1.1(Aug. 2002)

INPUT/OUTPUT FUNCTIONAL DESCRIPTION

*1 : The timing reference point for the differential clocking is the cross point of CK and CK.

For any applications using the single ended clocking, apply V

REF

to CK pin.

Symbol

Type

Function

CK, CK*1

Input

The differential system clock Input.

All of the inputs are sampled on the rising edge of the clock except

s and DM

s that are sampled on both edges of the DQS.

CKE

Input

Activates the CK signal when high and deactivates the CK signal

when low. By deactivating the clock, CKE low indicates the Power

down mode or Self refresh mode.

Input

CS enables the command decoder when low and disabled the com-

mand decoder when high. When the command decoder is disabled,

new commands are ignored but previous operations continue.

RAS

Input

Latches row addresses on the positive going edge of the CK with

RAS low. Enables row access & precharge.

CAS

Input

Latches column addresses on the positive going edge of the CK with

CAS low. Enables column access.

Input

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

LDQS,(U)DQS

Input/Output

Data Strobe : Output with read data, input with write data. Edge-
aligned with read data, centered in write data. Used to capture write
data. For the x16, LDQS corresponds to the data on DQ0-DQ7 ;
UDQS corresponds to the data on DQ8-DQ15.

LDM,UDM

Input

Input Data Mask : DM is an input mask signal for write data. Input
data is masked when DM is sampled HIGH along with that input data
during a WRITE access. DM is sampled on both edges of DQS. DM
pins include dummy loading internally, to matches the DQ and DQS
loading. For the x16, LDM corresponds to the data on DQ0-DQ7 ;
UDM correspons to the data on DQ8-DQ15.

~ DQ

Input/Output

Data inputs/Outputs are multiplexed on the same pins.

, BA

Input

Selects which bank is to be active.

~ A

Input

Row/Column addresses are multiplexed on the same pins.

Row addresses : RA

~ RA

, Column addresses : CA

~ CA

Power Supply

Power and ground for the input buffers and core logic.

DDQ

SSQ

Power Supply

Isolated power supply and ground for the output buffers to provide

improved noise immunity.

REF

Power Supply

Reference voltage for inputs, used for SSTL interface.

NC/RFU

No connection/

Reserved for future use

This pin is recommended to be left "No connection" on the device

64M DDR SDRAM

K4D64163HF

- 6 -

Rev. 1.1(Aug. 2002)

BLOCK DIAGRAM

(1Mbit x 16I/O x 4 Bank)

Bank Select

Timing Register

Addr

ess

Regi

Ref

r
esh

Coun

t
e

Row Buf

f
e

Row Dec

ode

B
u

ffe
r

Data Input Register

Serial to parallel

1Mx16

Sense

-
bi

t
pr
ef

t
p

t
B
u

ffe
r

I/O
C
o

t
r
o

Column Decoder

Latency & Burst Length

Programming Register

t
r
obe

en.

CK,CK

ADDR

LCKE

CK,CK

CKE

RAS

CAS

LDM

LDMi

CK,CK

LCAS

LRAS

LCBR

LWE

LWCBR

LRAS

LC
B

CK, CK

LWE

LDMi

x16

DQi

Data Strobe

Intput Buffer

DLL

UDM

64M DDR SDRAM

K4D64163HF

- 7 -

Rev. 1.1(Aug. 2002)

· Power-Up Sequence

DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

1. Apply power and keep CKE at low state (All other inputs may be undefined)
- Apply VDD before VDDQ .
- Apply VDDQ before VREF & VTT
2. Start clock and maintain stable condition for minimum 200us.
3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high .
4. Issue precharge command for all banks of the device.
5. Issue a EMRS command to enable DLL

6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL.

1,2

7. Issue precharge command for all banks of the device.

8. Issue at least 2 or more auto-refresh commands.
9. Issue a mode register set command with A8 to low to initialize the mode register.

*1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL.
*2 Sequence of 6&7 is regardless of the order.

FUNCTIONAL DESCRIPTION

Power up & Initialization Sequence

Command

tRP

2 Clock min.

precharge

ALL Banks

2nd Auto

Refresh

Mode

Any

Command

RFC

1st Auto

Refresh

RFC

EMRS

MRS

2 Clock min.

DLL Reset

~ ~

precharge

ALL Banks

Inputs must be

stable for 200us

200 Clock min.

~ ~

2 Clock min.

CK,CK

64M DDR SDRAM

K4D64163HF

- 8 -

Rev. 1.1(Aug. 2002)

The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,

addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for
variety of different applications. The default value of the mode register is not defined, therefore the mode register must be
written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and
WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of
address pins A

~ A

and BA

, BA

in the same cycle as CS, RAS, CAS and WE going low is written in the mode register.

Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents
can be changed using the same command and clock cycle requirements during operation as long as all banks are in the
idle state. The mode register is divided into various fields depending on functionality. The burst length uses A

~ A

addressing mode uses A

, CAS latency(read latency from column address) uses A

~ A

. A

is used for test mode. A

used for DLL reset. A

, BA

and BA

must be set to low for normal MRS operation. Refer to the table for specific codes

for various burst length, addressing modes and CAS latencies.

MODE REGISTER SET(MRS)

Address Bus

Mode Register

CAS Latency

Latency

Reserved

Burst Length

Burst Type

Sequential

Interleave

Reserve

Burst Type

Type

Sequential

Interleave

* RFU(Reserved for future use)

should stay "0" during MRS
cycle.

MRS Cycle

Command

*1 : MRS can be issued only at all banks precharge state.
*2 : Minimum

is required to issue MRS command.

CK, CK

Precharge

NOP

MRS

NOP

Any

NOP

All Banks

Command

MRD

=2 t

RFU

DLL

CAS Latency

Burst Length

~ A

MRS

EMRS

DLL

DLL Reset

Yes

Test Mode

mode

Normal

Test

NOP

64M DDR SDRAM

K4D64163HF

- 9 -

Rev. 1.1(Aug. 2002)

The extended mode register stores the data for enabling or disabling DLL and selecting output driver

strength. The default value of the extended mode register is not defined, therefore the extened mode register
must be written after power up for enabling or disabling DLL. The extended mode register is written by assert-
ing low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE
already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A11
and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. A1
and A6 are used for setting driver strength to normal, weak or matched impedance. Two clock cycles are
required to complete the write operation in the extended mode register. The mode register contents can be
changed using the same command and clock cycle requirements during operation as long as all banks are in
the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address
pins except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific
codes.

DLL Enable

Enable

Disable

~ A

MRS

EMRS

EXTENDED MODE REGISTER SET(EMRS)

Address Bus

Extended

*1 : RFU(Reserved for future use) should stay "0" during EMRS cycle.

Output Driver Impedence Control

Weak

Matched

RFU

D.I.C

RFU

D.I.C

DLL

Mode Register

64M DDR SDRAM

K4D64163HF

- 10 -

Rev. 1.1(Aug. 2002)

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Note :

POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out)

Recommended operating conditions(Voltage referenced to V

=0V, T

=0 to 65

Parameter

Symbol

Min

Typ

Max

Unit

Note

Device Supply voltage

3.135

3.3

3.465

Output Supply voltage

DDQ

2.375

2.50

2.625

Reference voltage

REF

0.49*V

DDQ

0.51*V

DDQ

Termination voltage

Vtt

REF

-0.04

REF

+0.04

Input logic high voltage

IH(DC)

REF

+0.15

DDQ

+0.30

Input logic low voltage

IL(DC)

-0.30

REF

-0.15

Output logic high voltage

Vtt+0.76

=-15.2mA

Output logic low voltage

Vtt-0.76

=+15.2mA

Input leakage current

-5

Output leakage current

-5

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Value

Unit

Voltage on any pin relative to Vss

, V

OUT

-0.5 ~ 3.6

Voltage on V

supply relative to Vss

-1.0 ~ 3.6

Voltage on V

supply relative to Vss

DDQ

-0.5 ~ 3.6

Storage temperature

STG

-55 ~ +150

Power dissipation

1.0

Short circuit current

1. Under all conditions V

DDQ

must be less than or equal to V

2. V

REF

is expected to equal 0.50*V

DDQ

of the transmitting device and to track variations in the DC level of the same. Peak to

peak noise on the V

REF

may not exceed +

2% of the DC value. Thus, from 0.50*V

DDQ

, V

REF

is allowed +

25mV for DC error

and an additional +

25mV for AC noise.

3. V

of the transmitting device must track V

REF

of the receiving device.

4. V

(max.)= V

DDQ

+1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.

5. V

(mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.

6. For any pin under test input of 0V < V

< V

is acceptable. For all other pins that are not under test V

=0V.

Note :

64M DDR SDRAM

K4D64163HF

- 11 -

Rev. 1.1(Aug. 2002)

DC CHARACTERISTICS

Note : 1. Measured with outputs open.

2. Refresh period is 64ms.

Parameter

Symbol

Test Condition

Version

Unit Note

-33

-36

-40

-50

-60

Operating Current
(One Bank Active)

CC1

Burst Lenth=2

(min)

=0mA,

(min)

210

200

190

170

160

Precharge Standby Current
in Power-down mode

CC2

CKE

(max),

(min)

Precharge Standby Current
in Non Power-down mode

CC2

CKE

(min), CS

(min),

(min)

110

105

Active Standby Current
power-down mode

CC3

CKE

(max),

(min)

110

105

Active Standby Current in
in Non Power-down mode

CC3

CKE

VIH(min), CS

VIH(min),

(min)

160

150

140

120

100

Operating Current
( Burst Mode)

CC4

RFC

(min)

RFC

(min)

Page Burst, All Banks activated.

390

370

350

320

300

Refresh Current

CC5

RFC

(min)

210

200

190

180

170

Self Refresh Current

CC6

CKE

0.2V

Recommended operating conditions Unless Otherwise Noted, T

=0 to 65

1. V

is the magnitude of the difference between the input level on CK and the input level on CK

2. The value of V

is expected to equal 0.5*V

DDQ

of the transmitting device and must track variations in the DC level of the same

Note :

AC INPUT OPERATING CONDITIONS

Recommended operating conditions(Voltage referenced to V

=0V, V

=3.3V+

5%, V

DDQ

=2.5V+

5%,T

=0 to 65

Parameter

Symbol

Min

Typ

Max

Unit

Note

Input High (Logic 1) Voltage; DQ

REF

+0.35

Input Low (Logic 0) Voltage; DQ

REF

-0.35

Clock Input Differential Voltage; CK and CK

0.7

DDQ

+0.6

Clock Input Crossing Point Voltage; CK and CK

0.5*V

DDQ

-0.2

0.5*V

DDQ

+0.2

64M DDR SDRAM

K4D64163HF

- 12 -

Rev. 1.1(Aug. 2002)

=50

Output

LOAD

=30pF

(Fig. 1) Output Load Circuit

Z0=50

REF

=0.5*V

DDQ

=0.5*V

DDQ

DECOUPLING CAPACITANCE GUIDE LINE

Recommended decoupling capacitance added to power line at board.

Parameter

Symbol

Value

Unit

Decoupling Capacitance between V

and V

DC1

0.1 + 0.01

Decoupling Capacitance between V

DDQ

and V

SSQ

DC2

0.1 + 0.01

1. V

and V

DDQ

pins are separated each other.

All V

pins are connected in chip. All V

DDQ

pins are connected in chip.

2. V

and V

SSQ

pins are separated each other

All V

pins are connected in chip. All V

SSQ

pins are connected in chip.

Note :

AC OPERATING TEST CONDITIONS

=3.3V

±5%

, T

= 0 to 65

Parameter

Value

Unit

Note

Input reference voltage for CK(for single ended)

0.50*V

DDQ

CK and CK signal maximum peak swing

1.5

CK signal minimum slew rate

1.0

V/ns

Input Levels(V

)

REF

+0.35/V

REF

-0.35

Input timing measurement reference level

REF

Output timing measurement reference level

Output load condition

See Fig.1

CAPACITANCE

=3.3V, T

= 25

f=1MHz)

Parameter

Symbol

Min

Max

Unit

Input capacitance(

CK, CK )

IN1

1.0

5.0

Input capacitance(A

, BA

~BA

)

IN2

1.0

4.0

Input capacitance
(

CKE, CS, RAS,CAS, WE )

IN3

1.0

4.0

Data & DQS input/output capacitance(DQ

~DQ

)

OUT

1.0

6.5

Input capacitance(DM0 ~ DM3)

IN4

1.0

6.5

64M DDR SDRAM

K4D64163HF

- 13 -

Rev. 1.1(Aug. 2002)

C CHARACTERISTICS

Parameter

Sym-

bol

-33

-36

-40

-50

-60

Unit Note

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

K cycle time

CL=3

3.3

4.0

3.6

4.0

5.0

6.0

K high level width

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

tCK

K low level width

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

tCK

QS out access time from CK

DQSCK

-0.6

0.6

-0.6

0.6

-0.6

0.6

-0.7

0.7

-0.75

0.75

utput access time from CK

-0.6

0.6

-0.6

0.6

-0.6

0.6

-0.7

0.7

-0.75

0.75

ata strobe edge to Dout edge

DQSQ

0.4

0.45

0.5

ead preamble

RPRE

0.9

1.1

0.9

1.1

0.9

1.1

0.9

1.1

0.9

1.1

tCK

ead postamble

RPST

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

tCK

K to valid DQS-in

DQSS

0.8

1.25

0.85

1.15

0.85

1.15

0.8

1.2

0.75

1.25

tCK

QS-In setup time

WPRES

QS-in hold time

WPREH

0.45

0.35

0.3

0.25

tCK

QS write postamble

WPST

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

tCK

QS-In high level width

DQSH

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

tCK

QS-In low level width

DQSL

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

tCK

ddress and Control input setup

0.9

1.0

1.1

ddress and Control input hold

0.9

1.0

1.1

Q and DM setup time to DQS

0.4

0.45

0.5

Q and DM hold time to DQS

0.4

0.45

0.5

lock half period

tCLmin

tCHmin

tCLmin

tCHmin

tCLmin

tCHmin

tCLmin

tCHmin

tCLmin

tCHmin

ata output hold time from DQS

tHP-0.4

tHP-
0.45

tHP-0.5

ote 1 :

The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data

strobe and all data associated with that data strobe are coincidentally valid.

- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst

ase

output vaild window even then the clock duty cycle applied to the device is better than 45/55%

A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle

variation and replaces tDV

tQHmin = tHP-X where

. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)
. X=A frequency dependent timing allowance account for tDQSQmax

64M DDR SDRAM

K4D64163HF

- 14 -

Rev. 1.1(Aug. 2002)

AC CHARACTERISTICS (II)

K4D64163HF-TC33

Frequency

Cas Latency

tRC

tRFC

tRAS

tRCD

tRP

tRRD

tDAL

Unit

300MHz (3.0ns )

tCK

275MHz ( 3.6ns )

tCK

250MHz ( 4.0ns )

tCK

200MHz ( 5.0ns )

tCK

166MHz ( 6.0ns )

tCK

(Unit : Number of Clock)

AC CHARACTERISTICS (I)

Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM

Parameter

Symbol

-33

-36

-40

-50

-60

Unit

Note

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Row cycle time

tCK

Refresh row cycle time

RFC

tCK

Row active time

RAS

100K

tCK

RAS to CAS delay

RCD

tCK

Row precharge time

tCK

Row active to Row active

RRD

tCK

Last data in to Row precharge
@Normal Precharge

tCK

Last data in to Row precharge
@Auto Precharge

WR_A

tCK

Last data in to Read command

CDLR

tCK

Col. address to Col. address

CCD

tCK

Mode register set cycle time

MRD

tCK

Auto precharge write recovery
+ Precharge

DAL

tCK

Exit self refresh to read com-

XSR

200

tCK

Power down exit time

PDEX

2tCK

+tIS

2tCK

+tIS

1tCK

+tIS

1tCK

+tIS

1tCK

+tIS

Refresh interval time

REF

15.6

K4D64163HF-TC36

Frequency

Cas Latency

tRC

tRFC

tRAS

tRCD

tRP

tRRD

tDAL

Unit

275MHz (3.6ns )

tCK

250MHz ( 4.0ns )

tCK

200MHz ( 5.0ns )

tCK

166MHz ( 6.0ns )

tCK

K4D64163HF-TC40

Frequency

Cas Latency

tRC

tRFC

tRAS

tRCD

tRP

tRRD

tDAL

Unit

250MHz ( 4.0ns )

tCK

200MHz ( 5.0ns )

tCK

166MHz ( 6.0ns )

tCK

64M DDR SDRAM

K4D64163HF

- 15 -

Rev. 1.1(Aug. 2002)

BAa

tRCD

ACTIVEA

ACTIVEB WRITEA

WRITEB

BAa

BAb

BAa

PRECH

BAa

Normal Write Burst

(@ BL=4)

Multi Bank Interleaving Write Burst

(@ BL=4)

BAa

BAb

tRAS

tRC

tRP

tRRD

COMMAND

DQS

CK, CK

A10/AP

ADDR

(A0~A11)

BA[1:0]

ACTIVEA

WRITEA

Da0 Da1 Da2 Da3

Simplified Timing @ BL=4

Db0 Db1

Db3

Da0 Da1 Da2 Da3

Db2

K4D64163HF-TC50

Frequency

Cas Latency

tRC

tRFC

tRAS

tRCD

tRP

tRRD

tDAL

Unit

200MHz ( 5.0ns )

tCK

166MHz ( 6.0ns )

tCK

K4D64163HF-TC60

Frequency

Cas Latency

tRC

tRFC

tRAS

tRCD

tRP

tRRD

tDAL

Unit

166MHz ( 6.0ns )

tCK

64M DDR SDRAM

K4D64163HF

- 16 -

Rev. 1.1(Aug. 2002)

PACKAGE DIMENSIONS (66pin TSOP-II)

Units : Millimeters

0.30

0.08

0.65TYP

(0.71)

22.22

0.10

0.125

(
0

.80)

10.1

0.10

#33

#66

#34

(1.50)

(
1

.50)

0.65

0.08

1.0

0.10

1.20M

(
0

.50)

.
5

)

(
1

0.76)

.
7

0.20

(10

)

(10

)

+0.075

-0.035

(
0

.
80)

0.10 MAX

0.075 MAX

[

]

0.05 M

I
N

(10

)

(10

)

(R0

.15

)

0.210

0.05

0.665

0.05

(R0

)

(R0

.
45~

0.75

0.25TYP

NOTE
1. ( ) IS REFERENCE
2. [ ] IS ASS

Y OUT QUALITY

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