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Электронный компонент: K4E151612D

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K4E171611D, K4E151611D
CMOS DRAM
K4E171612D, K4E151612D
This is a family of 1,048,576 x 16 bit Extended Data Out CMOS DRAMs. Extended Data Out Mode offers high speed random access of
memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+5.0V or +3.3V), refresh cycle (1K Ref. or 4K
Ref.), access time (-45, -50 or -60), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features
of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-
refresh operation is available in L-version. This 1Mx16 EDO Mode DRAM family is fabricated using Samsung
s advanced CMOS pro-
cess to realize high band-width, low power consumption and high reliability. It may be used as graphic memory unit for microcomputer,
personal computer and portable machines.
Part Identification

- K4E171611D-J(T) (5V, 4K Ref.)
- K4E151611D-J(T) (5V, 1K Ref.)
- K4E171612D-J(T) (3.3V, 4K Ref.)
- K4E151612D-J(T) (3.3V, 1K Ref.)
Extended Data Out Mode operation
(Fast Page Mode with Extended Data Out)
2 CAS Byte/Word Read/Write operation
CAS-before-RAS refresh capability
RAS-only and Hidden refresh capability
Self-refresh capability (L-ver only)
TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
Early Write or output enable controlled write
JEDEC Standard pinout
Available in plastic SOJ 400mil and TSOP(II) packages
Single +5V
10% power supply (5V product)
Single +3.3V
0.3V power supply (3.3V product)
Control
Clocks
VBB Generator
Refresh Timer
Refresh Control
Refresh Counter
Row Address Buffer
Col. Address Buffer
Row Decoder
Column Decoder
Lower
Data out
Buffer
RAS
UCAS
LCAS
W
Vcc
Vss
DQ0
to
DQ7
A0-A11
(A0 - A9)
*1
A0 - A7
(A0 - A9)
*1
Memory Array
1,048,576 x16
Cells
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
1M x 16Bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Refresh Cycles
Part
NO.
V
CC
Refresh
cycle
Refresh period
Nor-
L-ver
K4E171611D
5V
4K
64ms
128ms
K4E171612D
3.3V
K4E151611D
5V
1K
16ms
K4E151612D
3.3V
Performance Range
Speed
t
RAC
t
CAC
t
RC
t
HPC
Remark
-45
45ns
13ns
69ns
16ns
5V/3.3V
-50
50ns
15ns
84ns
20ns
5V/3.3V
-60
60ns
17ns
104ns
25ns
5V/3.3V
Active Power Dissipation
Speed
3.3V
5V
4K
1K
4K
1K
-45
360
540
550
825
-50
324
504
495
770
-60
288
468
440
715
Unit : mW
S
e
n
s
e

A
m
p
s

&

I
/
O
Upper
Data in
Buffer
Upper
Data out
Buffer
Lower
Data in
Buffer
DQ8
to
DQ15
OE
Note)
*1
: 1K Refresh
K4E171611D, K4E151611D
CMOS DRAM
K4E171612D, K4E151612D
V
CC
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
N.C
N.C
N.C
W
RAS
*A11(N.C)
*A10(N.C)
A0
A1
A2
A3
V
CC
V
SS
DQ15
DQ14
DQ13
DQ12
V
SS
DQ11
DQ10
DQ9
DQ8
N.C
N.C
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
PIN CONFIGURATION (Top Views)
Pin Name
Pin Function
A0 - A11
Address Inputs (4K Product)
A0 - A9
Address Inputs (1K Product)
DQ0 - 15
Data In/Out
V
SS
Ground
RAS
Row Address Strobe
UCAS
Upper Column Address Strobe
LCAS
Lower Column Address Strobe
W
Read/Write Input
OE
Data Output Enable
V
CC
Power(+5V)
Power(+3.3V)
N.C
No Connection
V
CC
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
N.C
N.C
W
RAS
*A11(N.C)
*A10(N.C)
A0
A1
A2
A3
V
CC
V
SS
DQ15
DQ14
DQ13
DQ12
V
SS
DQ11
DQ10
DQ9
DQ8
N.C
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
*A10 and A11 are N.C for K4E151611(2)D(5V/3.3V, 1K Ref. product)
J : 400mil 42 SOJ
T : 400mil 50(44) TSOP II
K4E17(5)1611(2)D-J
K4E17(5)1611(2)D-T
K4E171611D, K4E151611D
CMOS DRAM
K4E171612D, K4E151612D
ABSOLUTE MAXIMUM RATINGS
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted
to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Parameter
Symbol
Rating
Units
3.3V
5V
Voltage on any pin relative to V
SS
V
IN,
V
OUT
-0.5 to +4.6
-1.0 to +7.0
V
Voltage on V
CC
supply relative to V
SS
V
CC
-0.5 to +4.6
-1.0 to +7.0
V
Storage Temperature
Tstg
-55 to +150
-55 to +150
C
Power Dissipation
P
D
1
1
W
Short Circuit Output Current
I
OS
Address
50
50
mA
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to Vss, T
A
= 0 to 70
C)
*1 : V
CC
+1.3V/15ns(3.3V), V
CC
+2.0V/20ns(5V), Pulse width is measured at V
CC
*2 : -1.3V/15ns(3.3V), -2.0V/20ns(5V), Pulse width is measured at V
SS
Parameter
Symbol
3.3V
5V
Units
Min
Typ
Max
Min
Typ
Max
Supply Voltage
V
CC
3.0
3.3
3.6
4.5
5.0
5.5
V
Ground
V
SS
0
0
0
0
0
0
V
Input High Voltage
V
IH
2.0
-
V
CC
+0.3
*1
2.4
-
V
CC
+1.0
*1
V
Input Low Voltage
V
IL
-0.3
*2
-
0.8
-1.0
*2
-
0.8
V
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Max
Parameter
Symbol
Min
Max
Units
3.3V
Input Leakage Current (Any input 0
V
IN
V
IN
+0.3V,
all other input pins not under test=0 Volt)
I
I(L)
-5
5
uA
Output Leakage Current
(Data out is disabled, 0V
V
OUT
V
CC
)
I
O(L)
-5
5
uA
Output High Voltage Level(I
OH
=-2mA)
V
OH
2.4
-
V
Output Low Voltage Level(I
OL
=2mA)
V
OL
-
0.4
V
5V
Input Leakage Current (Any input 0
V
IN
V
IN
+0.5V,
all other input pins not under test=0 Volt)
I
I(L)
-5
5
uA
Output Leakage Current
(Data out is disabled, 0V
V
OUT
V
CC
)
I
O(L)
-5
5
uA
Output High Voltage Level(I
OH
=-5mA)
V
OH
2.4
-
V
Output Low Voltage Level(I
OL
=4.2mA)
V
OL
-
0.4
V
K4E171611D, K4E151611D
CMOS DRAM
K4E171612D, K4E151612D
*Note :
I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
, I
CC3
and I
CC6,
address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one Hyper page mode cycle time, t
HPC
.
DC AND OPERATING CHARACTERISTICS
(Continued)
I
CC1
* : Operating Current (RAS and UCAS, LCAS, Address cycling @t
RC
=min.)
I
CC2
: Standby Current (RAS=UCAS=LCAS=W=V
IH
)
I
CC3
* : RAS-only Refresh Current (UCAS=LCAS=V
IH
, RAS, Address cycling @t
RC
=min.)
I
CC4
* : Hyper Page Mode Current (RAS=V
IL
, UCAS or LCAS, Address cycling @t
HPC
=min.)
I
CC5
: Standby Current (RAS=UCAS=LCAS=W=V
CC
-0.2V)
I
CC6
* : CAS-Before-RAS Refresh Current (RAS, UCAS or LCAS cycling @t
RC
=min.)
I
CC7
: Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(V
IH
)=V
CC
-0.2V, Input low voltage(V
IL
)=0.2V, UCAS, LCAS=0.2V,
DQ=Don
t care, T
RC
=31.25us(4K/L-ver), 125us(1K/L-ver)
T
RAS
=T
RAS
min~300ns
I
CCS
: Self Refresh Current
RAS=UCAS=LCAS=V
IL
, W=OE=A0 ~ A11=V
CC
-0.2V or 0.2V,
DQ0 ~ DQ15=V
CC
-0.2V, 0.2V or Open
Symbol
Power
Speed
Max
Units
K4E171612D
K4E151612D
K4E171611D
K4E151611D
I
CC1
Don
t care
-45
-50
-60
100
90
80
150
140
130
100
90
80
150
140
130
mA
mA
mA
I
CC2
Normal
L
Don
t care
1
1
1
1
2
1
2
1
mA
mA
I
CC3
Don
t care
-45
-50
-60
100
90
80
150
140
130
100
90
80
150
140
130
mA
mA
mA
I
CC4
Don
t care
-45
-50
-60
110
100
90
110
100
90
110
100
90
110
100
90
mA
mA
mA
I
CC5
Normal
L
Don
t care
0.5
200
0.5
200
1
200
1
200
mA
uA
I
CC6
Don
t care
-45
-50
-60
100
90
80
150
140
130
110
90
80
150
140
130
mA
mA
mA
I
CC7
L
Don
t care
300
200
350
250
uA
I
CCS
L
Don
t care
150
150
200
200
uA
K4E171611D, K4E151611D
CMOS DRAM
K4E171612D, K4E151612D
CAPACITANCE
(T
A
=25
C, V
CC
=5V or 3.3V, f=1MHz)
Parameter
Symbol
Min
Max
Units
Input capacitance [A0 ~ A11]
C
IN1
-
5
pF
Input capacitance [RAS, UCAS, LCAS, W, OE]
C
IN2
-
7
pF
Output capacitance [DQ0 - DQ15]
C
DQ
-
7
pF
Test condition (5V device) : V
CC
=5.0V
10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V
Parameter
Symbol
-45
-50
-60
Units
Notes
Min
Max
Min
Max
Min
Max
Random read or write cycle time
t
RC
79
84
104
ns
Read-modify-write cycle time
t
RWC
105
115
140
ns
Access time from RAS
t
RAC
45
50
60
ns
3,4,10
Access time from CAS
t
CAC
14
15
17
ns
3,4,5
Access time from column address
t
AA
23/*20
25
30
ns
3,10
CAS to output in Low-Z
t
CLZ
3
3
3
ns
3
Output buffer turn-off delay from CAS
t
CEZ
3
13
3
13
3
15
ns
6,19
OE to output in Low-Z
t
OLZ
3
3
3
ns
3
Transition time (rise and fall)
t
T
2
50
2
50
2
50
ns
2
RAS precharge time
t
RP
30
30
40
ns
RAS pulse width
t
RAS
45
10K
50
10K
60
10K
ns
RAS hold time
t
RSH
13
13
17
ns
CAS hold time
t
CSH
36
40
50
ns
CAS pulse width
t
CAS
7 / *6.5
10K
8
10K
10
10K
ns
18
RAS to CAS delay time
t
RCD
19
31
20
35
20
43
ns
4
RAS to column address delay time
t
RAD
14
22
15
25
15
30
ns
10
CAS to RAS precharge time
t
CRP
5
5
5
ns
Row address set-up time
t
ASR
0
0
0
ns
Row address hold time
t
RAH
9
10
10
ns
Column address set-up time
t
ASC
0
0
0
ns
11
Column address hold time
t
CAH
7
8
10
ns
11
Column address to RAS lead time
t
RAL
23
25
30
ns
Read command set-up time
t
RCS
0
0
0
ns
Read command hold time referenced to CAS
t
RCH
0
0
0
ns
8
Read command hold time referenced to RAS
t
RRH
0
0
0
ns
8
Write command hold time
t
WCH
8
10
10
ns
Write command pulse width
t
WP
8
10
10
ns
Write command to RAS lead time
t
RWL
10
13
15
ns
Write command to CAS lead time
t
CWL
7
8
10
ns
14
AC CHARACTERISTICS
(0
C
T
A
70
C, See note 1,2)
Test condition (3.3V device) : V
CC
=3.3V
0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V
* KM416C1204DT-45 (5V, 1K Refresh) only
K4E171611D, K4E151611D
CMOS DRAM
K4E171612D, K4E151612D
AC CHARACTERISTICS
(Continued)
* KM416C1204DT-45 (5V, 1K Refresh) only
Parameter
Symbol
-45
-50
-60
Units
Notes
Min
Max
Min
Max
Min
Max
Data set-up time
t
DS
0
0
0
ns
9,17
Data hold time
t
DH
7
8
10
ns
9,17
Refresh period (1K, Normal)
t
REF
16
16
16
ms
Refresh period (4K, Normal)
t
REF
64
64
64
ms
Refresh period (L-ver)
t
REF
128
128
128
ms
Write command set-up time
t
WCS
0
0
0
ns
7
CAS to W delay time
t
CWD
28
32
36
ns
7,13
RAS to W delay time
t
RWD
59
67
79
ns
7
Column address W delay time
t
AWD
37
42
49
ns
7
CAS precharge to W delay time
t
CPWD
39
47
54
ns
7
CAS set-up time (CAS -before-RAS refresh)
t
CSR
5
5
5
ns
15
CAS hold time (CAS -before-RAS refresh)
t
CHR
10
10
10
ns
16
RAS to CAS precharge time
t
RPC
5
5
5
ns
Access time from CAS precharge
t
CPA
25
28
35
ns
3
Hyper Page mode cycle time
t
HPC
18
20
25
ns
18
Hyper Page read-modify-write cycle time
t
HPRWC
39
47
56
ns
18
CAS precharge time (Hyper Page cycle)
t
CP
7 / *6.5
8
10
ns
12
RAS pulse width (Hyper Page cycle)
t
RASP
45
200K
50
200K
60
200K
ns
RAS hold time from CAS precharge
t
RHCP
27
30
35
ns
OE access time
t
OEA
13
13
15
ns
3
OE to data delay
t
OED
10
13
15
ns
Output buffer turn off delay time from OE
t
OEZ
3
13
3
13
3
15
ns
6
OE command hold time
t
OEH
10
13
15
ns
Output data hold time
t
DOH
4
5
5
ns
Output buffer turn off delay from RAS
t
REZ
3
13
3
13
3
15
ns
6,19
Output buffer turn off delay from W
t
WEZ
3
13
3
13
3
15
ns
6
W to data delay
t
WED
15
15
15
ns
OE to CAS hold time
t
OCH
5
5
5
ns
CAS hold time to OE
t
CHO
5
5
5
ns
OE precharge time
t
OEP
5
5
5
ns
W pulse width (Hyper Page Cycle)
t
WPE
5
5
5
ns
RAS pulse width (C-B-R self refresh)
t
RASS
100
100
100
us
20,21,22
RAS precharge time (C-B-R self refresh)
t
RPS
79
90
110
ns
20,21,22
CAS hold time (C-B-R self refresh)
t
CHS
-50
-50
-50
ns
20,21,22
K4E171611D, K4E151611D
CMOS DRAM
K4E171612D, K4E151612D
NOTES
An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles
before proper device operation is achieved.
Input voltage levels are Vih/Vil. V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals.
Transition times are measured between V
IH
(min) and V
IL
(max) and are assumed to be 2ns for all inputs.
Measured with a load equivalent to 2 TTL(5V)/1TTL(3.3V) loads and 100pF.
Operation within the
t
RCD
(max) limit insures that
t
RAC
(max) can be met.
t
RCD
(max) is specified as a reference point only.
If
t
RCD
is greater than the specified
t
RCD
(max) limit, then access time is controlled exclusively by
t
CAC
.
Assumes that t
RCD
t
RCD
(max).
This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V
oh
or V
ol
.
t
WCS
,
t
RWD
,
t
CWD
,
t
AWD
and
t
CPWD
are non restrictive operating parameters. They are included in the data sheet as electrical
characteristics only. If
t
WCS
t
WCS
(min), the cycle is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If
t
CWD
t
CWD
(min),
t
RWD
t
RWD
(min),
t
AWD
t
AWD
(min) and
t
CPWD
t
CPWD
(min), then the cycle is a read-
modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions
is satisfied, the condition of the data out is indeterminate.
Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in OE controlled write cycle
and read-modify-write cycles.
Operation within the
t
RAD
(max) limit insures that
t
RAC
(max) can be met.
t
RAD
(max) is specified as a reference point only.
If
t
RAD
is greater than the specified
t
RAD
(max) limit, then access time is controlled by
t
AA
.
K4E17(5)1611(2)D Truth Table
RAS
LCAS
UCAS
W
OE
DQ0 - DQ7
DQ8-DQ15
STATE
H
X
X
X
X
Hi-Z
Hi-Z
Standby
L
H
H
X
X
Hi-Z
Hi-Z
Refresh
L
L
H
H
L
DQ-OUT
Hi-Z
Byte Read
L
H
L
H
L
Hi-Z
DQ-OUT
Byte Read
L
L
L
H
L
DQ-OUT
DQ-OUT
Word Read
L
L
H
L
H
DQ-IN
-
Byte Write
L
H
L
L
H
-
DQ-IN
Byte Write
L
L
L
L
H
DQ-IN
DQ-IN
Word Write
L
L
L
H
H
Hi-Z
Hi-Z
-
8.
6.
5.
10.
9.
3.
2.
1.
4.
7.
K4E171611D, K4E151611D
CMOS DRAM
K4E171612D, K4E151612D
t
ASC
, t
CAH
are referenced to the earlier CAS falling edge.
t
CP
is specified from the later CAS rising edge in the previous cycle to the earlier CAS falling edge in the next cycle.
t
CWD
is referenced to the later CAS falling edge at word read-modify-write cycle.
t
CWL
is specified from W falling edge to the earlier CAS rising edge.
t
CSR
is referenced to the earlier CAS falling edge before RAS transition low.
t
CHR
is referenced to the later CAS rising edge after RAS transition low.
t
CSR
t
CHR
RAS
LCAS
UCAS
22.
13.
19.
12.
11.
t
DS,
t
DH
is independently specified for lower byte DQ(0-7), upper byte DQ(8-15)
t
ASC
6ns, assume t
T
=2.0ns.
If RAS goes to high before CAS high going, the open circuit condition of the output is achieved by CAS high going.
If CAS goes to high before RAS high going, the open circuit condition of the output is achieved by RAS high going.
If
t
RASS
100us, then RAS precharge time must use
t
RPS
instead of
t
RP
.
For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K)/1024(1K) cycles of burst refresh must be executed
within 64ms/16ms before and after self refresh, in order to meet refresh specification.
For distributed CAS-before-RAS with 15.6us interval, CAS-before-RAS refresh should be executed with in 15.6us immediately
before and after self refresh in order to meet refresh specification.
18.
16.
15.
14.
21.
20.
17.
K4E171611D, K4E151611D
CMOS DRAM
K4E171612D, K4E151612D
t
CRP
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
V
OH
-
V
OL
-
DQ0 ~ DQ7
COLUMN
ADDRESS
ROW
ADDRESS
t
RAS
t
RC
t
CRP
t
RP
t
CSH
t
RSH
t
RCD
t
CAS
t
RAL
t
ASR
t
RAH
t
ASC
t
CAH
t
CRP
t
AA
t
OEA
t
CAC
t
CLZ
t
RAC
OPEN
t
CEZ
t
RCH
Don
t care
Undefined
LCAS
V
IH
-
V
IL
-
t
CRP
t
CSH
t
RSH
t
RCD
t
CAS
t
RAD
t
RRH
V
OH
-
V
OL
-
DQ8 ~ DQ15
t
CAC
t
CLZ
t
RAC
OPEN
DATA-OUT
DATA-OUT
t
CEZ
t
OEZ
t
OEZ
t
RCS
WORD READ CYCLE
t
OLZ
K4E171611D, K4E151611D
CMOS DRAM
K4E171612D, K4E151612D
NOTE : D
IN
= OPEN
LOWER BYTE READ CYCLE
RAS
V
IH
-
V
IL
-
LCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
V
OH
-
V
OL
-
DQ0 ~ DQ7
COLUMN
ADDRESS
ROW
ADDRESS
t
RAS
t
RC
t
RP
t
CSH
t
RSH
t
RCD
t
CAS
t
RAL
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
CRP
t
AA
t
OEA
t
CAC
t
CLZ
t
RAC
OPEN
DATA-OUT
t
OEZ
t
CEZ
t
RRH
t
RCH
Don
t care
Undefined
t
CRP
t
RPC
UCAS
V
IH
-
V
IL
-
OPEN
V
OH
-
V
OL
-
DQ8 ~ DQ15
t
RCS
t
OLZ
K4E171611D, K4E151611D
CMOS DRAM
K4E171612D, K4E151612D
NOTE : D
IN
= OPEN
UPPER BYTE READ CYCLE
RAS
V
IH
-
V
IL
-
LCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
V
OH
-
V
OL
-
DQ0 ~ DQ7
COLUMN
ADDRESS
ROW
ADDRESS
t
RAS
t
RC
t
CRP
t
RP
t
CSH
t
RSH
t
RCD
t
CAS
t
RAL
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
CRP
t
AA
t
OEA
t
CAC
t
CLZ
t
RAC
OPEN
DATA-OUT
t
OEZ
t
CEZ
t
RRH
t
RCH
Don
t care
Undefined
UCAS
V
IH
-
V
IL
-
OPEN
V
OH
-
V
OL
-
DQ8 ~ DQ15
t
CRP
t
RPC
t
RCS
t
OLZ
K4E171611D, K4E151611D
CMOS DRAM
K4E171612D, K4E151612D
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDRESS
t
RAS
t
RC
t
CRP
t
RP
t
CSH
t
RSH
t
RCD
t
CAS
t
RAL
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
CRP
Don
t care
WORD WRITE CYCLE ( EARLY WRITE )
NOTE : D
OUT
= OPEN
Undefined
LCAS
V
IH
-
V
IL
-
t
WCS
V
IH
-
V
IL
-
DQ0 ~ DQ7
t
DS
V
IH
-
V
IL
-
DQ8 ~ DQ15
t
CRP
t
CSH
t
RSH
t
RCD
t
CAS
t
CRP
t
WCH
t
WP
t
DH
DATA-IN
t
DS
t
DH
DATA-IN
K4E171611D, K4E151611D
CMOS DRAM
K4E171612D, K4E151612D
t
CRP
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDRESS
t
RAS
t
RC
t
RP
t
RAL
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
Don
t care
LOWER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : D
OUT
= OPEN
Undefined
LCAS
V
IH
-
V
IL
-
t
WCS
V
IH
-
V
IL
-
DQ0 ~ DQ7
t
DS
V
IH
-
V
IL
-
DQ8 ~ DQ15
t
CRP
t
CSH
t
RSH
t
RCD
t
CAS
t
WCH
t
WP
t
DH
DATA-IN
t
CRP
K4E171611D, K4E151611D
CMOS DRAM
K4E171612D, K4E151612D
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDRESS
t
RAS
t
RC
t
CRP
t
RP
t
CSH
t
RSH
t
RCD
t
CAS
t
RAL
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
CRP
Don
t care
UPPER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : D
OUT
= OPEN
Undefined
LCAS
V
IH
-
V
IL
-
t
WCS
V
IH
-
V
IL
-
DQ0 ~ DQ7
V
IH
-
V
IL
-
DQ8 ~ DQ15
t
WCH
t
WP
t
DS
t
DH
DATA-IN
t
CRP
K4E171611D, K4E151611D
CMOS DRAM
K4E171612D, K4E151612D
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
ROW
ADDRESS
t
RAS
t
RC
t
CRP
t
RP
t
CSH
t
RSH
t
RCD
t
CAS
t
RAL
t
RAD
t
ASR
t
RAH
t
ASC
t
CRP
Don
t care
WORD WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : D
OUT
= OPEN
Undefined
LCAS
V
IH
-
V
IL
-
V
IH
-
V
IL
-
DQ0 ~ DQ7
V
IH
-
V
IL
-
DQ8 ~ DQ15
t
CRP
t
RSH
t
RCD
t
CAS
t
CRP
t
RWL
t
WP
t
CWL
t
DH
t
DH
DATA-IN
COLUMN
ADDRESS
t
OEH
t
OED
t
DS
t
DS
DATA-IN
t
CSH
t
CAH
K4E171611D, K4E151611D
CMOS DRAM
K4E171612D, K4E151612D
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDRESS
t
RAS
t
RC
t
RP
t
RAL
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
Don
t care
LOWER BYTE WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : D
OUT
= OPEN
Undefined
LCAS
V
IH
-
V
IL
-
t
RWL
V
IH
-
V
IL
-
DQ0 ~ DQ7
t
DS
V
IH
-
V
IL
-
DQ8 ~ DQ15
t
CRP
t
CSH
t
RSH
t
RCD
t
CAS
t
CRP
t
WP
t
CWL
t
DH
DATA-IN
t
CRP
t
RPC
t
OEH
t
OED
K4E171611D, K4E151611D
CMOS DRAM
K4E171612D, K4E151612D
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDRESS
t
RAS
t
RC
t
CRP
t
RP
t
CSH
t
RSH
t
RCD
t
CAS
t
RAL
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
CRP
Don
t care
UPPER BYTE WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : D
OUT
= OPEN
Undefined
LCAS
V
IH
-
V
IL
-
V
IH
-
V
IL
-
V
IH
-
V
IL
-
t
CRP
t
RWL
t
WP
t
CWL
t
DS
t
DH
DATA-IN
t
OEH
t
OED
DQ0 ~ DQ7
DQ8 ~ DQ15
t
CRP
K4E171611D, K4E151611D
CMOS DRAM
K4E171612D, K4E151612D
t
RWL
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDR.
t
RAS
t
RWC
t
RP
t
RSH
t
RCD
t
CAS
t
CSH
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
CRP
Don
t care
WORD READ - MODIFY - WRITE CYCLE
Undefined
LCAS
V
IH
-
V
IL
-
V
I/OH
-
V
I/OL
-
DQ0 ~ DQ7
V
I/OH
-
V
I/OL
-
DQ8 ~ DQ15
t
WP
t
CWL
t
DS
t
DH
t
RSH
t
RCD
t
CAS
t
CRP
t
AWD
t
CWD
t
OEA
t
RWD
t
OED
t
OEZ
t
RAC
t
AA
t
OEZ
t
RAC
t
AA
t
DS
t
OED
t
DH
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
t
CAC
t
CLZ
t
CAC
t
CLZ
t
OLZ
t
OLZ
K4E171611D, K4E151611D
CMOS DRAM
K4E171612D, K4E151612D
t
RWL
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDR.
t
RAS
t
RWC
t
RP
t
CSH
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
CRP
Don
t care
LOWER-BYTE READ - MODIFY - WRITE CYCLE
Undefined
LCAS
V
IH
-
V
IL
-
V
I/OH
-
V
I/OL
-
DQ0 ~ DQ7
V
OH
-
V
OL
-
DQ8 ~ DQ15
t
WP
t
CWL
t
DS
t
DH
t
RSH
t
RCD
t
CAS
t
CRP
t
AWD
t
CWD
t
OEA
t
RWD
t
OED
t
OEZ
t
RAC
t
AA
VALID
DATA-OUT
VALID
DATA-IN
t
RPC
t
CAC
t
CLZ
OPEN
t
OLZ
K4E171611D, K4E151611D
CMOS DRAM
K4E171612D, K4E151612D
t
RWL
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDR
t
RAS
t
RWC
t
RP
t
RSH
t
RCD
t
CAS
t
CSH
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
CRP
Don
t care
UPPER-BYTE READ - MODIFY - WRITE CYCLE
Undefined
LCAS
V
IH
-
V
IL
-
V
OH
-
V
OL
-
DQ0 ~ DQ7
V
I/OH
-
V
I/OL
-
DQ8 ~ DQ15
t
WP
t
CWL
t
AWD
t
CWD
t
OEA
t
RWD
t
OEZ
t
RAC
t
AA
t
DS
t
OED
t
DH
VALID
DATA-OUT
VALID
DATA-IN
t
CRP
t
RPC
t
CAC
t
CLZ
OPEN
t
OLZ
K4E171611D, K4E151611D
CMOS DRAM
K4E171612D, K4E151612D
t
ASC
t
OLZ
t
CLZ
t
OLZ
t
CLZ
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDR
t
RASP
t
RP
t
RCD
t
CRP
Don
t care
HYPER PAGE MODE WORD READ CYCLE
Undefined
LCAS
V
IH
-
V
IL
-
V
OH
-
V
OL
-
DQ0 ~ DQ7
V
OH
-
V
OL
-
DQ8 ~ DQ15
COLUMN
ADDRESS
t
CAS
t
CAS
t
CAS
t
CAS
t
CP
t
CP
t
CP
t
REZ
t
HPC
t
HPC
t
HPC
t
RHCP
t
CSH
t
RCD
t
CRP
t
CAS
t
CAS
t
CAS
t
CAS
t
CP
t
CP
t
CP
t
RAD
t
RCS
t
OEA
t
RCH
t
RRH
COLUMN
ADDRESS
COLUMN
ADDR
t
OEZ
t
OEP
t
CHO
t
AA
t
CPA
t
AA
t
CAC
VALID
DATA-OUT
t
OEP
t
OEZ
t
RAC
t
CAC
t
DOH
VALID
DATA-OUT
VALID
DATA-OUT
t
OCH
t
CPA
t
AA
t
CAC
t
CAC
t
CPA
t
OEZ
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-OUT
t
OEP
t
OEZ
t
RAC
t
CAC
VALID
DATA-OUT
VALID
DATA-OUT
t
OEZ
VALID
DATA-OUT
VALID
DATA-OUT
t
DOH
t
OEA
t
ASR
t
RAH
t
ASC
t
CAH
t
ASC
t
CAH
t
CAH
t
CAH
t
ASC
t
RAL
K4E171611D, K4E151611D
CMOS DRAM
K4E171612D, K4E151612D
t
OEA
t
OLZ
t
CLZ
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDR
t
RASP
t
RP
t
CRP
Don
t care
HYPER PAGE MODE LOWER BYTE READ CYCLE
Undefined
LCAS
V
IH
-
V
IL
-
V
OH
-
V
OL
-
DQ0 ~ DQ7
V
OH
-
V
OL
-
DQ8 ~ DQ15
COLUMN
ADDRESS
t
REZ
t
RHCP
t
CSH
t
RCD
t
CAS
t
CAS
t
CAS
t
CAS
t
CP
t
CP
t
CP
t
RAD
t
RCS
t
RCH
t
RRH
COLUMN
ADDRESS
COLUMN
ADDR
t
OEZ
t
OEP
t
CHO
t
CPA
t
CAC
VALID
DATA-OUT
t
OEP
t
OEZ
t
RAC
t
CAC
t
DOH
VALID
DATA-OUT
VALID
DATA-OUT
t
OCH
t
CPA
t
CAC
t
CAC
t
CPA
t
OEZ
VALID
DATA-OUT
VALID
DATA-OUT
OPEN
t
RPC
t
ASR
t
RAH
t
ASC
t
CAH
t
ASC
t
CAH
t
CAH
t
ASC
t
CAH
t
ASC
t
AA
t
HPC
t
HPC
t
HPC
t
AA
t
AA
t
AA
t
OEA
t
RAL
K4E171611D, K4E151611D
CMOS DRAM
K4E171612D, K4E151612D
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDR.
t
RASP
t
RP
t
RCD
t
ASR
t
CRP
Don
t care
HYPER PAGE MODE UPPER BYTE READ CYCLE
Undefined
LCAS
V
IH
-
V
IL
-
V
OH
-
V
OL
-
DQ0 ~ DQ7
V
OH
-
V
OL
-
DQ8 ~ DQ15
COLUMN
ADDRESS
t
CAS
t
CAS
t
CAS
t
CAS
t
CP
t
CP
t
CP
t
REZ
t
HPC
t
HPC
t
HPC
t
RHCP
t
CSH
t
CRP
t
RAH
t
ASC
t
CAH
t
CAH
t
CAH
t
ASC
t
CAH
t
RCS
t
OEA
t
RCH
t
RRH
COLUMN
ADDRESS
COLUMN
ADDR.
t
OEZ
t
OEP
t
CHO
t
CPA
t
CAC
VALID
DATA-OUT
t
OEP
t
OEZ
t
RAC
t
CAC
t
OLZ
t
CLZ
t
DOH
VALID
DATA-OUT
VALID
DATA-OUT
t
OCH
t
CPA
t
CAC
t
CAC
t
CPA
t
OEZ
VALID
DATA-OUT
VALID
DATA-OUT
OPEN
t
ASC
t
RPC
t
RPC
t
RAD
t
ASC
t
AA
t
AA
t
AA
t
OEA
t
RAL
K4E171611D, K4E151611D
CMOS DRAM
K4E171612D, K4E151612D
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDR
t
RASP
t
RP
t
RCD
t
ASR
t
CRP
Don
t care
HYPER PAGE MODE WORD WRITE CYCLE ( EARLY WRITE )
Undefined
LCAS
V
IH
-
V
IL
-
V
IH
-
V
IL
-
DQ0 ~ DQ7
V
IH
-
V
IL
-
DQ8 ~ DQ15
t
CRP
t
HPC
t
RHCP
t
RAD
t
RAH
t
CAH
t
CAH
t
ASC
t
CAH
t
ASC
VALID
DATA-IN
t
DS
COLUMN
ADDRESS
COLUMN
ADDRESS
t
CAS
t
CP
t
CAS
t
CP
t
CAS
t
RSH
t
RCD
t
CRP
t
HPC
t
HPC
t
CAS
t
CP
t
CAS
t
CP
t
CAS
t
RSH
t
CSH
t
ASC
t
WP
t
WCS
t
WCH
t
WP
t
WCS
t
WCH
t
WP
t
WCS
t
WCH
VALID
DATA-IN
VALID
DATA-IN
t
DH
t
DS
t
DH
t
DS
t
DH
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
t
DH
t
DH
t
DH
t
DS
t
DS
t
DS
NOTE : D
OUT
= OPEN
t
HPC
t
RAL
K4E171611D, K4E151611D
CMOS DRAM
K4E171612D, K4E151612D
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDR
t
RASP
t
RP
t
ASR
t
CRP
Don
t care
HYPER PAGE MODE LOWER BYTE WRITE CYCLE ( EARLY WRITE )
Undefined
LCAS
V
IH
-
V
IL
-
V
IH
-
V
IL
-
DQ0 ~ DQ7
V
IH
-
V
IL
-
DQ8 ~ DQ15
t
RPC
t
RHCP
t
RAD
t
RAH
t
CAH
t
CAH
t
ASC
t
CAH
t
ASC
VALID
DATA-IN
t
DS
COLUMN
ADDRESS
COLUMN
ADDRESS
t
RCD
t
CRP
t
HPC
t
HPC
t
CAS
t
CP
t
CAS
t
CP
t
CAS
t
RSH
t
CSH
t
ASC
t
WP
t
WCS
t
WCH
t
WP
t
WCS
t
WCH
t
WP
t
WCS
t
WCH
VALID
DATA-IN
VALID
DATA-IN
t
DH
t
DS
t
DH
t
DS
t
DH
NOTE : D
OUT
= OPEN
t
RAL
K4E171611D, K4E151611D
CMOS DRAM
K4E171612D, K4E151612D
t
WCS
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDR
t
RASP
t
RP
t
ASR
t
CRP
Don
t care
HYPER PAGE MODE UPPER BYTE WRITE CYCLE ( EARLY WRITE )
Undefined
LCAS
V
IH
-
V
IL
-
V
IH
-
V
IL
-
DQ0 ~ DQ7
V
IH
-
V
IL
-
DQ8 ~ DQ15
t
RPC
t
RHCP
t
RAD
t
RAH
t
CAH
t
CAH
t
ASC
t
CAH
t
ASC
VALID
DATA-IN
t
DS
COLUMN
ADDRESS
COLUMN
ADDRESS
t
RCD
t
CRP
t
HPC
t
HPC
t
CAS
t
CP
t
CAS
t
CP
t
CAS
t
RSH
t
CSH
t
ASC
t
WP
t
WCH
t
WP
t
WCS
t
WCH
t
WP
t
WCS
t
WCH
VALID
DATA-IN
VALID
DATA-IN
t
DH
t
DS
t
DH
t
DS
t
DH
NOTE : D
OUT
= OPEN
t
RAL
K4E171611D, K4E151611D
CMOS DRAM
K4E171612D, K4E151612D
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
V
I/OH
-
V
I/OL
-
DQ0 ~ DQ7
ROW
ADDR
t
CSH
t
RASP
t
RP
t
ASR
Don
t care
HYPER PAGE MODE WORD READ - MODIFY - WRITE CYCLE
Undefined
t
RCD
t
CP
t
RAD
t
CAH
t
WP
t
DH
COL.
ADDR
COL.
ADDR
t
CAS
t
CAS
t
CRP
t
ASC
t
CAH
t
RAL
t
RCS
t
CWL
t
CWD
t
AWD
t
RWD
t
WP
t
CWD
t
AWD
t
CWL
t
AA
t
RAC
t
OEA
t
CLZ
t
CAC
t
OEZ
t
CPWD
t
OED
t
ASC
t
CLZ
t
OEA
t
CAC
t
AA
t
DH
t
OED
LCAS
V
IH
-
V
IL
-
t
RCD
t
CP
t
CAS
t
CAS
t
CRP
t
CRP
t
CRP
V
I/OH
-
V
I/OL
-
DQ8 ~ DQ15
VALID
DATA-OUT
t
DH
t
AA
t
RAC
t
CLZ
t
CAC
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
t
CLZ
t
CAC
t
AA
t
DH
t
OEZ
t
OED
t
DS
t
DS
t
DS
t
OED
t
OEZ
t
OEZ
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
t
DS
t
HPRWC
t
RSH
t
RWL
t
RCS
t
RAH
K4E171611D, K4E151611D
CMOS DRAM
K4E171612D, K4E151612D
t
ASC
RAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
V
I/OH
-
V
I/OL
-
DQ0 ~ DQ7
ROW
ADDR
t
CSH
t
RASP
t
RP
t
ASR
Don
t care
HYPER PAGE MODE LOWER BYTE READ - MODIFY - WRITE CYCLE
Undefined
t
RAD
t
CAH
t
WP
t
DH
COL.
ADDR
COL.
ADDR
t
ASC
t
CAH
t
RAL
t
RCS
t
CWL
t
CWD
t
AWD
t
RWD
t
WP
t
CWD
t
AWD
t
CWL
t
AA
t
RAC
t
OEA
t
CLZ
t
CAC
t
OEZ
t
CPWD
t
OED
t
CLZ
t
OEA
t
CAC
t
AA
t
DH
t
OED
t
RWL
t
RCD
t
CP
t
CAS
t
CAS
t
CRP
t
CRP
t
CRP
V
I/OH
-
V
I/OL
-
DQ8 ~ DQ15
t
DS
t
OEZ
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
t
DS
t
RPC
t
RSH
OPEN
LCAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
t
HPRWC
t
RCS
t
OLZ
t
OLZ
t
RAH
K4E171611D, K4E151611D
CMOS DRAM
K4E171612D, K4E151612D
t
ASC
t
CRP
RAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
V
I/OH
-
V
I/OL
-
DQ0 ~ DQ7
ROW
ADDR
t
CSH
t
RASP
t
RP
t
ASR
Don
t care
HYPER PAGE MODE UPPER BYTE READ - MODIFY - WRITE CYCLE
Undefined
t
RAD
t
CAH
t
WP
t
DH
COL.
ADDR
COL.
ADDR
t
CAH
t
RAL
t
RCS
t
CWL
t
CWD
t
AWD
t
RWD
t
WP
t
CWD
t
AWD
t
CWL
t
AA
t
RAC
t
OEA
t
CLZ
t
CAC
t
OEZ
t
CPWD
t
OED
t
CLZ
t
OEA
t
CAC
t
AA
t
DH
t
OED
t
RWL
t
RCD
t
CP
t
CAS
t
CAS
t
CRP
t
CRP
V
I/OH
-
V
I/OL
-
DQ8 ~ DQ15
t
DS
t
OEZ
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
t
DS
t
RPC
t
RSH
OPEN
LCAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
t
HPRWC
t
ASC
t
RCS
t
RAH
t
OLZ
t
OLZ
K4E171611D, K4E151611D
CMOS DRAM
K4E171612D, K4E151612D
HYPER PAGE READ AND WRITE MIXED CYCLE
RAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDR
t
RASP
t
RP
Don
t care
Undefined
V
I/OH
-
V
I/OL
-
DQ0 ~ DQ7
t
WEZ
t
CP
t
HPC
t
HPC
t
HPC
t
RCD
t
RAH
t
ASC
t
CAH
t
CAH
t
CAH
t
ASC
t
CAH
t
RCH
t
RCS
t
RCS
t
RCH
t
ASC
COLUMN
ADDRESS
COL.
ADDR
VALID
DATA-OUT
t
REZ
t
AA
t
WCS
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-IN
t
RAC
COL.
ADDR
t
CAS
t
ASR
t
CAS
t
CAS
t
CAS
t
ASC
t
CP
t
RCH
t
WCH
t
WPE
t
CLZ
t
CPA
t
WED
t
AA
t
WEZ
t
DS
t
DH
t
CAC
t
OEA
t
CP
t
HPC
t
HPC
t
CAS
t
CAS
t
CAS
t
CAS
t
CP
V
I/OH
-
V
I/OL
-
DQ8 ~ DQ15
t
WEZ
VALID
DATA-OUT
t
REZ
t
AA
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-IN
t
RAC
t
AA
t
WEZ
t
DS
t
DH
t
CAC
t
OEA
LCAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
t
CP
t
HPC
t
CP
READ(
t
CAC
)
READ(
t
CPA
)
WRITE
READ(
t
AA
)
t
RAD
t
RHCP
t
RAL
K4E171611D, K4E151611D
CMOS DRAM
K4E171612D, K4E151612D
t
CRP
OPEN
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
ROW
ADDR
t
RC
t
RP
t
ASR
t
CRP
RAS - ONLY REFRESH CYCLE
LCAS
V
IH
-
V
IL
-
t
RAS
t
RAH
NOTE : W, OE , D
IN
= Don
t care
D
OUT
= OPEN
t
RPC
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE, A = Don
t care
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
t
RC
t
RP
LCAS
V
IH
-
V
IL
-
t
RAS
t
RPC
t
CP
t
RPC
t
CSR
t
CHR
t
CP
t
CSR
t
CHR
t
CEZ
OPEN
V
OH
-
V
OL
-
DQ0 ~ DQ7
V
OH
-
V
OL
-
DQ8 ~ DQ15
Don
t care
t
RP
Undefined
K4E171611D, K4E151611D
CMOS DRAM
K4E171612D, K4E151612D
t
OEZ
DATA-IN
DATA-OUT
t
RP
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
ROW
ADDRESS
t
RAS
t
RC
t
CHR
t
RCD
t
RSH
t
RAD
t
ASR
t
RAH
t
ASC
t
CRP
Don
t care
HIDDEN REFRESH CYCLE ( READ )
Undefined
LCAS
V
IH
-
V
IL
-
V
OH
-
V
OL
-
DQ0 ~ DQ7
V
OH
-
V
OL
-
DQ8 ~ DQ15
t
RSH
t
RCD
t
CRP
t
WRH
COLUMN
ADDRESS
t
OEA
t
RAS
t
RC
t
CHR
t
CAH
t
RCS
t
AA
t
RAC
t
CLZ
t
CAC
DATA-OUT
t
CEZ
OPEN
OPEN
t
RP
t
REZ
t
WEZ
t
OLZ
t
RAL
K4E171611D, K4E151611D
CMOS DRAM
K4E171612D, K4E151612D
t
WCS
t
RP
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
ROW
ADDRESS
t
RAS
t
RC
t
CHR
t
RCD
t
RSH
t
RAD
t
ASR
t
RAH
t
ASC
t
CRP
Don
t care
HIDDEN REFRESH CYCLE ( WRITE )
Undefined
LCAS
V
IH
-
V
IL
-
V
IH
-
V
IL
-
DQ0 ~ DQ7
V
IH
-
V
IL
-
DQ8 ~ DQ15
t
RSH
t
RCD
t
CRP
t
WRH
COLUMN
ADDRESS
t
RAS
t
RC
t
CHR
t
CAH
t
WRP
t
DS
NOTE : D
OUT
= OPEN
t
WP
t
WCH
DATA-IN
t
DH
t
DS
DATA-IN
t
DH
t
RP
K4E171611D, K4E151611D
CMOS DRAM
K4E171612D, K4E151612D
OPEN
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE , A = Don
t care
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
t
RPS
LCAS
V
IH
-
V
IL
-
t
RASS
t
RPC
t
CP
t
RPC
t
CSR
t
CEZ
OPEN
V
OH
-
V
OL
-
DQ0 ~ DQ7
V
OH
-
V
OL
-
DQ8 ~ DQ15
t
CHS
t
CP
t
CSR
t
CHS
t
RP
Don
t care
Undefined
K4E171611D, K4E151611D
CMOS DRAM
K4E171612D, K4E151612D
42 SOJ
400mil
0
.
4
0
0

(
1
0
.
1
6
)
0
.
4
3
5

(
1
1
.
0
6
)
0
.
4
4
5

(
1
1
.
3
0
)
1.080 (27.43)
1.070 (27.19)
MAX
1.091 (27.71)
M
A
X
0
.
1
4
8

(
3
.
7
6
)
0.032 (0.81)
0.026 (0.66)
0.021 (0.53)
0.015 (0.38)
0.027 (0.69)
0.012 (0.30)
0.006 (0.15)
0
.
3
6
0

(
9
.
1
5
)
0
.
3
8
0

(
9
.
6
5
)
MIN
#42
#1
0.0375 (0.95)
0.050 (1.27)
Units : Inches (millimeters)
50(44) TSOP(II) 400mil
Units : Inches (millimeters)
MAX
0.047 (1.20)
MIN
0.002 (0.05)
0.018 (0.45)
0.010 (0.25)
0.0315 (0.80)
0.034 (0.875)
0.821 (20.85)
0.829 (21.05)
0.841 (21.35)
MAX
0.010 (0.25)
0.004 (0.10)
0
.
4
0
0

(
1
0
.
1
6
)
0
.
4
7
1

(
1
1
.
9
6
)
0
.
4
5
5

(
1
1
.
5
6
)
0~8
0.030 (0.75)
0.018 (0.45)
TYP
0.010 (0.25)
O
PACKAGE DIMENSION