K4E170811C, K4E160811C
CMOS DRAM
K4E170812C, K4E160812C
This is a family of 2,097,152 x 8 bit Extended Data Out CMOS DRAMs. Extended Data Out Mode offers high speed random access of
memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+5.0V or +3.3V), refresh cycle (2K Ref. or 4K
Ref.), access time (-50 or -60), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of
this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh
operation is available in L-version. This 2Mx8 EDO Mode DRAM family is fabricated using Samsung
s advanced CMOS process to real-
ize high band-width, low power consumption and high reliability. It may be used as graphic memory unit for microcomputer and personal
computer.
Part Identification
- K4E170811C-B(F) (5V, 4K Ref.)
- K4E160811C-B(F) (5V, 2K Ref.)
- K4E170812C-B(F) (3.3V, 4K Ref.)
- K4E160812C-B(F) (3.3V, 2K Ref.)
Extended Data Out Mode operation
(Fast page mode with Extended Data Out)
CAS-before-RAS refresh capability
RAS-only and Hidden refresh capability
Self-refresh capability (L-ver only)
Fast parallel test mode capability
TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
Early Write or output enable controlled write
JEDEC Standard pinout
Available in Plastic SOJ and TSOP(II) packages
Single +5V
10% power supply (5V product)
Single +3.3V
0.3V power supply (3.3V product)
Control
Clocks
RAS
CAS
W
Vcc
Vss
DQ0
to
DQ7
A0-A11
(A0 - A10)
*1
A0 - A8
(A0 - A9)
*1
Memory Array
2,097,152 x8
Cells
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
2M x 8Bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Refresh Cycles
Part
NO.
V
CC
Refresh
cycle
Refresh period
Normal
L-ver
K4E170811C
5V
4K
64ms
128ms
K4E170812C
3.3V
K4E160811C
5V
2K
32ms
K4E160812C
3.3V
Performance Range
Speed
t
RAC
t
CAC
t
RC
t
HPC
Remark
-50
50ns
13ns
84ns
20ns
5V/3.3V
-60
60ns
15ns
104ns
25ns
5V/3.3V
Active Power Dissipation
Speed
3.3V
5V
4K
2K
4K
2K
-50
324
396
495
605
-60
288
360
440
550
Unit : mW
S
e
n
s
e
A
m
p
s
&
I
/
O
Data out
Buffer
Data in
Buffer
OE
Note)
*1
: 2K Refresh
Col. Address Buffer
Row Address Buffer
Refresh Counter
Refresh Control
Refresh Timer
Column Decoder
Row Decoder
VBB Generator
K4E170811C, K4E160811C
CMOS DRAM
K4E170812C, K4E160812C
V
CC
DQ0
DQ1
DQ2
DQ3
W
RAS
*A11(N.C)
A10
A0
A1
A2
A3
V
CC
V
SS
DQ7
DQ6
DQ5
DQ4
CAS
OE
A9
A8
A7
A6
A5
A4
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PIN CONFIGURATION (Top Views)
Pin Name
Pin Function
A0 - A11
Address Inputs (4K Product)
A0 - A10
Address Inputs (2K Product)
DQ0 - 7
Data In/Out
V
SS
Ground
RAS
Row Address Strobe
CAS
Column Address Strobe
W
Read/Write Input
OE
Data Output Enable
V
CC
Power(+5V)
Power(+3.3V)
N.C
No Connection (2K Ref. product)
V
CC
DQ0
DQ1
DQ2
DQ3
W
RAS
*A11(N.C)
A10
A0
A1
A2
A3
V
CC
V
SS
DQ7
DQ6
DQ5
DQ4
CAS
OE
A9
A8
A7
A6
A5
A4
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
*A11 is N.C for K4E160811(2)C(5V/3.3V, 2K Ref. product)
B : 300mil 28 SOJ
F : 300mil 28 TSOP II
K4E17(6)0811(2)C-B
K4E17(6)0811(2)C-F
K4E170811C, K4E160811C
CMOS DRAM
K4E170812C, K4E160812C
ABSOLUTE MAXIMUM RATINGS
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted
to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Parameter
Symbol
Rating
Units
3.3V
5V
Voltage on any pin relative to V
SS
V
IN,
V
OUT
-0.5 to +4.6
-1.0 to +7.0
V
Voltage on V
CC
supply relative to V
SS
V
CC
-0.5 to +4.6
-1.0 to +7.0
V
Storage Temperature
Tstg
-55 to +150
-55 to +150
C
Power Dissipation
P
D
1
1
W
Short Circuit Output Current
I
OS
Address
50
50
mA
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to Vss, T
A
= 0 to 70
C)
*1 : V
CC
+1.3V/15ns(3.3V), V
CC
+2.0V/20ns(5V), Pulse width is measured at V
CC
*2 : -1.3V/15ns(3.3V), -2.0V/20ns(5V), Pulse width is measured at V
SS
Parameter
Symbol
3.3V
5V
Units
Min
Typ
Max
Min
Typ
Max
Supply Voltage
V
CC
3.0
3.3
3.6
4.5
5.0
5.5
V
Ground
V
SS
0
0
0
0
0
0
V
Input High Voltage
V
IH
2.0
-
V
CC
+0.3
*1
2.4
-
V
CC
+1.0
*1
V
Input Low Voltage
V
IL
-0.3
*2
-
0.8
-1.0
*2
-
0.8
V
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Max
Parameter
Symbol
Min
Max
Units
3.3V
Input Leakage Current (Any input 0
V
IN
V
IN
+0.3V,
all other input pins not under test=0 Volt)
I
I(L)
-5
5
uA
Output Leakage Current
(Data out is disabled, 0V
V
OUT
V
CC
)
I
O(L)
-5
5
uA
Output High Voltage Level(I
OH
=-2mA)
V
OH
2.4
-
V
Output Low Voltage Level(I
OL
=2mA)
V
OL
-
0.4
V
5V
Input Leakage Current (Any input 0
V
IN
V
IN
+0.5V,
all other input pins not under test=0 Volt)
I
I(L)
-5
5
uA
Output Leakage Current
(Data out is disabled, 0V
V
OUT
V
CC
)
I
O(L)
-5
5
uA
Output High Voltage Level(I
OH
=-5mA)
V
OH
2.4
-
V
Output Low Voltage Level(I
OL
=4.2mA)
V
OL
-
0.4
V
K4E170811C, K4E160811C
CMOS DRAM
K4E170812C, K4E160812C
*Note :
I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
, I
CC3
and I
CC6,
address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one Hyper page mode cycle time, t
HPC
.
DC AND OPERATING CHARACTERISTICS
(Continued)
I
CC1
* : Operating Current (RAS and CAS cycling @t
RC
=min.)
I
CC2
: Standby Current (RAS=CAS=W=V
IH
)
I
CC3
* : RAS-only Refresh Current (CAS=V
IH
, RAS cycling @t
RC
=min.)
I
CC4
* : Hyper Page Mode Current (RAS=V
IL
, CAS, Address cycling @t
HPC
=min.)
I
CC5
: Standby Current (RAS=CAS=W=V
CC
-0.2V)
I
CC6
* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @t
RC
=min.)
I
CC7
: Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(V
IH
)=V
CC
-0.2V, Input low voltage(V
IL
)=0.2V, CAS=0.2V,
DQ=Don
t care, T
RC
=31.25us(4K/L-ver), 62.5us(2K/L-ver),
T
RAS
=T
RAS
min~300ns
I
CCS
: Self Refresh Current
RAS=CAS=V
IL
, W=OE=A0 ~ A11=V
CC
-0.2V or 0.2V,
DQ0 ~ DQ7=V
CC
-0.2V, 0.2V or Open
Symbol
Power
Speed
Max
Units
K4E170812C
K4E160812C
K4E170811C
K4E160811C
I
CC1
Don
t care
-50
-60
90
80
110
100
90
80
110
100
mA
mA
mA
I
CC2
Normal
L
Don
t care
1
1
1
1
2
1
2
1
mA
mA
I
CC3
Don
t care
-50
-60
90
80
110
100
90
80
110
100
mA
mA
mA
I
CC4
Don
t care
-50
-60
80
70
90
80
80
70
90
80
mA
mA
mA
I
CC5
Normal
L
Don
t care
0.5
200
0.5
200
1
250
1
250
mA
uA
I
CC6
Don
t care
-50
-60
90
80
110
100
90
80
110
100
mA
mA
mA
I
CC7
L
Don
t care
250
250
300
300
uA
I
CCS
L
Don
t care
200
200
250
250
uA
K4E170811C, K4E160811C
CMOS DRAM
K4E170812C, K4E160812C
CAPACITANCE
(T
A
=25
C, V
CC
=5V or 3.3V, f=1MHz)
Parameter
Symbol
Min
Max
Units
Input capacitance [A0 ~ A11]
C
IN1
-
5
pF
Input capacitance [RAS, CAS, W, OE]
C
IN2
-
7
pF
Output capacitance [DQ0 - DQ7]
C
DQ
-
7
pF
Test condition (5V device) : V
CC
=5.0V
10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V
Parameter
Symbol
-50
-60
Units
Notes
Min
Max
Min
Max
Random read or write cycle time
t
RC
84
104
ns
Read-modify-write cycle time
t
RWC
116
140
ns
Access time from RAS
t
RAC
50
60
ns
3,4,10
Access time from CAS
t
CAC
13
15
ns
3,4,5
Access time from column address
t
AA
25
30
ns
3,10
CAS to output in Low-Z
t
CLZ
3
3
ns
3
Output buffer turn-off delay from CAS
t
CEZ
3
13
3
15
ns
6,14
OE to output in Low-Z
t
OLZ
3
3
ns
3
Transition time (rise and fall)
t
T
2
50
2
50
ns
2
RAS precharge time
t
RP
30
40
ns
RAS pulse width
t
RAS
50
10K
60
10K
ns
RAS hold time
t
RSH
13
15
ns
CAS hold time
t
CSH
38
45
ns
CAS pulse width
t
CAS
8
10K
10
10K
ns
RAS to CAS delay time
t
RCD
20
37
20
45
ns
4
RAS to column address delay time
t
RAD
15
25
15
30
ns
10
CAS to RAS precharge time
t
CRP
5
5
ns
Row address set-up time
t
ASR
0
0
ns
Row address hold time
t
RAH
10
10
ns
Column address set-up time
t
ASC
0
0
ns
Column address hold time
t
CAH
8
10
ns
Column address to RAS lead time
t
RAL
25
30
ns
Read command set-up time
t
RCS
0
0
ns
Read command hold time referenced to CAS
t
RCH
0
0
ns
8
Read command hold time referenced to RAS
t
RRH
0
0
ns
8
Write command hold time
t
WCH
10
10
ns
Write command pulse width
t
WP
10
10
ns
Write command to RAS lead time
t
RWL
13
15
ns
Write command to CAS lead time
t
CWL
8
10
ns
AC CHARACTERISTICS
(0
C
T
A
70
C, See note 1,2)
Test condition (3.3V device) : V
CC
=3.3V
0.3V, Vih/Vil=2.0/0.8V, Voh/Vol=2.0/0.8V
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