K4E170811D, K4E160811D

CMOS DRAM

K4E170812D, K4E160812D

This is a family of 2,097,152 x 8 bit Extended Data Out CMOS DRAMs. Extended Data Out Mode offers high speed random access of

memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+5.0V or +3.3V), refresh cycle (2K Ref. or 4K

Ref.), access time (-50 or -60), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of

this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh

operation is available in L-version. This 2Mx8 EDO Mode DRAM family is fabricated using Samsung

s advanced CMOS process to real-

ize high band-width, low power consumption and high reliability. It may be used as graphic memory unit for microcomputer and personal

computer.

· Part Identification

- K4E170811D-B(F) (5V, 4K Ref.)
- K4E160811D-B(F) (5V, 2K Ref.)
- K4E170812D-B(F) (3.3V, 4K Ref.)
- K4E160812D-B(F) (3.3V, 2K Ref.)

· Extended Data Out Mode operation

(Fast page mode with Extended Data Out)

· CAS-before-RAS refresh capability

· RAS-only and Hidden refresh capability

· Self-refresh capability (L-ver only)

· Fast parallel test mode capability

· TTL(5V)/LVTTL(3.3V) compatible inputs and outputs

· Early Write or output enable controlled write

· JEDEC Standard pinout

· Available in Plastic SOJ and TSOP(II) packages

· Single +5V

10% power supply (5V product)

· Single +3.3V

0.3V power supply (3.3V product)

Control
Clocks

RAS
CAS

Vcc
Vss

DQ0

DQ7

A0-A11

(A0 - A10)

A0 - A8

(A0 - A9)

Memory Array

2,097,152 x8

Cells

SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.

2M x 8Bit CMOS Dynamic RAM with Extended Data Out

DESCRIPTION

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Refresh Cycles

Part
NO.

Refresh

cycle

Refresh period

Normal

L-ver

K4E170811D

64ms

128ms

K4E170812D

3.3V

K4E160811D

32ms

K4E160812D

3.3V

Performance Range

Speed

RAC

CAC

HPC

Remark

-50

50ns

13ns

84ns

20ns

5V/3.3V

-60

60ns

15ns

104ns

25ns

5V/3.3V

Active Power Dissipation

Speed

3.3V

-50

324

396

495

605

-60

288

360

440

550

Unit : mW

I
/
O

Data out

Buffer

Data in

Buffer

Note)

: 2K Refresh

Col. Address Buffer

Row Address Buffer

Refresh Counter

Refresh Control

Refresh Timer

Column Decoder

Row Decoder

VBB Generator

K4E170811D, K4E160811D

CMOS DRAM

K4E170812D, K4E160812D

DQ0
DQ1
DQ2
DQ3

RAS

*A11(N.C)

A10

A0
A1
A2
A3

DQ7
DQ6
DQ5
DQ4
CAS
OE
A9
A8
A7
A6
A5
A4
V

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

PIN CONFIGURATION (Top Views)

Pin Name

Pin Function

A0 - A11

Address Inputs (4K Product)

A0 - A10

Address Inputs (2K Product)

DQ0 - 7

Data In/Out

Ground

RAS

Row Address Strobe

CAS

Column Address Strobe

Read/Write Input

Data Output Enable

Power(+5V)

Power(+3.3V)

N.C

No Connection (2K Ref. product)

DQ0
DQ1
DQ2
DQ3

RAS

*A11(N.C)

A10

A0
A1
A2
A3

DQ7
DQ6
DQ5
DQ4
CAS
OE
A9
A8
A7
A6
A5
A4
V

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

*A11 is N.C for K4E160811(2)D(5V/3.3V, 2K Ref. product)

B : 300mil 28 SOJ
F : 300mil 28 TSOP II

· K4E17(6)0811(2)D-B

· K4E17(6)0811(2)D-F

K4E170811D, K4E160811D

CMOS DRAM

K4E170812D, K4E160812D

ABSOLUTE MAXIMUM RATINGS

* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted

to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Parameter

Symbol

Rating

Units

3.3V

Voltage on any pin relative to V

IN,

OUT

-0.5 to +4.6

-1.0 to +7.0

Voltage on V

supply relative to V

-0.5 to +4.6

-1.0 to +7.0

Storage Temperature

Tstg

-55 to +150

Power Dissipation

Short Circuit Output Current

Address

RECOMMENDED OPERATING CONDITIONS

(Voltage referenced to Vss, T

= 0 to 70

*1 : V

+1.3V/15ns(3.3V), V

+2.0V/20ns(5V), Pulse width is measured at V

*2 : -1.3V/15ns(3.3V), -2.0V/20ns(5V), Pulse width is measured at V

Parameter

Symbol

3.3V

Units

Min

Typ

Max

Min

Typ

Max

Supply Voltage

3.0

3.3

3.6

4.5

5.0

5.5

Ground

Input High Voltage

2.0

+0.3

2.4

+1.0

Input Low Voltage

-0.3

0.8

-1.0

0.8

DC AND OPERATING CHARACTERISTICS

(Recommended operating conditions unless otherwise noted.)

Max

Parameter

Symbol

Min

Max

Units

3.3V

Input Leakage Current (Any input 0

+0.3V,

all other input pins not under test=0 Volt)

I(L)

-5

Output Leakage Current
(Data out is disabled, 0V

OUT

)

O(L)

-5

Output High Voltage Level(I

=-2mA)

2.4

Output Low Voltage Level(I

=2mA)

0.4

Input Leakage Current (Any input 0

+0.5V,

all other input pins not under test=0 Volt)

I(L)

-5

Output Leakage Current
(Data out is disabled, 0V

OUT

)

O(L)

-5

Output High Voltage Level(I

=-5mA)

2.4

Output Low Voltage Level(I

=4.2mA)

0.4

K4E170811D, K4E160811D

CMOS DRAM

K4E170812D, K4E160812D

*Note :

CC1

, I

CC3

, I

CC4

and I

CC6

are dependent on output loading and cycle rates. Specified values are obtained with the output open.

is specified as an average current. In I

CC1

, I

CC3

and I

CC6,

address can be changed maximum once while RAS=V

. In I

CC4

address can be changed maximum once within one Hyper page mode cycle time, t

HPC

DC AND OPERATING CHARACTERISTICS

(Continued)

CC1

* : Operating Current (RAS and CAS cycling @t

=min.)

CC2

: Standby Current (RAS=CAS=W=V

)

CC3

* : RAS-only Refresh Current (CAS=V

, RAS cycling @t

=min.)

CC4

* : Hyper Page Mode Current (RAS=V

, CAS, Address cycling @t

HPC

=min.)

CC5

: Standby Current (RAS=CAS=W=V

-0.2V)

CC6

* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @t

=min.)

CC7

: Battery back-up current, Average power supply current, Battery back-up mode

Input high voltage(V

)=V

-0.2V, Input low voltage(V

)=0.2V, CAS=0.2V,

DQ=Don

t care, T

=31.25us(4K/L-ver), 62.5us(2K/L-ver),

RAS

min~300ns

CCS

: Self Refresh Current

RAS=CAS=V

, W=OE=A0 ~ A11=V

-0.2V or 0.2V,

DQ0 ~ DQ7=V

-0.2V, 0.2V or Open

Symbol

Power

Speed

Max

Units

K4E170812D

K4E160812D

K4E170811D

K4E160811D

CC1

Don

t care

-50
-60

90
80

110
100

90
80

110

100

mA
mA

CC2

Normal

Don

t care

1
1

2
1

mA
mA

CC3

Don

t care

-50
-60

90
80

110
100

90
80

110

100

mA
mA

CC4

Don

t care

-50
-60

80
70

90
80

80
70

90
80

mA
mA

CC5

Normal

Don

t care

0.5

200

0.5

200

250

CC6

Don

t care

-50
-60

90
80

110
100

90
80

110

100

mA
mA

CC7

Don

t care

250

300

CCS

Don

t care

200

250

K4E170811D, K4E160811D

CMOS DRAM

K4E170812D, K4E160812D

CAPACITANCE

=25

C, V

=5V or 3.3V, f=1MHz)

Parameter

Symbol

Min

Max

Units

Input capacitance [A0 ~ A11]

IN1

Input capacitance [RAS, CAS, W, OE]

IN2

Output capacitance [DQ0 - DQ7]

Test condition (5V device) : V

=5.0V

10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V

Parameter

Symbol

-50

-60

Units

Notes

Min

Max

Min

Max

Random read or write cycle time

104

Read-modify-write cycle time

RWC

116

140

Access time from RAS

RAC

3,4,10

Access time from CAS

CAC

3,4,5

Access time from column address

3,10

CAS to output in Low-Z

CLZ

Output buffer turn-off delay from CAS

CEZ

6,14

OE to output in Low-Z

OLZ

Transition time (rise and fall)

RAS precharge time

RAS pulse width

RAS

10K

RAS hold time

RSH

CAS hold time

CSH

CAS pulse width

CAS

10K

RAS to CAS delay time

RCD

RAS to column address delay time

RAD

CAS to RAS precharge time

CRP

Row address set-up time

ASR

Row address hold time

RAH

Column address set-up time

ASC

Column address hold time

CAH

Column address to RAS lead time

RAL

Read command set-up time

RCS

Read command hold time referenced to CAS

RCH

Read command hold time referenced to RAS

RRH

Write command hold time

WCH

Write command pulse width

Write command to RAS lead time

RWL

Write command to CAS lead time

CWL

AC CHARACTERISTICS

C, See note 1,2)

Test condition (3.3V device) : V

=3.3V

0.3V, Vih/Vil=2.0/0.8V, Voh/Vol=2.0/0.8V

K4E170811D, K4E160811D

CMOS DRAM

K4E170812D, K4E160812D

AC CHARACTERISTICS

(Continued)

Parameter

Symbol

-50

-60

Units

Notes

Min

Max

Min

Max

Data set-up time

Data hold time

Refresh period (2K, Normal)

REF

Refresh period (4K, Normal)

REF

Refresh period (L-ver)

REF

128

Write command set-up time

WCS

CAS to W delay time

CWD

RAS to W delay time

RWD

Column address to W delay time

AWD

CAS precharge to W delay time

CPWD

CAS set-up time (CAS -before-RAS refresh)

CSR

CAS hold time (CAS -before-RAS refresh)

CHR

RAS to CAS precharge time

RPC

Access time from CAS precharge

CPA

Hyper Page cycle time

HPC

Hyper Page read-modify-write cycle time

HPRWC

CAS precharge time (Hyper Page cycle)

RAS pulse width (Hyper Page cycle)

RASP

200K

RAS hold time from CAS precharge

RHCP

OE access time

OEA

OE to data delay

OED

Output buffer turn off delay time from OE

OEZ

OE command hold time

OEH

Write command set-up time (Test mode in)

WTS

Write command hold time (Test mode in)

WTH

W to RAS precharge time(C-B-R refresh)

WRP

W to RAS hold time(C-B-R refresh)

WRH

Output data hold time

DOH

Output buffer turn off delay from RAS

REZ

6,14

Output buffer turn off delay from W

WEZ

W to data delay

WED

OE to CAS hold time

OCH

CAS hold time to OE

CHO

OE precharge time

OEP

W pulse width (Hyper Page Cycle)

WPE

RAS pulse width (C-B-R self refresh)

RASS

100

15,16,17

RAS precharge time (C-B-R self refresh)

RPS

110

15,16,17

CAS hold time (C-B-R self refresh)

CHS

-50

15,16,17

K4E170811D, K4E160811D

CMOS DRAM

K4E170812D, K4E160812D

TEST MODE CYCLE

Parameter

Symbol

-50

-60

Units

Note

Min

Max

Min

Max

Random read or write cycle time

109

Read-modify-write cycle time

RWC

121

145

Access time from RAS

RAC

3,4,10,12

Access time from CAS

CAC

3,4,5,12

Access time from column address

3,10,12

RAS pulse width

RAS

10K

CAS pulse width

CAS

10K

RAS hold time

RSH

CAS hold time

CSH

Column address to RAS lead time

RAL

CAS to W delay time

CWD

RAS to W delay time

RWD

Column address to W delay time

AWD

CAS precharge to W delay time

CPWD

Hyper Page cycle time

HPC

Hyper Page read-modify-write cycle time

HPRWC

RAS pulse width (Hyper Page cycle)

RASP

200K

Access time from CAS precharge

CPA

OE access time

OEA

OE to data delay

OED

OE command hold time

OEH

( Note 11 )

K4E170811D, K4E160811D

CMOS DRAM

K4E170812D, K4E160812D

NOTES

An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles

before proper device operation is achieved.

(min) and V

(max) are reference levels for measuring timing of input signals. Transition times are measured between

(min) and V

(max) and are assumed to be 2ns for all inputs.

Measured with a load equivalent to 2 TTL(5V)/1 TTL(3.3V) loads and 100pF.

Operation within the

RCD

(max) limit insures that

RAC

(max) can be met.

RCD

(max) is specified as a reference point only.

RCD

is greater than the specified

RCD

(max) limit, then access time is controlled exclusively by

CAC

Assumes that

RCD

(max).

This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V

or V

WCS

RWD

CWD

and

AWD

are non restrictive operating parameters. They are included in the data sheet as electrical charac-

teristics only. If

WCS

(min), the cycle is an early write cycle and the data output will remain high impedance for the dura-

tion of the cycle. If

CWD

(min),

RWD

(min) and

AWD

(min), then the cycle is a read-modify-write cycle and the

data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition

of the data out is indeterminate.

Either

RCH

RRH

must be satisfied for a read cycle.

These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in OE controlled write cycle

and read-modify-write cycles.

Operation within the

RAD

(max) limit insures that

RAC

(max) can be met.

RAD

(max) is specified as a reference point only.

RAD

is greater than the specified

RAD

(max) limit, then access time is controlled by

These specifications are applied in the test mode.

In test mode read cycle, the value of

RAC

CAC

is delayed by 2ns to 5ns for the specified values. These parameters

should be specified in test mode cycles by adding the above value to the specified value in this data sheet.

ASC

6ns, Assume t

= 2.0ns

If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes

high before RAS high going, the open circuit condition of the output is achieved by RAS high going.

RASS

100us, then RAS precharge time must use

RPS

instead of

For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K)/2048(2K) cycles of burst refresh must be exe-

cuted within 64ms/32ms before and after self refresh, in order to meet refresh specification.

For distributed CAS-before-RAS with 15.6us interval CAS-before-RAS refresh should be executed with in 15.6us immedi-

ately before and after self refresh in order to meet refresh specification.

10.

11.

12.

13.

14.

15.

16.

17.

K4E170811D, K4E160811D

CMOS DRAM

K4E170812D, K4E160812D

DOH

HYPER PAGE READ CYCLE

RAS

CAS

COLUMN

ADDRESS

ROW

ADDR

RASP

RCD

ASR

CRP

Don

t care

Undefined

DQ0 ~ DQ3(7)

OEP

COLUMN

ADDRESS

CAS

HPC

RHCP

CSH

RAD

RAH

ASC

CAH

ASC

CAH

RCS

RCH

ASC

COLUMN

ADDRESS

COLUMN

ADDR

VALID

DATA-OUT

OEZ

OEA

OEP

CAC

CPA

VALID

DATA-OUT

VALID

DATA-OUT

OEZ

CLZ

RAC

OEA

OLZ

CAC

RRH

CHO

REZ

OEZ

CAC

OCH

CPA

CAC

VALID

DATA-OUT

¡ó

ASC

RAL

OEA

K4E170811D, K4E160811D

CMOS DRAM

K4E170812D, K4E160812D

RAS

CAS

COLUMN

ADDRESS

ROW

ADDR.

RASP

RCD

ASR

CRP

Don

t care

HYPER PAGE WRITE CYCLE ( EARLY WRITE )

Undefined

DQ0 ~ DQ3(7)

RHCP

RAD

RAH

CAH

ASC

CAH

ASC

VALID

DATA-IN

¡ó

COLUMN

ADDRESS

COLUMN

ADDRESS

CAS

RSH

¡ó

CSH

ASC

¡ó

WCS

WCH

WCS

WCH

¡ó

VALID

DATA-IN

VALID

DATA-IN

¡ó

CWL

RWL

NOTE : D

OUT

= OPEN

HPC

WCS

RAL

K4E170811D, K4E160811D

CMOS DRAM

K4E170812D, K4E160812D

Don

t care

HYPER PAGE READ-MODIFY-WRITE CYCLE

Undefined

RAS

CAS

I/OH

I/OL

ROW

ADDR

CSH

RASP

ASR

RCD

RAD

CAH

COL.

ADDR

COL.

ADDR

CAS

CRP

ASC

CAH

RAL

RCS

CWL

CWD

AWD

RWD

CWD

AWD

CWL

RAC

OEA

CLZ

OEZ

CPWD

OED

ASC

CLZ

OEA

CAC

OED

RWL

CRP

OEZ

VALID

DATA-OUT

VALID

DATA-IN

VALID

DATA-OUT

VALID

DATA-IN

DQ0 ~ DQ3(7)

RSH

OLZ

HPRWC

CAC

RAH

K4E170811D, K4E160811D

CMOS DRAM

K4E170812D, K4E160812D

HYPER PAGE READ AND WRITE MIXED CYCLE

RAS

CAS

COLUMN

ADDRESS

ROW

ADDR

RASP

Don

t care

Undefined

I/OH

I/OL

DQ0 ~ DQ3(7)

WEZ

HPC

RAD

RAH

ASC

CAH

ASC

CAH

RCH

RCS

RCH

ASC

COLUMN

ADDRESS

COL.

ADDR

VALID

DATA-OUT

REZ

WCS

VALID

DATA-OUT

VALID

DATA-OUT

VALID

DATA-IN

RAC

COL.

ADDR

CAS

ASR

CAS

ASC

RCH

WCH

WPE

CLZ

CPA

WED

WEZ

CAC

OEA

READ(

CAC

)

READ(

CPA

)

WRITE

READ(

)

RHCP

RAL

CLZ

K4E170811D, K4E160811D

CMOS DRAM

K4E170812D, K4E160812D

PACKAGE DIMENSION

28 SOJ

300mil

.
3

(
7

.
6

)

.
3

(
8

.
3

)

.
3

(
8

.
6

)

0.730 (18.54)

0.720 (18.30)

MAX

0.741 (18.82)

.
1

(
3

.
7

)

0.0375 (0.95)

0.050 (1.27)

0.032 (0.81)

0.026 (0.66)

0.021 (0.53)

0.015 (0.38)

0.027 (0.69)

0.012 (0.30)

0.006 (0.15)

.
2

(
7

.
1

)

.
2

(
6

.
6

)

MIN

#28

Units : Inches (millimeters)

28 TSOP(II) 300mil

MAX

0.047 (1.20)

MIN

0.002 (0.05)

0.020 (0.50)

0.012 (0.30)

0.050 (1.27)

0.037 (0.95)

0.721 (18.31)
0.729 (18.51)

0.741 (18.81)

MAX

0.010 (0.25)

0.004 (0.10)

.
3

(
7

.
6

)

.
3

(
9

.
4

)

.
3

(
9

.
0

)

Units : Inches (millimeters)

0~8

0.030 (0.75)

0.018 (0.45)

TYP

0.010 (0.25)

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: K4E170811D-B