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Электронный компонент: K4E170811D-B

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K4E170811D, K4E160811D
CMOS DRAM
K4E170812D, K4E160812D
This is a family of 2,097,152 x 8 bit Extended Data Out CMOS DRAMs. Extended Data Out Mode offers high speed random access of
memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+5.0V or +3.3V), refresh cycle (2K Ref. or 4K
Ref.), access time (-50 or -60), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of
this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh
operation is available in L-version. This 2Mx8 EDO Mode DRAM family is fabricated using Samsung
s advanced CMOS process to real-
ize high band-width, low power consumption and high reliability. It may be used as graphic memory unit for microcomputer and personal
computer.
Part Identification

- K4E170811D-B(F) (5V, 4K Ref.)
- K4E160811D-B(F) (5V, 2K Ref.)
- K4E170812D-B(F) (3.3V, 4K Ref.)
- K4E160812D-B(F) (3.3V, 2K Ref.)
Extended Data Out Mode operation
(Fast page mode with Extended Data Out)
CAS-before-RAS refresh capability
RAS-only and Hidden refresh capability
Self-refresh capability (L-ver only)
Fast parallel test mode capability
TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
Early Write or output enable controlled write
JEDEC Standard pinout
Available in Plastic SOJ and TSOP(II) packages
Single +5V
10% power supply (5V product)
Single +3.3V
0.3V power supply (3.3V product)
Control
Clocks
RAS
CAS
W
Vcc
Vss
DQ0
to
DQ7
A0-A11
(A0 - A10)
*1
A0 - A8
(A0 - A9)
*1
Memory Array
2,097,152 x8
Cells
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
2M x 8Bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Refresh Cycles
Part
NO.
V
CC
Refresh
cycle
Refresh period
Normal
L-ver
K4E170811D
5V
4K
64ms
128ms
K4E170812D
3.3V
K4E160811D
5V
2K
32ms
K4E160812D
3.3V
Performance Range
Speed
t
RAC
t
CAC
t
RC
t
HPC
Remark
-50
50ns
13ns
84ns
20ns
5V/3.3V
-60
60ns
15ns
104ns
25ns
5V/3.3V
Active Power Dissipation
Speed
3.3V
5V
4K
2K
4K
2K
-50
324
396
495
605
-60
288
360
440
550
Unit : mW
S
e
n
s
e

A
m
p
s

&

I
/
O
Data out
Buffer
Data in
Buffer
OE
Note)
*1
: 2K Refresh
Col. Address Buffer
Row Address Buffer
Refresh Counter
Refresh Control
Refresh Timer
Column Decoder
Row Decoder
VBB Generator
K4E170811D, K4E160811D
CMOS DRAM
K4E170812D, K4E160812D
V
CC
DQ0
DQ1
DQ2
DQ3
W
RAS
*A11(N.C)
A10
A0
A1
A2
A3
V
CC
V
SS
DQ7
DQ6
DQ5
DQ4
CAS
OE
A9
A8
A7
A6
A5
A4
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PIN CONFIGURATION (Top Views)
Pin Name
Pin Function
A0 - A11
Address Inputs (4K Product)
A0 - A10
Address Inputs (2K Product)
DQ0 - 7
Data In/Out
V
SS
Ground
RAS
Row Address Strobe
CAS
Column Address Strobe
W
Read/Write Input
OE
Data Output Enable
V
CC
Power(+5V)
Power(+3.3V)
N.C
No Connection (2K Ref. product)
V
CC
DQ0
DQ1
DQ2
DQ3
W
RAS
*A11(N.C)
A10
A0
A1
A2
A3
V
CC
V
SS
DQ7
DQ6
DQ5
DQ4
CAS
OE
A9
A8
A7
A6
A5
A4
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
*A11 is N.C for K4E160811(2)D(5V/3.3V, 2K Ref. product)
B : 300mil 28 SOJ
F : 300mil 28 TSOP II
K4E17(6)0811(2)D-B
K4E17(6)0811(2)D-F
K4E170811D, K4E160811D
CMOS DRAM
K4E170812D, K4E160812D
ABSOLUTE MAXIMUM RATINGS
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted
to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Parameter
Symbol
Rating
Units
3.3V
5V
Voltage on any pin relative to V
SS
V
IN,
V
OUT
-0.5 to +4.6
-1.0 to +7.0
V
Voltage on V
CC
supply relative to V
SS
V
CC
-0.5 to +4.6
-1.0 to +7.0
V
Storage Temperature
Tstg
-55 to +150
-55 to +150
C
Power Dissipation
P
D
1
1
W
Short Circuit Output Current
I
OS
Address
50
50
mA
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to Vss, T
A
= 0 to 70
C)
*1 : V
CC
+1.3V/15ns(3.3V), V
CC
+2.0V/20ns(5V), Pulse width is measured at V
CC
*2 : -1.3V/15ns(3.3V), -2.0V/20ns(5V), Pulse width is measured at V
SS
Parameter
Symbol
3.3V
5V
Units
Min
Typ
Max
Min
Typ
Max
Supply Voltage
V
CC
3.0
3.3
3.6
4.5
5.0
5.5
V
Ground
V
SS
0
0
0
0
0
0
V
Input High Voltage
V
IH
2.0
-
V
CC
+0.3
*1
2.4
-
V
CC
+1.0
*1
V
Input Low Voltage
V
IL
-0.3
*2
-
0.8
-1.0
*2
-
0.8
V
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Max
Parameter
Symbol
Min
Max
Units
3.3V
Input Leakage Current (Any input 0
V
IN
V
IN
+0.3V,
all other input pins not under test=0 Volt)
I
I(L)
-5
5
uA
Output Leakage Current
(Data out is disabled, 0V
V
OUT
V
CC
)
I
O(L)
-5
5
uA
Output High Voltage Level(I
OH
=-2mA)
V
OH
2.4
-
V
Output Low Voltage Level(I
OL
=2mA)
V
OL
-
0.4
V
5V
Input Leakage Current (Any input 0
V
IN
V
IN
+0.5V,
all other input pins not under test=0 Volt)
I
I(L)
-5
5
uA
Output Leakage Current
(Data out is disabled, 0V
V
OUT
V
CC
)
I
O(L)
-5
5
uA
Output High Voltage Level(I
OH
=-5mA)
V
OH
2.4
-
V
Output Low Voltage Level(I
OL
=4.2mA)
V
OL
-
0.4
V
K4E170811D, K4E160811D
CMOS DRAM
K4E170812D, K4E160812D
*Note :
I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
, I
CC3
and I
CC6,
address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one Hyper page mode cycle time, t
HPC
.
DC AND OPERATING CHARACTERISTICS
(Continued)
I
CC1
* : Operating Current (RAS and CAS cycling @t
RC
=min.)
I
CC2
: Standby Current (RAS=CAS=W=V
IH
)
I
CC3
* : RAS-only Refresh Current (CAS=V
IH
, RAS cycling @t
RC
=min.)
I
CC4
* : Hyper Page Mode Current (RAS=V
IL
, CAS, Address cycling @t
HPC
=min.)
I
CC5
: Standby Current (RAS=CAS=W=V
CC
-0.2V)
I
CC6
* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @t
RC
=min.)
I
CC7
: Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(V
IH
)=V
CC
-0.2V, Input low voltage(V
IL
)=0.2V, CAS=0.2V,
DQ=Don
t care, T
RC
=31.25us(4K/L-ver), 62.5us(2K/L-ver),
T
RAS
=T
RAS
min~300ns
I
CCS
: Self Refresh Current
RAS=CAS=V
IL
, W=OE=A0 ~ A11=V
CC
-0.2V or 0.2V,
DQ0 ~ DQ7=V
CC
-0.2V, 0.2V or Open
Symbol
Power
Speed
Max
Units
K4E170812D
K4E160812D
K4E170811D
K4E160811D
I
CC1
Don
t care
-50
-60
90
80
110
100
90
80
110
100
mA
mA
I
CC2
Normal
L
Don
t care
1
1
1
1
2
1
2
1
mA
mA
I
CC3
Don
t care
-50
-60
90
80
110
100
90
80
110
100
mA
mA
I
CC4
Don
t care
-50
-60
80
70
90
80
80
70
90
80
mA
mA
I
CC5
Normal
L
Don
t care
0.5
200
0.5
200
1
250
1
250
mA
uA
I
CC6
Don
t care
-50
-60
90
80
110
100
90
80
110
100
mA
mA
I
CC7
L
Don
t care
250
250
300
300
uA
I
CCS
L
Don
t care
200
200
250
250
uA
K4E170811D, K4E160811D
CMOS DRAM
K4E170812D, K4E160812D
CAPACITANCE
(T
A
=25
C, V
CC
=5V or 3.3V, f=1MHz)
Parameter
Symbol
Min
Max
Units
Input capacitance [A0 ~ A11]
C
IN1
-
5
pF
Input capacitance [RAS, CAS, W, OE]
C
IN2
-
7
pF
Output capacitance [DQ0 - DQ7]
C
DQ
-
7
pF
Test condition (5V device) : V
CC
=5.0V
10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V
Parameter
Symbol
-50
-60
Units
Notes
Min
Max
Min
Max
Random read or write cycle time
t
RC
84
104
ns
Read-modify-write cycle time
t
RWC
116
140
ns
Access time from RAS
t
RAC
50
60
ns
3,4,10
Access time from CAS
t
CAC
13
15
ns
3,4,5
Access time from column address
t
AA
25
30
ns
3,10
CAS to output in Low-Z
t
CLZ
3
3
ns
3
Output buffer turn-off delay from CAS
t
CEZ
3
13
3
15
ns
6,14
OE to output in Low-Z
t
OLZ
3
3
ns
3
Transition time (rise and fall)
t
T
2
50
2
50
ns
2
RAS precharge time
t
RP
30
40
ns
RAS pulse width
t
RAS
50
10K
60
10K
ns
RAS hold time
t
RSH
13
15
ns
CAS hold time
t
CSH
38
45
ns
CAS pulse width
t
CAS
8
10K
10
10K
ns
RAS to CAS delay time
t
RCD
20
37
20
45
ns
4
RAS to column address delay time
t
RAD
15
25
15
30
ns
10
CAS to RAS precharge time
t
CRP
5
5
ns
Row address set-up time
t
ASR
0
0
ns
Row address hold time
t
RAH
10
10
ns
Column address set-up time
t
ASC
0
0
ns
Column address hold time
t
CAH
8
10
ns
Column address to RAS lead time
t
RAL
25
30
ns
Read command set-up time
t
RCS
0
0
ns
Read command hold time referenced to CAS
t
RCH
0
0
ns
8
Read command hold time referenced to RAS
t
RRH
0
0
ns
8
Write command hold time
t
WCH
10
10
ns
Write command pulse width
t
WP
10
10
ns
Write command to RAS lead time
t
RWL
13
15
ns
Write command to CAS lead time
t
CWL
8
10
ns
AC CHARACTERISTICS
(0
C
T
A
70
C, See note 1,2)
Test condition (3.3V device) : V
CC
=3.3V
0.3V, Vih/Vil=2.0/0.8V, Voh/Vol=2.0/0.8V
K4E170811D, K4E160811D
CMOS DRAM
K4E170812D, K4E160812D
AC CHARACTERISTICS
(Continued)
Parameter
Symbol
-50
-60
Units
Notes
Min
Max
Min
Max
Data set-up time
t
DS
0
0
ns
9
Data hold time
t
DH
8
10
ns
9
Refresh period (2K, Normal)
t
REF
32
32
ms
Refresh period (4K, Normal)
t
REF
64
64
ms
Refresh period (L-ver)
t
REF
128
128
ms
Write command set-up time
t
WCS
0
0
ns
7
CAS to W delay time
t
CWD
30
34
ns
7
RAS to W delay time
t
RWD
67
79
ns
7
Column address to W delay time
t
AWD
42
49
ns
7
CAS precharge to W delay time
t
CPWD
47
54
ns
CAS set-up time (CAS -before-RAS refresh)
t
CSR
5
5
ns
CAS hold time (CAS -before-RAS refresh)
t
CHR
10
10
ns
RAS to CAS precharge time
t
RPC
5
5
ns
Access time from CAS precharge
t
CPA
28
35
ns
3
Hyper Page cycle time
t
HPC
20
25
ns
13
Hyper Page read-modify-write cycle time
t
HPRWC
47
56
ns
13
CAS precharge time (Hyper Page cycle)
t
CP
8
10
ns
RAS pulse width (Hyper Page cycle)
t
RASP
50
200K
60
200K
ns
RAS hold time from CAS precharge
t
RHCP
30
35
ns
OE access time
t
OEA
13
15
ns
OE to data delay
t
OED
13
15
ns
Output buffer turn off delay time from OE
t
OEZ
3
13
3
15
ns
6
OE command hold time
t
OEH
13
15
ns
Write command set-up time (Test mode in)
t
WTS
10
10
ns
11
Write command hold time (Test mode in)
t
WTH
10
10
ns
11
W to RAS precharge time(C-B-R refresh)
t
WRP
10
10
ns
W to RAS hold time(C-B-R refresh)
t
WRH
10
10
ns
Output data hold time
t
DOH
5
5
ns
Output buffer turn off delay from RAS
t
REZ
3
13
3
15
ns
6,14
Output buffer turn off delay from W
t
WEZ
3
13
3
15
ns
6
W to data delay
t
WED
15
15
ns
OE to CAS hold time
t
OCH
5
5
ns
CAS hold time to OE
t
CHO
5
5
ns
OE precharge time
t
OEP
5
5
ns
W pulse width (Hyper Page Cycle)
t
WPE
5
5
ns
RAS pulse width (C-B-R self refresh)
t
RASS
100
100
us
15,16,17
RAS precharge time (C-B-R self refresh)
t
RPS
90
110
ns
15,16,17
CAS hold time (C-B-R self refresh)
t
CHS
-50
-50
ns
15,16,17
K4E170811D, K4E160811D
CMOS DRAM
K4E170812D, K4E160812D
TEST MODE CYCLE
Parameter
Symbol
-50
-60
Units
Note
Min
Max
Min
Max
Random read or write cycle time
t
RC
89
109
ns
Read-modify-write cycle time
t
RWC
121
145
ns
Access time from RAS
t
RAC
55
65
ns
3,4,10,12
Access time from CAS
t
CAC
18
20
ns
3,4,5,12
Access time from column address
t
AA
30
35
ns
3,10,12
RAS pulse width
t
RAS
55
10K
65
10K
ns
CAS pulse width
t
CAS
13
10K
15
10K
ns
RAS hold time
t
RSH
18
20
ns
CAS hold time
t
CSH
43
50
ns
Column address to RAS lead time
t
RAL
30
35
ns
CAS to W delay time
t
CWD
35
39
ns
7
RAS to W delay time
t
RWD
72
84
ns
7
Column address to W delay time
t
AWD
47
54
ns
7
CAS precharge to W delay time
t
CPWD
52
59
ns
Hyper Page cycle time
t
HPC
25
30
ns
13
Hyper Page read-modify-write cycle time
t
HPRWC
53
61
ns
13
RAS pulse width (Hyper Page cycle)
t
RASP
55
200K
65
200K
ns
Access time from CAS precharge
t
CPA
33
40
ns
3
OE access time
t
OEA
18
20
ns
OE to data delay
t
OED
18
20
ns
OE command hold time
t
OEH
18
20
ns
( Note 11 )
K4E170811D, K4E160811D
CMOS DRAM
K4E170812D, K4E160812D
NOTES
An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles
before proper device operation is achieved.
V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals. Transition times are measured between
V
IH
(min) and V
IL
(max) and are assumed to be 2ns for all inputs.
Measured with a load equivalent to 2 TTL(5V)/1 TTL(3.3V) loads and 100pF.
Operation within the
t
RCD
(max) limit insures that
t
RAC
(max) can be met.
t
RCD
(max) is specified as a reference point only.
If
t
RCD
is greater than the specified
t
RCD
(max) limit, then access time is controlled exclusively by
t
CAC
.
Assumes that
t
RCD
t
RCD
(max).
This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V
oh
or V
ol
.
t
WCS
,
t
RWD
,
t
CWD
and
t
AWD
are non restrictive operating parameters. They are included in the data sheet as electrical charac-
teristics only. If
t
WCS
t
WCS
(min), the cycle is an early write cycle and the data output will remain high impedance for the dura-
tion of the cycle. If
t
CWD
t
CWD
(min),
t
RWD
t
RWD
(min) and
t
AWD
t
AWD
(min), then the cycle is a read-modify-write cycle and the
data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition
of the data out is indeterminate.
Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in OE controlled write cycle
and read-modify-write cycles.
Operation within the
t
RAD
(max) limit insures that
t
RAC
(max) can be met.
t
RAD
(max) is specified as a reference point only.
If
t
RAD
is greater than the specified
t
RAD
(max) limit, then access time is controlled by
t
AA
.
These specifications are applied in the test mode.
In test mode read cycle, the value of
t
RAC
,
t
AA
,
t
CAC
is delayed by 2ns to 5ns for the specified values. These parameters
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
t
ASC
6ns, Assume t
T
= 2.0ns
If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes
high before RAS high going, the open circuit condition of the output is achieved by RAS high going.
If
t
RASS
100us, then RAS precharge time must use
t
RPS
instead of
t
RP
.
For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K)/2048(2K) cycles of burst refresh must be exe-
cuted within 64ms/32ms before and after self refresh, in order to meet refresh specification.
For distributed CAS-before-RAS with 15.6us interval CAS-before-RAS refresh should be executed with in 15.6us immedi-
ately before and after self refresh in order to meet refresh specification.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
1.
2.
3.
4.
17.
K4E170811D, K4E160811D
CMOS DRAM
K4E170812D, K4E160812D
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
V
OH
-
V
OL
-
COLUMN
ADDRESS
ROW
ADDRESS
t
RAS
t
RC
t
CRP
t
RP
t
CSH
t
RSH
t
RCD
t
CAS
t
RAL
t
ASR
t
RAH
t
ASC
t
CAH
t
CRP
t
AA
t
OEA
t
CLZ
t
RAC
OPEN
t
RCH
Don
t care
Undefined
t
RAD
t
RRH
DATA-OUT
t
REZ
t
RCS
READ CYCLE
t
OEZ
t
CEZ
t
WEZ
DQ0 ~ DQ3(7)
t
OLZ
t
CAC
K4E170811D, K4E160811D
CMOS DRAM
K4E170812D, K4E160812D
t
WCS
NOTE : D
OUT
= OPEN
WRITE CYCLE ( EARLY WRITE )
RAS
V
IH
-
V
IL
-
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDRESS
t
RAS
t
RC
t
CRP
t
RP
t
CSH
t
RSH
t
RCD
t
CAS
t
RAL
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
CRP
Don
t care
Undefined
t
WCH
t
WP
CAS
t
RWL
t
CWL
t
DS
t
DH
DATA-IN
DQ0 ~ DQ3(7)
K4E170811D, K4E160811D
CMOS DRAM
K4E170812D, K4E160812D
NOTE : D
OUT
= OPEN
WRITE CYCLE ( OE CONTROLLED WRITE )
RAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
V
IH
-
V
IL
-
DQ0 ~ DQ3(7)
COLUMN
ADDRESS
ROW
ADDRESS
t
RAS
t
RC
t
CRP
t
RP
t
CSH
t
RSH
t
RCD
t
CAS
t
RAL
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
CRP
t
WP
Don
t care
Undefined
CAS
V
IH
-
V
IL
-
t
RWL
t
CWL
t
DH
t
OEH
t
OED
DATA-IN
t
DS
K4E170811D, K4E160811D
CMOS DRAM
K4E170812D, K4E160812D
READ - MODIFY - WRITE CYCLE
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
V
I/OH
-
V
I/OL
-
DQ0 ~ DQ3(7)
ROW
ADDR
t
RAS
t
RWC
t
RP
t
RSH
t
RCD
t
CAS
t
CSH
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
CRP
VALID
t
WP
Don
t care
t
RWL
t
CWL
t
OEZ
t
OEA
t
OED
t
AWD
t
CWD
t
RWD
DATA-OUT
Undefined
VALID
DATA-IN
t
RAC
t
AA
t
CAC
t
CLZ
t
DS
t
DH
COLUMN
ADDRESS
t
OLZ
K4E170811D, K4E160811D
CMOS DRAM
K4E170812D, K4E160812D
t
DOH
HYPER PAGE READ CYCLE
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDR
t
RASP
t
RP
t
RCD
t
ASR
t
CRP
Don
t care
Undefined
V
OH
-
V
OL
-
DQ0 ~ DQ3(7)
t
OEP
COLUMN
ADDRESS
t
CAS
t
CAS
t
CAS
t
CAS
t
CP
t
CP
t
CP
t
HPC
t
HPC
t
HPC
t
RHCP
t
CSH
t
RAD
t
RAH
t
ASC
t
CAH
t
CAH
t
CAH
t
ASC
t
CAH
t
RCS
t
AA
t
RCH
t
ASC
COLUMN
ADDRESS
COLUMN
ADDR
VALID
DATA-OUT
t
OEZ
t
OEA
t
OEP
t
AA
t
CAC
t
AA
t
CPA
t
CPA
VALID
DATA-OUT
VALID
DATA-OUT
t
OEZ
t
CLZ
t
RAC
t
OEA
t
OLZ
t
CAC
t
RRH
t
CHO
t
REZ
t
OEZ
t
CAC
t
OCH
t
CPA
t
CAC
VALID
DATA-OUT
t
ASC
t
AA
t
RAL
t
OEA
K4E170811D, K4E160811D
CMOS DRAM
K4E170812D, K4E160812D
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDR.
t
RASP
t
RP
t
RCD
t
ASR
t
CRP
Don
t care
HYPER PAGE WRITE CYCLE ( EARLY WRITE )
Undefined
V
IH
-
V
IL
-
DQ0 ~ DQ3(7)
t
RHCP
t
RAD
t
RAH
t
CAH
t
CAH
t
ASC
t
CAH
t
ASC
VALID
DATA-IN
t
DS
COLUMN
ADDRESS
COLUMN
ADDRESS
t
CAS
t
CP
t
CAS
t
CP
t
CAS
t
RSH
t
CSH
t
ASC
t
WP
t
WCS
t
WCH
t
WP
t
WCS
t
WCH
t
WP
t
WCH
VALID
DATA-IN
VALID
DATA-IN
t
DH
t
DS
t
DH
t
DS
t
DH
t
CWL
t
CWL
t
CWL
t
RWL
NOTE : D
OUT
= OPEN
t
HPC
t
HPC
t
WCS
t
RAL
K4E170811D, K4E160811D
CMOS DRAM
K4E170812D, K4E160812D
Don
t care
HYPER PAGE READ-MODIFY-WRITE CYCLE
Undefined
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
V
I/OH
-
V
I/OL
-
ROW
ADDR
t
CSH
t
RASP
t
RP
t
ASR
t
RCD
t
CP
t
RAD
t
CAH
t
WP
t
DH
COL.
ADDR
COL.
ADDR
t
CAS
t
CAS
t
CRP
t
ASC
t
CAH
t
RAL
t
RCS
t
CWL
t
CWD
t
AWD
t
RWD
t
WP
t
CWD
t
AWD
t
CWL
t
RAC
t
OEA
t
CLZ
t
OEZ
t
CPWD
t
OED
t
ASC
t
CLZ
t
OEA
t
CAC
t
AA
t
DH
t
OED
t
RWL
t
CRP
t
DS
t
OEZ
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
t
DS
DQ0 ~ DQ3(7)
t
RSH
t
OLZ
t
OLZ
t
HPRWC
t
CAC
t
AA
t
RAH
K4E170811D, K4E160811D
CMOS DRAM
K4E170812D, K4E160812D
HYPER PAGE READ AND WRITE MIXED CYCLE
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDR
t
RASP
t
RP
Don
t care
Undefined
V
I/OH
-
V
I/OL
-
DQ0 ~ DQ3(7)
t
WEZ
t
CP
t
CP
t
HPC
t
HPC
t
HPC
t
RAD
t
RAH
t
ASC
t
CAH
t
CAH
t
CAH
t
ASC
t
CAH
t
RCH
t
RCS
t
RCS
t
RCH
t
ASC
COLUMN
ADDRESS
COL.
ADDR
VALID
DATA-OUT
t
REZ
t
AA
t
WCS
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-IN
t
RAC
COL.
ADDR
t
CAS
t
ASR
t
CAS
t
CAS
t
CAS
t
ASC
t
CP
t
RCH
t
WCH
t
WPE
t
CLZ
t
CPA
t
WED
t
AA
t
WEZ
t
DS
t
DH
t
CAC
t
OEA
READ(
t
CAC
)
READ(
t
CPA
)
WRITE
READ(
t
AA
)
t
RHCP
t
RAL
t
CLZ
K4E170811D, K4E160811D
CMOS DRAM
K4E170812D, K4E160812D
Don
t care
RAS - ONLY REFRESH CYCLE*
NOTE : W, OE, D
IN
= Don
t care
Undefined
D
OUT
= OPEN
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
ROW
ADDR
t
RC
t
RP
t
ASR
t
CRP
t
RAS
t
RAH
t
RPC
t
CRP
OPEN
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE , A = Don
t care
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
t
RC
t
RP
t
RAS
t
RPC
t
CP
t
RPC
t
CSR
t
CHR
t
CEZ
V
OH
-
V
OL
-
DQ0 ~ DQ3(7)
t
WRP
t
WRH
W
V
IH
-
V
IL
-
t
RP
K4E170811D, K4E160811D
CMOS DRAM
K4E170812D, K4E160812D
HIDDEN REFRESH CYCLE ( READ )
t
OEZ
DATA-OUT
t
RP
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
ROW
ADDRESS
t
RAS
t
RC
t
CHR
t
RCD
t
RSH
t
RAD
t
ASR
t
RAH
t
ASC
t
CRP
Don
t care
Undefined
V
OH
-
V
OL
-
DQ0 ~ DQ3(7)
t
WRH
COLUMN
ADDRESS
t
OEA
t
RAS
t
RC
t
CAH
t
RCS
t
AA
t
RAC
t
CLZ
t
CAC
t
CEZ
OPEN
t
RP
t
WEZ
t
REZ
t
OLZ
t
RAL
K4E170811D, K4E160811D
CMOS DRAM
K4E170812D, K4E160812D
t
CRP
t
WCS
t
RP
RAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
ROW
ADDRESS
t
RAS
t
RC
t
RAD
t
ASR
t
RAH
t
ASC
Don
t care
HIDDEN REFRESH CYCLE ( WRITE )
Undefined
CAS
V
IH
-
V
IL
-
V
IH
-
V
IL
-
DQ0 ~ DQ3(7)
t
RSH
t
RCD
t
WRH
COLUMN
ADDRESS
t
RAS
t
RC
t
CHR
t
CAH
t
WRP
t
DS
NOTE : D
OUT
= OPEN
t
WP
t
WCH
DATA-IN
t
DH
t
RP
t
RAL
K4E170811D, K4E160811D
CMOS DRAM
K4E170812D, K4E160812D
OPEN
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE, A = Don
t care
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
t
RPS
t
RASS
t
RPC
t
CP
t
RPC
t
CSR
t
CEZ
V
OH
-
V
OL
-
DQ0 ~ DQ3(7)
t
RP
Don
t care
Undefined
t
CHS
t
WRP
t
WRH
W
V
IH
-
V
IL
-
OPEN
TEST MODE IN CYCLE
NOTE : OE , A = Don
t care
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
t
RP
t
RC
t
RPC
t
CP
t
RPC
t
CSR
t
OFF
V
OH
-
V
OL
-
DQ0 ~ DQ3(7)
t
WTS
t
WTH
W
V
IH
-
V
IL
-
t
CHR
t
RP
t
RAS
K4E170811D, K4E160811D
CMOS DRAM
K4E170812D, K4E160812D
PACKAGE DIMENSION
28 SOJ
300mil
0
.
3
0
0

(
7
.
6
2
)
0
.
3
3
0

(
8
.
3
9
)
0
.
3
4
0

(
8
.
6
3
)
0.730 (18.54)
0.720 (18.30)
MAX
0.741 (18.82)
M
A
X
0
.
1
4
8

(
3
.
7
6
)
0.0375 (0.95)
0.050 (1.27)
0.032 (0.81)
0.026 (0.66)
0.021 (0.53)
0.015 (0.38)
0.027 (0.69)
0.012 (0.30)
0.006 (0.15)
0
.
2
8
0

(
7
.
1
1
)
0
.
2
6
0

(
6
.
6
1
)
MIN
#28
#1
Units : Inches (millimeters)
28 TSOP(II) 300mil
MAX
0.047 (1.20)
MIN
0.002 (0.05)
0.020 (0.50)
0.012 (0.30)
0.050 (1.27)
0.037 (0.95)
0.721 (18.31)
0.729 (18.51)
0.741 (18.81)
MAX
0.010 (0.25)
0.004 (0.10)
0
.
3
0
0

(
7
.
6
2
)
0
.
3
7
1

(
9
.
4
2
)
0
.
3
5
5

(
9
.
0
2
)
Units : Inches (millimeters)
0~8
0.030 (0.75)
0.018 (0.45)
TYP
0.010 (0.25)
O