K4E171611C, K4E151611C

CMOS DRAM

K4E171612C, K4E151612C

This is a family of 1,048,576 x 16 bit Extended Data Out CMOS DRAMs. Extended Data Out Mode offers high speed random access of

memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+5.0V or +3.3V), refresh cycle (1K Ref. or 4K

Ref.), access time (-45, -50 or -60), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features

of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-

refresh operation is available in L-version. This 1Mx16 EDO Mode DRAM family is fabricated using Samsung

s advanced CMOS pro-

cess to realize high band-width, low power consumption and high reliability. It may be used as graphic memory unit for microcomputer,

personal computer and portable machines.

· Part Identification

- K4E171611C-J(T)(5V, 4K Ref.)
- K4E151611C-J(T) (5V, 1K Ref.)
- K4E171612C-J(T)(3.3V, 4K Ref.)
- K4E151612C-J(T)(3.3V, 1K Ref.)

· Extended Data Out Mode operation

(Fast Page Mode with Extended Data Out)

· 2 CAS Byte/Word Read/Write operation

CAS-before-RAS refresh capability

RAS-only and Hidden refresh capability

Self-refresh capability (L-ver only)

· TTL(5V)/LVTTL(3.3V) compatible inputs and outputs

Early Write or output enable controlled write

· JEDEC Standard pinout

Available in plastic SOJ 400mil and TSOP(II) packages

Single +5V

10% power supply (5V product)

Single +3.3V

0.3V power supply (3.3V product)

Control
Clocks

VBB Generator

Refresh Timer

Refresh Control

Refresh Counter

Row Address Buffer

Col. Address Buffer

Row Decoder

Column Decoder

Lower

Data out

Buffer

RAS

UCAS

LCAS

Vcc
Vss

DQ0

DQ7

A0-A11

(A0 - A9)

A0 - A7

(A0 - A9)

Memory Array
1,048,576 x16

Cells

SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.

1M x 16Bit CMOS Dynamic RAM with Extended Data Out

DESCRIPTION

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Refresh Cycles

Part
NO.

Refresh

cycle

Refresh period

Normal

L-ver

K4E171611C

64ms

128ms

K4E171612C

3.3V

K4E151611C

16ms

K4E151612C

3.3V

Performance Range

Speed

RAC

CAC

HPC

Remark

-45

45ns

13ns

69ns

16ns

5V/3.3V

-50

50ns

15ns

84ns

20ns

5V/3.3V

-60

60ns

17ns

104ns

25ns

5V/3.3V

· Active Power Dissipation

Speed

3.3V

-45

360

540

550

825

-50

324

504

495

770

-60

288

468

440

715

Unit : mW

I
/
O

Upper

Data in

Buffer

Upper

Data out

Buffer

Lower

Data in

Buffer

DQ8

DQ15

Note)

: 1K Refresh

K4E171611C, K4E151611C

CMOS DRAM

K4E171612C, K4E151612C

DQ0
DQ1
DQ2
DQ3

DQ4
DQ5
DQ6
DQ7

N.C

N.C
N.C

RAS

*A11(N.C)

*A10(N.C)

A0
A1
A2
A3

DQ15
DQ14
DQ13
DQ12
V

DQ11
DQ10
DQ9
DQ8
N.C

N.C
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
V

1
2
3
4
5
6
7
8
9
10
11

12
13
14
15
16
17
18
19
20
21
22

44
43
42
41
40
39
38
37
36
35
34

33
32
31
30
29
28
27
26
25
24
23

PIN CONFIGURATION (Top Views)

Pin Name

Pin Function

A0 - A11

Address Inputs (4K Product)

A0 - A9

Address Inputs (1K Product)

DQ0 - 15

Data In/Out

Ground

RAS

Row Address Strobe

UCAS

Upper Column Address Strobe

LCAS

Lower Column Address Strobe

Read/Write Input

Data Output Enable

Power(+5V)

Power(+3.3V)

N.C

No Connection

DQ0
DQ1
DQ2
DQ3

DQ4
DQ5
DQ6
DQ7

N.C
N.C

RAS

*A11(N.C)

*A10(N.C)

A0
A1
A2
A3

DQ15
DQ14
DQ13
DQ12
V

DQ11
DQ10
DQ9
DQ8
N.C
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
V

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

*A10 and A11 are N.C for K151611(2)C(5V/3.3V, 1K Ref. product)

J : 400mil 42 SOJ
T : 400mil 50(44) TSOP II

· K4E17(5)1611(2)C-J

· K4E17(5)1611(2)C-T

K4E171611C, K4E151611C

CMOS DRAM

K4E171612C, K4E151612C

ABSOLUTE MAXIMUM RATINGS

* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted

to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Parameter

Symbol

Rating

Units

3.3V

Voltage on any pin relative to V

IN,

OUT

-0.5 to +4.6

-1.0 to +7.0

Voltage on V

supply relative to V

-0.5 to +4.6

-1.0 to +7.0

Storage Temperature

Tstg

-55 to +150

Power Dissipation

Short Circuit Output Current

Address

RECOMMENDED OPERATING CONDITIONS

(Voltage referenced to Vss, T

= 0 to 70

*1 : V

+1.3V/15ns(3.3V), V

+2.0V/20ns(5V), Pulse width is measured at V

*2 : -1.3V/15ns(3.3V), -2.0V/20ns(5V), Pulse width is measured at V

Parameter

Symbol

3.3V

Units

Min

Typ

Max

Min

Typ

Max

Supply Voltage

3.0

3.3

3.6

4.5

5.0

5.5

Ground

Input High Voltage

2.0

+0.3

2.4

+1.0

Input Low Voltage

-0.3

0.8

-1.0

0.8

DC AND OPERATING CHARACTERISTICS

(Recommended operating conditions unless otherwise noted.)

Max

Parameter

Symbol

Min

Max

Units

3.3V

Input Leakage Current (Any input 0

+0.3V,

all other input pins not under test=0 Volt)

I(L)

-5

Output Leakage Current
(Data out is disabled, 0V

OUT

)

O(L)

-5

Output High Voltage Level(I

=-2mA)

2.4

Output Low Voltage Level(I

=2mA)

0.4

Input Leakage Current (Any input 0

+0.5V,

all other input pins not under test=0 Volt)

I(L)

-5

Output Leakage Current
(Data out is disabled, 0V

OUT

)

O(L)

-5

Output High Voltage Level(I

=-5mA)

2.4

Output Low Voltage Level(I

=4.2mA)

0.4

K4E171611C, K4E151611C

CMOS DRAM

K4E171612C, K4E151612C

*Note :

CC1

, I

CC3

, I

CC4

and I

CC6

are dependent on output loading and cycle rates. Specified values are obtained with the output open.

is specified as an average current. In I

CC1

, I

CC3

and I

CC6,

address can be changed maximum once while RAS=V

. In I

CC4

address can be changed maximum once within one Hyper page mode cycle time, t

HPC

DC AND OPERATING CHARACTERISTICS

(Continued)

CC1

* : Operating Current (RAS and UCAS, LCAS, Address cycling @t

=min.)

CC2

: Standby Current (RAS=UCAS=LCAS=W=V

)

CC3

* : RAS-only Refresh Current (UCAS=LCAS=V

, RAS, Address cycling @t

=min.)

CC4

* : Hyper Page Mode Current (RAS=V

, UCAS or LCAS, Address cycling @t

HPC

=min.)

CC5

: Standby Current (RAS=UCAS=LCAS=W=V

-0.2V)

CC6

* : CAS-Before-RAS Refresh Current (RAS, UCAS or LCAS cycling @t

=min.)

CC7

: Battery back-up current, Average power supply current, Battery back-up mode

Input high voltage(V

)=V

-0.2V, Input low voltage(V

)=0.2V, UCAS, LCAS=0.2V,

DQ=Don

t care, T

=31.25us(4K/L-ver), 125us(1K/L-ver)

RAS

min~300ns

CCS

: Self Refresh Current

RAS=UCAS=LCAS=V

, W=OE=A0 ~ A11=V

-0.2V or 0.2V,

DQ0 ~ DQ15=V

-0.2V, 0.2V or Open

Symbol

Power

Speed

Max

Units

K4E171612C

K4E151612C

K4E171611C

K4E151611C

CC1

Don

t care

-45
-50
-60

100

90
80

150
140
130

100

90
80

150
140
130

mA
mA
mA

CC2

Normal

Don

t care

1
1

2
1

mA
mA

CC3

Don

t care

-45
-50
-60

100

90
80

150
140
130

100

90
80

150
140
130

mA
mA
mA

CC4

Don

t care

-45
-50
-60

110

100

110

100

110
100

mA
mA
mA

CC5

Normal

Don

t care

0.5

200

0.5

200

CC6

Don

t care

-45
-50
-60

100

90
80

150
140
130

110

90
80

150
140
130

mA
mA
mA

CC7

Don

t care

300

200

350

250

CCS

Don

t care

150

200

K4E171611C, K4E151611C

CMOS DRAM

K4E171612C, K4E151612C

CAPACITANCE

=25

C, V

=5V or 3.3V, f=1MHz)

Parameter

Symbol

Min

Max

Units

Input capacitance [A0 ~ A11]

IN1

Input capacitance [RAS, UCAS, LCAS, W, OE]

IN2

Output capacitance [DQ0 - DQ15]

Test condition (5V device) : V

=5.0V

10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V

Parameter

Symbol

-45

-50

-60

Units

Notes

Min

Max

Min

Max

Min

Max

Random read or write cycle time

104

Read-modify-write cycle time

RWC

105

115

140

Access time from RAS

RAC

3,4,10

Access time from CAS

CAC

3,4,5

Access time from column address

23/*20

3,10

CAS to output in Low-Z

CLZ

Output buffer turn-off delay from CAS

CEZ

6,19

OE to output in Low-Z

OLZ

Transition time (rise and fall)

RAS precharge time

RAS pulse width

RAS

10K

RAS hold time

RSH

CAS hold time

CSH

CAS pulse width

CAS

7 / *6.5

10K

RAS to CAS delay time

RCD

RAS to column address delay time

RAD

CAS to RAS precharge time

CRP

Row address set-up time

ASR

Row address hold time

RAH

Column address set-up time

ASC

Column address hold time

CAH

Column address to RAS lead time

RAL

Read command set-up time

RCS

Read command hold time referenced to CAS

RCH

Read command hold time referenced to RAS

RRH

Write command hold time

WCH

Write command pulse width

Write command to RAS lead time

RWL

Write command to CAS lead time

CWL

AC CHARACTERISTICS

C, See note 1,2)

Test condition (3.3V device) : V

=3.3V

0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V

* KM416C1204CT-45 (5V, 1K Refresh) only

K4E171611C, K4E151611C

CMOS DRAM

K4E171612C, K4E151612C

AC CHARACTERISTICS

(Continued)

* KM416C1204CT-45 (5V, 1K Refresh) only

Parameter

Symbol

-45

-50

-60

Units

Notes

Min

Max

Min

Max

Min

Max

Data set-up time

9,17

Data hold time

9,17

Refresh period (1K, Normal)

REF

Refresh period (4K, Normal)

REF

Refresh period (L-ver)

REF

128

Write command set-up time

WCS

CAS to W delay time

CWD

7,13

RAS to W delay time

RWD

Column address W delay time

AWD

CAS precharge to W delay time

CPWD

CAS set-up time (CAS -before-RAS refresh)

CSR

CAS hold time (CAS -before-RAS refresh)

CHR

RAS to CAS precharge time

RPC

Access time from CAS precharge

CPA

Hyper Page mode cycle time

HPC

Hyper Page read-modify-write cycle time

HPRWC

CAS precharge time (Hyper Page cycle)

7 / *6.5

RAS pulse width (Hyper Page cycle)

RASP

200K

RAS hold time from CAS precharge

RHCP

OE access time

OEA

OE to data delay

OED

Output buffer turn off delay time from OE

OEZ

OE command hold time

OEH

Output data hold time

DOH

Output buffer turn off delay from RAS

REZ

6,19

Output buffer turn off delay from W

WEZ

W to data delay

WED

OE to CAS hold time

OCH

CAS hold time to OE

CHO

OE precharge time

OEP

W pulse width (Hyper Page Cycle)

WPE

RAS pulse width (C-B-R self refresh)

RASS

100

20,21,22

RAS precharge time (C-B-R self refresh)

RPS

110

20,21,22

CAS hold time (C-B-R self refresh)

CHS

-50

20,21,22

K4E171611C, K4E151611C

CMOS DRAM

K4E171612C, K4E151612C

NOTES

An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles

before proper device operation is achieved.

Input voltage levels are Vih/Vil. V

(min) and V

(max) are reference levels for measuring timing of input signals.

Transition times are measured between V

(min) and V

(max) and are assumed to be 2ns for all inputs.

Measured with a load equivalent to 2 TTL(5V)/1TTL(3.3V) loads and 100pF.

Operation within the

RCD

(max) limit insures that

RAC

(max) can be met.

RCD

(max) is specified as a reference point only.

RCD

is greater than the specified

RCD

(max) limit, then access time is controlled exclusively by

CAC

Assumes that t

RCD

(max).

This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V

or V

WCS

RWD

CWD

AWD

and

CPWD

are non restrictive operating parameters. They are included in the data sheet as electrical

characteristics only. If

WCS

(min), the cycle is an early write cycle and the data output will remain high impedance for the

duration of the cycle. If

CWD

(min),

RWD

(min),

AWD

(min) and

CPWD

(min), then the cycle is a read-

modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions

is satisfied, the condition of the data out is indeterminate.

Either

RCH

RRH

must be satisfied for a read cycle.

These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in OE controlled write cycle

and read-modify-write cycles.

Operation within the

RAD

(max) limit insures that

RAC

(max) can be met.

RAD

(max) is specified as a reference point only.

RAD

is greater than the specified

RAD

(max) limit, then access time is controlled by

K4E17(5)1611(2)C Truth Table

RAS

LCAS

UCAS

DQ0 - DQ7

DQ8-DQ15

STATE

Hi-Z

Standby

Hi-Z

Refresh

DQ-OUT

Hi-Z

Byte Read

Hi-Z

DQ-OUT

Byte Read

DQ-OUT

Word Read

DQ-IN

Byte Write

DQ-IN

Byte Write

DQ-IN

Word Write

Hi-Z

10.

K4E171611C, K4E151611C

CMOS DRAM

K4E171612C, K4E151612C

ASC

, t

CAH

are referenced to the earlier CAS falling edge.

is specified from the later CAS rising edge in the previous cycle to the earlier CAS falling edge in the next cycle.

CWD

is referenced to the later CAS falling edge at word read-modify-write cycle.

CWL

is specified from W falling edge to the earlier CAS rising edge.

CSR

is referenced to the earlier CAS falling edge before RAS transition low.

CHR

is referenced to the later CAS rising edge after RAS transition low.

CSR

CHR

RAS

LCAS

UCAS

22.

13.

19.

12.

11.

DS,

is independently specified for lower byte DQ(0-7), upper byte DQ(8-15)

ASC

6ns, assume t

=2.0ns.

If RAS goes to high before CAS high going, the open circuit condition of the output is achieved by CAS high going.

If CAS goes to high before RAS high going, the open circuit condition of the output is achieved by RAS high going.

RASS

100us, then RAS precharge time must use

RPS

instead of

For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K)/1024(1K) cycles of burst refresh must be executed

within 64ms/16ms before and after self refresh, in order to meet refresh specification.

For distributed CAS-before-RAS with 15.6us interval, CAS-before-RAS refresh should be executed with in 15.6us immediately

before and after self refresh in order to meet refresh specification.

18.

16.

15.

14.

21.

20.

17.

K4E171611C, K4E151611C

CMOS DRAM

K4E171612C, K4E151612C

CRP

RAS

UCAS

DQ0 ~ DQ7

COLUMN

ADDRESS

ROW

ADDRESS

RAS

CRP

CSH

RSH

RCD

CAS

RAL

ASR

RAH

ASC

CAH

CRP

OEA

CAC

CLZ

RAC

OPEN

CEZ

RCH

Don

t care

Undefined

LCAS

CRP

CSH

RSH

RCD

CAS

RAD

RRH

DQ8 ~ DQ15

CAC

CLZ

RAC

OPEN

DATA-OUT

CEZ

OEZ

RCS

WORD READ CYCLE

OLZ

K4E171611C, K4E151611C

CMOS DRAM

K4E171612C, K4E151612C

NOTE : D

= OPEN

LOWER BYTE READ CYCLE

RAS

LCAS

DQ0 ~ DQ7

COLUMN

ADDRESS

ROW

ADDRESS

RAS

CSH

RSH

RCD

CAS

RAL

RAD

ASR

RAH

ASC

CAH

CRP

OEA

CAC

CLZ

RAC

OPEN

DATA-OUT

OEZ

CEZ

RRH

RCH

Don

t care

Undefined

CRP

RPC

UCAS

OPEN

DQ8 ~ DQ15

RCS

OLZ

K4E171611C, K4E151611C

CMOS DRAM

K4E171612C, K4E151612C

NOTE : D

= OPEN

UPPER BYTE READ CYCLE

RAS

LCAS

DQ0 ~ DQ7

COLUMN

ADDRESS

ROW

ADDRESS

RAS

CRP

CSH

RSH

RCD

CAS

RAL

RAD

ASR

RAH

ASC

CAH

CRP

OEA

CAC

CLZ

RAC

OPEN

DATA-OUT

OEZ

CEZ

RRH

RCH

Don

t care

Undefined

UCAS

OPEN

DQ8 ~ DQ15

CRP

RPC

RCS

OLZ

K4E171611C, K4E151611C

CMOS DRAM

K4E171612C, K4E151612C

RAS

UCAS

COLUMN

ADDRESS

ROW

ADDRESS

RAS

CRP

CSH

RSH

RCD

CAS

RAL

RAD

ASR

RAH

ASC

CAH

CRP

Don

t care

WORD WRITE CYCLE ( EARLY WRITE )

NOTE : D

OUT

= OPEN

Undefined

LCAS

WCS

DQ0 ~ DQ7

DQ8 ~ DQ15

CRP

CSH

RSH

RCD

CAS

CRP

WCH

DATA-IN

K4E171611C, K4E151611C

CMOS DRAM

K4E171612C, K4E151612C

CRP

RAS

UCAS

COLUMN

ADDRESS

ROW

ADDRESS

RAS

RAL

RAD

ASR

RAH

ASC

CAH

Don

t care

LOWER BYTE WRITE CYCLE ( EARLY WRITE )

NOTE : D

OUT

= OPEN

Undefined

LCAS

WCS

DQ0 ~ DQ7

DQ8 ~ DQ15

CRP

CSH

RSH

RCD

CAS

WCH

DATA-IN

CRP

K4E171611C, K4E151611C

CMOS DRAM

K4E171612C, K4E151612C

RAS

UCAS

COLUMN

ADDRESS

ROW

ADDRESS

RAS

CRP

CSH

RSH

RCD

CAS

RAL

RAD

ASR

RAH

ASC

CAH

CRP

Don

t care

UPPER BYTE WRITE CYCLE ( EARLY WRITE )

NOTE : D

OUT

= OPEN

Undefined

LCAS

WCS

DQ0 ~ DQ7

DQ8 ~ DQ15

WCH

DATA-IN

CRP

K4E171611C, K4E151611C

CMOS DRAM

K4E171612C, K4E151612C

RAS

UCAS

ROW

ADDRESS

RAS

CRP

CSH

RSH

RCD

CAS

RAL

RAD

ASR

RAH

ASC

CRP

Don

t care

WORD WRITE CYCLE ( OE CONTROLLED WRITE )

NOTE : D

OUT

= OPEN

Undefined

LCAS

DQ0 ~ DQ7

DQ8 ~ DQ15

CRP

RSH

RCD

CAS

CRP

RWL

CWL

DATA-IN

COLUMN

ADDRESS

OEH

OED

DATA-IN

CSH

CAH

K4E171611C, K4E151611C

CMOS DRAM

K4E171612C, K4E151612C

RAS

UCAS

COLUMN

ADDRESS

ROW

ADDRESS

RAS

RAL

RAD

ASR

RAH

ASC

CAH

Don

t care

LOWER BYTE WRITE CYCLE ( OE CONTROLLED WRITE )

NOTE : D

OUT

= OPEN

Undefined

LCAS

RWL

DQ0 ~ DQ7

DQ8 ~ DQ15

CRP

CSH

RSH

RCD

CAS

CRP

CWL

DATA-IN

CRP

RPC

OEH

OED

K4E171611C, K4E151611C

CMOS DRAM

K4E171612C, K4E151612C

RAS

UCAS

COLUMN

ADDRESS

ROW

ADDRESS

RAS

CRP

CSH

RSH

RCD

CAS

RAL

RAD

ASR

RAH

ASC

CAH

CRP

Don

t care

UPPER BYTE WRITE CYCLE ( OE CONTROLLED WRITE )

NOTE : D

OUT

= OPEN

Undefined

LCAS

CRP

RWL

CWL

DATA-IN

OEH

OED

DQ0 ~ DQ7

DQ8 ~ DQ15

CRP

K4E171611C, K4E151611C

CMOS DRAM

K4E171612C, K4E151612C

RWL

RAS

UCAS

COLUMN

ADDRESS

ROW

ADDR.

RAS

RWC

RSH

RCD

CAS

CSH

RAD

ASR

RAH

ASC

CAH

CRP

Don

t care

WORD READ - MODIFY - WRITE CYCLE

Undefined

LCAS

I/OH

I/OL

DQ0 ~ DQ7

I/OH

I/OL

DQ8 ~ DQ15

CWL

RSH

RCD

CAS

CRP

AWD

CWD

OEA

RWD

OED

OEZ

RAC

OEZ

RAC

OED

VALID

DATA-OUT

VALID

DATA-IN

VALID

DATA-OUT

VALID

DATA-IN

CAC

CLZ

CAC

CLZ

OLZ

K4E171611C, K4E151611C

CMOS DRAM

K4E171612C, K4E151612C

RWL

RAS

UCAS

COLUMN

ADDRESS

ROW

ADDR.

RAS

RWC

CSH

RAD

ASR

RAH

ASC

CAH

CRP

Don

t care

LOWER-BYTE READ - MODIFY - WRITE CYCLE

Undefined

LCAS

I/OH

I/OL

DQ0 ~ DQ7

DQ8 ~ DQ15

CWL

RSH

RCD

CAS

CRP

AWD

CWD

OEA

RWD

OED

OEZ

RAC

VALID

DATA-OUT

VALID

DATA-IN

RPC

CAC

CLZ

OPEN

OLZ

K4E171611C, K4E151611C

CMOS DRAM

K4E171612C, K4E151612C

RWL

RAS

UCAS

COLUMN

ADDRESS

ROW

ADDR

RAS

RWC

RSH

RCD

CAS

CSH

RAD

ASR

RAH

ASC

CAH

CRP

Don

t care

UPPER-BYTE READ - MODIFY - WRITE CYCLE

Undefined

LCAS

DQ0 ~ DQ7

I/OH

I/OL

DQ8 ~ DQ15

CWL

AWD

CWD

OEA

RWD

OEZ

RAC

OED

VALID

DATA-OUT

VALID

DATA-IN

CRP

RPC

CAC

CLZ

OPEN

OLZ

K4E171611C, K4E151611C

CMOS DRAM

K4E171612C, K4E151612C

ASC

OLZ

CLZ

OLZ

CLZ

RAS

UCAS

COLUMN

ADDRESS

ROW

ADDR

RASP

RCD

CRP

Don

t care

HYPER PAGE MODE WORD READ CYCLE

Undefined

LCAS

DQ0 ~ DQ7

DQ8 ~ DQ15

COLUMN

ADDRESS

CAS

REZ

HPC

RHCP

CSH

RCD

CRP

CAS

RAD

RCS

OEA

RCH

RRH

COLUMN

ADDRESS

COLUMN

ADDR

OEZ

OEP

CHO

CPA

CAC

VALID

DATA-OUT

OEP

OEZ

RAC

CAC

DOH

VALID

DATA-OUT

VALID

DATA-OUT

OCH

CPA

CAC

CPA

OEZ

VALID

DATA-OUT

VALID

DATA-OUT

VALID

DATA-OUT

OEP

OEZ

RAC

CAC

VALID

DATA-OUT

VALID

DATA-OUT

OEZ

VALID

DATA-OUT

VALID

DATA-OUT

DOH

OEA

ASR

RAH

ASC

CAH

ASC

CAH

ASC

RAL

K4E171611C, K4E151611C

CMOS DRAM

K4E171612C, K4E151612C

OEA

OLZ

CLZ

RAS

UCAS

COLUMN

ADDRESS

ROW

ADDR

RASP

CRP

Don

t care

HYPER PAGE MODE LOWER BYTE READ CYCLE

Undefined

LCAS

DQ0 ~ DQ7

DQ8 ~ DQ15

COLUMN

ADDRESS

REZ

RHCP

CSH

RCD

CAS

RAD

RCS

RCH

RRH

COLUMN

ADDRESS

COLUMN

ADDR

OEZ

OEP

CHO

CPA

CAC

VALID

DATA-OUT

OEP

OEZ

RAC

CAC

DOH

VALID

DATA-OUT

VALID

DATA-OUT

OCH

CPA

CAC

CPA

OEZ

VALID

DATA-OUT

VALID

DATA-OUT

OPEN

¡ó

RPC

ASR

RAH

ASC

CAH

ASC

CAH

ASC

CAH

ASC

HPC

OEA

RAL

K4E171611C, K4E151611C

CMOS DRAM

K4E171612C, K4E151612C

RAS

UCAS

COLUMN

ADDRESS

ROW

ADDR.

RASP

RCD

ASR

CRP

Don

t care

HYPER PAGE MODE UPPER BYTE READ CYCLE

Undefined

LCAS

DQ0 ~ DQ7

DQ8 ~ DQ15

COLUMN

ADDRESS

CAS

REZ

HPC

RHCP

CSH

CRP

RAH

ASC

CAH

ASC

CAH

RCS

OEA

RCH

RRH

COLUMN

ADDRESS

COLUMN

ADDR.

OEZ

OEP

CHO

CPA

CAC

VALID

DATA-OUT

OEP

OEZ

RAC

CAC

OLZ

CLZ

DOH

VALID

DATA-OUT

VALID

DATA-OUT

OCH

CPA

CAC

CPA

OEZ

VALID

DATA-OUT

VALID

DATA-OUT

OPEN

¡ó

ASC

RPC

RAD

ASC

OEA

RAL

K4E171611C, K4E151611C

CMOS DRAM

K4E171612C, K4E151612C

RAS

UCAS

COLUMN

ADDRESS

ROW

ADDR

RASP

RCD

ASR

CRP

Don

t care

HYPER PAGE MODE WORD WRITE CYCLE ( EARLY WRITE )

Undefined

LCAS

DQ0 ~ DQ7

DQ8 ~ DQ15

CRP

HPC

RHCP

RAD

RAH

CAH

ASC

CAH

ASC

VALID

DATA-IN

¡ó

COLUMN

ADDRESS

COLUMN

ADDRESS

CAS

RSH

¡ó

RCD

CRP

HPC

CAS

RSH

¡ó

CSH

ASC

¡ó

WCS

WCH

WCS

WCH

WCS

WCH

¡ó

VALID

DATA-IN

VALID

DATA-IN

¡ó

VALID

DATA-IN

VALID

DATA-IN

VALID

DATA-IN

¡ó

NOTE : D

OUT

= OPEN

HPC

RAL

K4E171611C, K4E151611C

CMOS DRAM

K4E171612C, K4E151612C

RAS

UCAS

COLUMN

ADDRESS

ROW

ADDR

RASP

ASR

CRP

Don

t care

HYPER PAGE MODE LOWER BYTE WRITE CYCLE ( EARLY WRITE )

Undefined

LCAS

DQ0 ~ DQ7

DQ8 ~ DQ15

RPC

RHCP

RAD

RAH

CAH

ASC

CAH

ASC

VALID

DATA-IN

¡ó

COLUMN

ADDRESS

COLUMN

ADDRESS

RCD

CRP

HPC

CAS

RSH

¡ó

CSH

ASC

¡ó

WCS

WCH

WCS

WCH

WCS

WCH

¡ó

VALID

DATA-IN

VALID

DATA-IN

¡ó

NOTE : D

OUT

= OPEN

RAL

K4E171611C, K4E151611C

CMOS DRAM

K4E171612C, K4E151612C

WCS

RAS

UCAS

COLUMN

ADDRESS

ROW

ADDR

RASP

ASR

CRP

Don

t care

HYPER PAGE MODE UPPER BYTE WRITE CYCLE ( EARLY WRITE )

Undefined

LCAS

DQ0 ~ DQ7

DQ8 ~ DQ15

RPC

RHCP

RAD

RAH

CAH

ASC

CAH

ASC

VALID

DATA-IN

¡ó

COLUMN

ADDRESS

COLUMN

ADDRESS

RCD

CRP

HPC

CAS

RSH

¡ó

CSH

ASC

¡ó

WCH

WCS

WCH

WCS

WCH

¡ó

VALID

DATA-IN

VALID

DATA-IN

¡ó

NOTE : D

OUT

= OPEN

¡ó

RAL

K4E171611C, K4E151611C

CMOS DRAM

K4E171612C, K4E151612C

RAS

UCAS

I/OH

I/OL

DQ0 ~ DQ7

ROW

ADDR

CSH

RASP

ASR

Don

t care

HYPER PAGE MODE WORD READ - MODIFY - WRITE CYCLE

Undefined

RCD

RAD

CAH

COL.

ADDR

COL.

ADDR

CAS

CRP

ASC

CAH

RAL

RCS

CWL

CWD

AWD

RWD

CWD

AWD

CWL

RAC

OEA

CLZ

CAC

OEZ

CPWD

OED

ASC

CLZ

OEA

CAC

OED

LCAS

RCD

CAS

CRP

I/OH

I/OL

DQ8 ~ DQ15

VALID

DATA-OUT

RAC

CLZ

CAC

VALID

DATA-IN

VALID

DATA-OUT

VALID

DATA-IN

CLZ

CAC

OEZ

OED

OEZ

VALID

DATA-OUT

VALID

DATA-IN

VALID

DATA-OUT

VALID

DATA-IN

HPRWC

RSH

RWL

RCS

RAH

K4E171611C, K4E151611C

CMOS DRAM

K4E171612C, K4E151612C

ASC

RAS

I/OH

I/OL

DQ0 ~ DQ7

ROW

ADDR

CSH

RASP

ASR

Don

t care

HYPER PAGE MODE LOWER BYTE READ - MODIFY - WRITE CYCLE

Undefined

RAD

CAH

COL.

ADDR

COL.

ADDR

ASC

CAH

RAL

RCS

CWL

CWD

AWD

RWD

CWD

AWD

CWL

RAC

OEA

CLZ

CAC

OEZ

CPWD

OED

CLZ

OEA

CAC

OED

RWL

RCD

CAS

CRP

I/OH

I/OL

DQ8 ~ DQ15

OEZ

VALID

DATA-OUT

VALID

DATA-IN

VALID

DATA-OUT

VALID

DATA-IN

RPC

RSH

OPEN

LCAS

UCAS

HPRWC

RCS

OLZ

RAH

K4E171611C, K4E151611C

CMOS DRAM

K4E171612C, K4E151612C

ASC

CRP

RAS

I/OH

I/OL

DQ0 ~ DQ7

ROW

ADDR

CSH

RASP

ASR

Don

t care

HYPER PAGE MODE UPPER BYTE READ - MODIFY - WRITE CYCLE

Undefined

RAD

CAH

COL.

ADDR

COL.

ADDR

CAH

RAL

RCS

CWL

CWD

AWD

RWD

CWD

AWD

CWL

RAC

OEA

CLZ

CAC

OEZ

CPWD

OED

CLZ

OEA

CAC

OED

RWL

RCD

CAS

CRP

I/OH

I/OL

DQ8 ~ DQ15

OEZ

VALID

DATA-OUT

VALID

DATA-IN

VALID

DATA-OUT

VALID

DATA-IN

RPC

RSH

OPEN

LCAS

UCAS

HPRWC

ASC

RCS

RAH

OLZ

K4E171611C, K4E151611C

CMOS DRAM

K4E171612C, K4E151612C

HYPER PAGE READ AND WRITE MIXED CYCLE

RAS

COLUMN

ADDRESS

ROW

ADDR

RASP

Don

t care

Undefined

I/OH

I/OL

DQ0 ~ DQ7

WEZ

HPC

RCD

RAH

ASC

CAH

ASC

CAH

RCH

RCS

RCH

ASC

COLUMN

ADDRESS

COL.

ADDR

VALID

DATA-OUT

REZ

WCS

VALID

DATA-OUT

VALID

DATA-OUT

VALID

DATA-IN

RAC

COL.

ADDR

CAS

ASR

CAS

ASC

RCH

WCH

WPE

CLZ

CPA

WED

WEZ

CAC

OEA

HPC

CAS

I/OH

I/OL

DQ8 ~ DQ15

WEZ

VALID

DATA-OUT

REZ

VALID

DATA-OUT

VALID

DATA-OUT

VALID

DATA-IN

RAC

WEZ

CAC

OEA

LCAS

UCAS

HPC

READ(

CAC

)

READ(

CPA

)

WRITE

READ(

)

RAD

RHCP

RAL

K4E171611C, K4E151611C

CMOS DRAM

K4E171612C, K4E151612C

CRP

OPEN

RAS

UCAS

ROW

ADDR

ASR

CRP

RAS - ONLY REFRESH CYCLE

LCAS

RAS

RAH

NOTE : W, OE , D

= Don

t care

OUT

= OPEN

RPC

CAS - BEFORE - RAS REFRESH CYCLE

NOTE : OE, A = Don

t care

RAS

UCAS

LCAS

RAS

RPC

CSR

CHR

CSR

CHR

CEZ

OPEN

DQ0 ~ DQ7

DQ8 ~ DQ15

Don

t care

Undefined

K4E171611C, K4E151611C

CMOS DRAM

K4E171612C, K4E151612C

OEZ

DATA-IN

DATA-OUT

RAS

UCAS

ROW

ADDRESS

RAS

CHR

RCD

RSH

RAD

ASR

RAH

ASC

CRP

Don

t care

HIDDEN REFRESH CYCLE ( READ )

Undefined

LCAS

DQ0 ~ DQ7

DQ8 ~ DQ15

RSH

RCD

CRP

WRH

COLUMN

ADDRESS

OEA

RAS

CHR

CAH

RCS

RAC

CLZ

CAC

DATA-OUT

CEZ

OPEN

REZ

WEZ

OLZ

RAL

K4E171611C, K4E151611C

CMOS DRAM

K4E171612C, K4E151612C

WCS

RAS

UCAS

ROW

ADDRESS

RAS

CHR

RCD

RSH

RAD

ASR

RAH

ASC

CRP

Don

t care

HIDDEN REFRESH CYCLE ( WRITE )

Undefined

LCAS

DQ0 ~ DQ7

DQ8 ~ DQ15

RSH

RCD

CRP

WRH

COLUMN

ADDRESS

RAS

CHR

CAH

WRP

NOTE : D

OUT

= OPEN

WCH

DATA-IN

K4E171611C, K4E151611C

CMOS DRAM

K4E171612C, K4E151612C

42 SOJ

400mil

.
4

(
1

.
1

)

.
4

(
1

.
0

)

.
4

(
1

.
3

)

1.080 (27.43)

1.070 (27.19)

MAX

1.091 (27.71)

.
1

(
3

.
7

)

0.032 (0.81)

0.026 (0.66)

0.021 (0.53)

0.015 (0.38)

0.027 (0.69)

0.012 (0.30)

0.006 (0.15)

.
3

(
9

.
1

)

.
3

(
9

.
6

)

MIN

#42

0.0375 (0.95)

0.050 (1.27)

Units : Inches (millimeters)

50(44) TSOP(II) 400mil

Units : Inches (millimeters)

MAX

0.047 (1.20)

MIN

0.002 (0.05)

0.018 (0.45)

0.010 (0.25)

0.0315 (0.80)

0.034 (0.875)

0.821 (20.85)
0.829 (21.05)

0.841 (21.35)

MAX

0.010 (0.25)

0.004 (0.10)

.
4

(
1

.
1

)

.
4

(
1

.
9

)

.
4

(
1

.
5

)

0~8

0.030 (0.75)

0.018 (0.45)

TYP

0.010 (0.25)

PACKAGE DIMENSION

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: K4E171611C

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: K4E171611C