DRAM MODULE

M374F160(8)0DJ1-C

M374F160(8)0DJ1-C EDO Mode without buffer
16M x 72 DRAM DIMM with ECC Using 16Mx4, 4K & 8K Refresh, 3.3V

The Samsung M374F160(8)0DJ1-C is a 16Mx72bits Dynamic
RAM high density memory module. The Samsung
M374F160(8)0DJ1-C consists of eighteen CMOS 16Mx4bits
DRAMs in SOJ 400mil packages and one 1K/2K EEPROM for
SPD in 8-pin SOP package mounted on a 168-pin glass-
epoxy substrate. A 0.1 or 0.22uF decoupling capacitor is
mounted on the printed circuit board for each DRAM. The

M374F160(8)0DJ1-C is a Dual In-line Memory Module and is
intended for mounting into 168 pin edge connector sockets.

GENERAL DESCRIPTION

FEATURES

· Part Identification

· New JEDEC standard proposal without buffer

· Serial Presence Detect with EEPROM

· Extended Data Out Mode Operation

· CAS-before-RAS Refresh capability

· RAS-only and Hidden refresh capability

· LVTTL compatible inputs and outputs

· Single +3.3V

0.3V power supply

· PCB : Height(1000mil), double sided component

Part number

Ref.

CBR

ROR

M374F1600DJ1-C

SOJ

4K/64ms

M374F1680DJ1-C

SOJ

4K/64ms

8K/64ms

PIN CONFIGURATIONS

NOTE : A12 is used for only M374F1680DJ1-C (8K ref.)

Pin

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

Front

DQ0
DQ1
DQ2
DQ3

DQ4
DQ5
DQ6
DQ7
DQ8

DQ9

DQ10
DQ11
DQ12
DQ13

DQ14
DQ15

CB0
CB1

NC
NC

CAS0

Pin

29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56

Front

CAS1
RAS0

OE0

A0
A2
A4
A6
A8

A10
A12
V

OE2

RAS2
CAS2
CAS3

NC
NC

CB2
CB3

DQ16
DQ17

Pin

57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84

Front

DQ18
DQ19

DQ20

NC
DU
NC

DQ21
DQ22
DQ23

DQ24
DQ25
DQ26
DQ27

DQ28
DQ29
DQ30
DQ31

NC
NC
NC

SDA

SCL

Pin

85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

100
101
102
103
104
105
106
107
108
109
110
111
112

Back

DQ32
DQ33
DQ34
DQ35

DQ36
DQ37
DQ38
DQ39
DQ40

DQ41
DQ42
DQ43
DQ44
DQ45

DQ46
DQ47

CB4
CB5

NC
NC

CAS4

Pin

113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140

Back

CAS5

*RAS1

A1
A3
A5
A7
A9

A11

*A13

DU
DU

*RAS3

CAS6
CAS7

NC
NC

CB6
CB7

DQ48
DQ49

Pin

141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168

Back

DQ50
DQ51

DQ52

NC
DU
NC

DQ53
DQ54
DQ55

DQ56
DQ57
DQ58
DQ59

DQ60
DQ61
DQ62
DQ63

NC
NC

SA0
SA1
SA2

PIN NAMES

* These pins are not used in this module.

Pin Name

Function

A0 - A11

Address Input(4K ref.)

A0 - A12

Address Input(8K ref.)

DQ0 - DQ63

Data In/Out

W0, W2

Read/Write Enable

OE0, OE2

Output Enable

RAS0, RAS2

Row Address Strobe

CAS0 - CAS7

Column Address Strobe

Power(+3.3V)

Ground

No Connection

Don

t use

SDA

Serial Address/Data I/O

SCL

Serial Clock

SA0 - SA2

Address in EEPROM

CB0 - CB7

Check Bit

PERFORMANCE RANGE

Speed

RAC

CAC

HPC

-C50

50ns

13ns

84ns

20ns

-C60

60ns

15ns

104ns

25ns

DRAM MODULE

M374F160(8)0DJ1-C

FUNCTIONAL BLOCK DIAGRAM

Vss

0.1 or 0.22uF Capacitor
under each DRAM

To all DRAMs

RAS0

OE0

A0-A11(A12)

CAS0

CAS1

CAS2

CAS3

DQ0
DQ1
DQ2
DQ3

RAS2

OE2

Serial PD

SDA

SCL

SA1 SA2

SA0

DQ0
DQ1
DQ2
DQ3

DQ4
DQ5
DQ6
DQ7

DQ0
DQ1
DQ2
DQ3

DQ8
DQ9
DQ10
DQ11

DQ0
DQ1
DQ2
DQ3

DQ12
DQ13
DQ14
DQ15

DQ0
DQ1
DQ2
DQ3

CB0
CB1
CB2
CB3

DQ0
DQ1
DQ2
DQ3

DQ16
DQ17
DQ18
DQ19

DQ0
DQ1
DQ2
DQ3

DQ20
DQ21
DQ22
DQ23

DQ0
DQ1
DQ2
DQ3

DQ24
DQ25
DQ26
DQ27

DQ0
DQ1
DQ2
DQ3

DQ28
DQ29
DQ30
DQ31

DQ0
DQ1
DQ2
DQ3

DQ32
DQ33
DQ34
DQ35

DQ0
DQ1
DQ2
DQ3

DQ36
DQ37
DQ38
DQ39

U10

DQ0
DQ1
DQ2
DQ3

U11

DQ40
DQ41
DQ42
DQ43

DQ0
DQ1
DQ2
DQ3

DQ44
DQ45
DQ46
DQ47

U12

DQ0
DQ1
DQ2
DQ3

CB4
CB5
CB6
CB7

U13

DQ0
DQ1
DQ2
DQ3

U14

DQ48
DQ49
DQ50
DQ51

DQ0
DQ1
DQ2
DQ3

DQ52
DQ53
DQ54
DQ55

U15

DQ0
DQ1
DQ2
DQ3

U16

DQ56
DQ57
DQ58
DQ59

DQ0
DQ1
DQ2
DQ3

DQ60
DQ61
DQ62
DQ63

U17

CAS4

CAS5

CAS6

CAS7

NOTE : A12 is used for only M374F1680DJ1 (8K ref.)

DRAM MODULE

M374F160(8)0DJ1-C

CC1

, I

CC3

, I

CC4

and I

CC6

are dependent on output loading and cycle rates. Specified values are obtained with the output open.

is specified as an average current. In I

CC1

and I

CC3

, address can be changed maximum once while RAS=V

. In I

CC4

address can be changed maximum once within one EDO mode cycle time,

HPC

* NOTE :

ABSOLUTE MAXIMUM RATINGS *

* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to

the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.

Item

Symbol

Rating

Unit

Voltage on any pin relative V

Voltage on V

supply relative to V

Storage Temperature
Power Dissipation

Short Circuit Output Current

, V

OUT

stg

-0.5 to +4.6
-0.5 to +4.6
-55 to +150

V
V

RECOMMENDED OPERATING CONDITIONS

(Voltage referenced to V

, T

= 0 to 70

*1 : V

+1.3V at pulse width

15ns which is measured at V

*2 : -1.3V at pulse width

15ns which is measured at V

Item

Symbol

Min

Typ

Max

Unit

Supply Voltage
Ground
Input High Voltage
Input Low Voltage

3.0

2.0

-0.3

3.3

-
-

3.6

+0.3

0.8

V
V
V
V

DC AND OPERATING CHARACTERISTICS

(Recommended operating conditions unless otherwise noted)

CC1

CC2

CC3

CC4

CC5

CC6

IL)

OL)

Symbol

Speed

M374F1680DJ1

M374F1600DJ1

Unit

Min

Max

Min

Max

CC1

-50
-60

-
-

1440
1260

-
-

1980
1800

mA
mA

CC2

Don

t care

CC3

-50
-60

-
-

1440
1260

-
-

1980
1800

mA
mA

CC4

-50
-60

-
-

1620
1440

-
-

1620
1440

mA
mA

CC5

Don

t care

CC6

-50
-60

-
-

1980
1800

-
-

1980
1800

mA
mA

I(L)

O(L)

Don

t care

-10

-5

-10

-5

uA
uA

Don

t care

2.4

0.4

2.4

0.4

V
V

: Operating Current * (RAS, CAS, Address cycling @

=min)

: Standby Current (RAS=CAS=W=V

)

: RAS Only Refresh Current * (CAS=V

, RAS cycling @

=min)

: Extended Data Out Mode Current * (RAS=V

, CAS cycling :

HPC

=min)

: Standby Current (RAS=CAS=W=V

-0.2V)

: CAS-Before-RAS Refresh Current * (RAS and CAS cycling @

=min)

: Input Leakage Current (Any input 0

+0.3V, all other pins not under test=0 V)

: Output Leakage Current(Data Out is disabled, 0V

OUT

)

: Output High Voltage Level (I

= -2mA)

: Output Low Voltage Level (I

= 2mA)

DRAM MODULE

M374F160(8)0DJ1-C

CAPACITANCE

= 25

C, V

=3.3V, f = 1MHz)

Item

Symbol

Min

Max

Unit

Input capacitance[A0-A12]

Input capacitance[W0, W2, OE0, OE2]

Input capacitance[RAS0, RAS2]

Input capacitance[CAS0 - CAS7]

Input/Output capacitance[DQ0-DQ63, CB0-CB7]

IN1

IN2

IN3

IN4

CDQ

100

AC CHARACTERISTICS

C, V

=3.3V

0.3V. See notes 1,2.)

Test condition : V

=2.2/0.7V, V

=2.0/0.8V, output loading C

=100pF

Parameter

Symbol

-50

-60

Unit

Note

Min

Max

Min

Max

Random read or write cycle time

104

Read-modify-write cycle time

RWC

128

153

Access time from RAS

RAC

3,4,9

Access time from CAS

CAC

3,4,5

Access time from column address

3,9

CAS to output in Low-Z

CLZ

OE to output in Low-Z

OLZ

Output buffer turn-off delay from CAS

CEZ

6,10

Transition time(rise and fall)

RAS precharge time

RAS pulse width

RAS

10K

RAS hold time

RSH

CAS hold time

CSH

CAS pulse width

CAS

10K

RAS to CAS delay time

RCD

RAS to column address delay time

RAD

CAS to RAS precharge time

CRP

Row address set-up time

ASR

Row address hold time

RAH

Column address set-up time

ASC

Column address hold time

CAH

Column address to RAS lead time

RAL

Read command set-up time

RCS

Read command hold referenced to CAS

RCH

Read command hold referenced to RAS

RRH

Write command hold time

WCH

Write command pulse width

Write command to RAS lead time

RWL

Write command to CAS lead time

CWL

Data set-up time

Data hold time

Refresh period (4K & 8K Ref.)

REF

Write command set-up time

WCS

CAS to W delay time

CWD

RAS to W delay time

RWD

DRAM MODULE

M374F160(8)0DJ1-C

AC CHARACTERISTICS

C, V

=3.3V

0.3V. See notes 1,2.)

Test condition : V

=2.2/0.7V, V

=2.0/0.8V, output loading C

=100pF

Parameter

Symbol

-50

-60

Unit

Note

Min

Max

Min

Max

Column address to W delay time

AWD

CAS precharge to W delay time

CPWD

CAS setup time (CAS-before-RAS refresh)

CSR

CAS hold time (CAS-before-RAS refresh)

CHR

RAS to CAS precharge time

RPC

Access time from CAS precharge

CPA

Hyper page mode cycle time

HPC

Hyper page mode read-modify write cycle time

HPRWC

CAS precharge time (Hyper page cycle)

RAS pulse width (Hyper page cycle)

RASP

200K

RAS hold time from CAS precharge

RHCP

OE access time

OEA

OE to data delay

OED

Output buffer turn off delay time from OE

OEZ

OE command hold time

OEH

Output data hold time

DOH

Output buffer turn off delay from RAS

REZ

6,10

Output buffer turn off delay from W

WEZ

W to data delay

WED

OE to CAS hold time

OCH

CAS hold time to OE

CHO

OE precharge time

OEP

W pulse width (Hyper page cycle)

WPE

DRAM MODULE

M374F160(8)0DJ1-C

NOTES

An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.

Input voltage levels are V

. V

(min) and V

(max) are ref-

erence levels for measuring timing of input signals. Transi-
tion times are measured between V

(min) and V

(max) and

are assumed to be 5ns for all inputs.

Measured with a load equivalent to 1 TTL loads and 100pF.

Operation within the

RCD

(max) limit insures that

RAC

(max)

can be met.

RCD

(max) is specified as a reference point only.

RCD

is greater than the specified

RCD

(max) limit, then

access time is controlled exclusively by

CAC

Assumes that

RCD

(max).

This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to V

WCS

RWD

CWD

and

AWD

are non-restrictive operating

parameter. They are inclueded in the data sheet as electrical

characteristics only. If

WCS

(min), the cycle is an early

write cycle and the data out pin will remain high impedance

for the duration of the cycle. If

CWD

(min),

RWD

(min) and

AWD

(min), then the cycle is a

read-write cycle and the data output will contain the data
read from the selected address. If neither of the above conti-
tions are satisfied, The condition of the data out is indeterni-
mated.

Either

RCH

RRH

must be satisfied for a read cycle.

Operation within the

RAD

(max) limit insures that

RAC

(max)

can be met.

RAD

(max) is specified as a reference point only.

RAD

is greater than the specified

RAD

(max) limit, then

access time is controlled exclusively by

If RAS goes to high before CAS high going, the open circuit
condtion of the output is achieved by CAS high going. If CAS
goes to high before RAS high going, the open circuit cond-
tion of the output is achieved by RAS high going.

ASC

6ns.

10.

11.

DRAM MODULE

M374F160(8)0DJ1-C

DOH

HYPER PAGE READ CYCLE

RAS

CAS

COLUMN

ADDRESS

ROW

ADDR

RASP

RCD

ASR

CRP

Don

t care

Undefined

OEP

COLUMN

ADDRESS

CAS

HPC

RHCP

CSH

RAD

RAH

ASC

CAH

ASC

CAH

RCS

RCH

ASC

COLUMN

ADDRESS

COLUMN

ADDR

VALID

DATA-OUT

OEZ

OEA

OEP

CAC

OEA

CPA

CAC

CPA

VALID

DATA-OUT

VALID

DATA-OUT

OEZ

CLZ

RAC

OEA

OLZ

CAC

RRH

CHO

REZ

OEZ

CAC

OCH

CPA

CAC

VALID

DATA-OUT

¡ó

ASC

DRAM MODULE

M374F160(8)0DJ1-C

RAS

CAS

COLUMN

ADDRESS

ROW

ADDR.

RASP

RCD

ASR

CRP

Don

t care

HYPER PAGE WRITE CYCLE ( EARLY WRITE )

Undefined

RHCP

RAD

RAH

CAH

ASC

CAH

ASC

VALID

DATA-IN

¡ó

COLUMN

ADDRESS

COLUMN

ADDRESS

CAS

RSH

¡ó

CSH

ASC

¡ó

WCS

WCH

WCS

WCH

WCS

WCH

¡ó

VALID

DATA-IN

VALID

DATA-IN

¡ó

CWL

RWL

NOTE : D

OUT

= OPEN

HPC

DRAM MODULE

M374F160(8)0DJ1-C

Don

t care

HYPER PAGE READ-MODIFY-WRITE CYCLE

Undefined

RAS

CAS

I/OH

I/OL

ROW

ADDR

CSH

RASP

ASR

RAH

RCD

RAD

CAH

COL.

ADDR

COL.

ADDR

CAS

CRP

ASC

CAH

RAL

RCS

CWL

CWD

AWD

RWD

CWD

AWD

CWL

RAC

OEA

CLZ

OEZ

CPWD

OED

ASC

CLZ

OEA

CAC

OED

RWL

CRP

OEZ

VALID

DATA-OUT

VALID

DATA-IN

VALID

DATA-OUT

VALID

DATA-IN

RSH

OLZ

HPRWC

CAC

DRAM MODULE

M374F160(8)0DJ1-C

HYPER PAGE READ AND WRITE MIXED CYCLE

RAS

CAS

COLUMN

ADDRESS

ROW

ADDR

RASP

Don

t care

Undefined

I/OH

I/OL

WEZ

HPC

RAD

RAH

ASC

CAH

ASC

CAH

RCH

RCS

RCH

ASC

COLUMN

ADDRESS

COL.

ADDR

VALID

DATA-OUT

REZ

WCS

VALID

DATA-OUT

VALID

DATA-OUT

VALID

DATA-IN

RAC

COL.

ADDR

CAS

ASR

CAS

ASC

RCH

WCH

WPE

CLZ

CPA

WED

WEZ

CAC

OEA

READ(

CAC

)

READ(

CPA

)

WRITE

READ(

)

DRAM MODULE

M374F160(8)0DJ1-C

Don

t care

RAS - ONLY REFRESH CYCLE*

NOTE : W, OE, D

= Don

t care

Undefined

OUT

= OPEN

RAS

CAS

ROW

ADDR

ASR

CRP

RAS

RAH

RPC

CRP

OPEN

CAS - BEFORE - RAS REFRESH CYCLE

NOTE : OE , A = Don

t care

RAS

CAS

RAS

RPC

CSR

CHR

CEZ

WRP

WRH

* In RAS-only refresh cycle of 64Mb A-dile & B-die, when CAS signal transits from Low to High, the valid data may be cut off.

DRAM MODULE

M374F160(8)0DJ1-C

CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE

RAS

CAS

COLUMN

ADDRESS

RAS

RSH

CHR

RAL

CSR

CPT

CAS

ASC

CAH

READ CYCLE

DATA-OUT

REZ

CLZ

WRITE CYCLE

DATA-IN

CWD

CWL

RWL

READ-MODIFY-WRITE

AWD

OEA

CAC

VALID

DATA-OUT

I/OH

I/OL

Don

t care

Undefined

OEA

OEZ

RCS

CLZ

OEZ

OED

WRP

WRH

RRH

RCH

RCS

CAC

WRP

WRH

WCS

WCH

CWL

RWL

WRP

WRH

VALID

DATA-IN

NOTE : This timing diagram is applied to all devices besides 64M DRAM based modules.

CEZ

WEZ

DRAM MODULE

M374F160(8)0DJ1-C

PACKAGE DIMENSIONS

Units : Inches (millimeters)

0.050

0.039

.002

0.010Max

(0.250 Max)

0.350Max
(8.89Max)

0.050

0.0039

Tolerances :

.005(.13) unless otherwise specified

The used device is 16Mx4 DRAM with EDO mode, SOJ
DRAM Part No. : M374F1680DJ1 - K4E660412D

(1.270

0.10)

(1.000

.050)

(1.270)

.
1

i
n

(
2

.
5

i
n

)

Detail C

0.250

(6.350)

Detail A

0.1230

.0050

(3.125

.125)

0.250

(6.350)

Detail B

0.1230

.0050

(3.125

.125)

0.079

.0040

(2.000

.100)

0.079

.0040

(2.000

.100)

M374F1600DJ1 - K4E640412D

5.250

5.014

R 0.079

(R 2.000)

0.250

(6.350)

1.450

(36.830)

2.150

(54.61)

0.350

.
1

i
n

(
2

.
5

i
n

)

.
7

(
1

.
7

)

.118DIA

.004

(3.000DIA

.100)

(8.890)

0.250

(6.350)

.450
(11.430)

4.550

(115.57)

0.157

0.004

(4.000

0.100)

0.054

(1.372)

(127.350)

(133.350)

.
0

(
2

.
4

)

0.118

(3.000)

.
1

(
3

.
0

)

( Front view )

( Back view )

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