CMOS DRAM
K4E660411D,
K4E640411D
This is a family of 16,777,216 x 4 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random
access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time ( -50, or -60), package type (SOJ or TSOP-
II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities.
This 16Mx4 EDO Mode DRAM family is fabricated using Samsung
s advanced CMOS process to realize high band-width, low power
consumption and high reliability.
Extended Data Out Mode operation
CAS-before-RAS refresh capability
RAS-only and Hidden refresh capability
Fast parallel test mode capability
TTL(5.0V) compatible inputs and outputs
Early Write or output enable controlled write
JEDEC Standard pinout
Available in Plastic SOJ and TSOP(II) packages
+5.0V
10% power supply
Control
Clocks
RAS
CAS
W
Vcc
Vss
A0~A12
(A0~A11)*1
A0~A10
(A0~A11)*1
Memory Array
16,777,216 x 4
Cells
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
16M x 4bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
Note) *1 : 4K Refresh
Performance Range
Speed
t
RAC
t
CAC
t
RC
t
PC
-50
50ns
13ns
84ns
20ns
-60
60ns
15ns
104ns
25ns
Active Power Dissipation
Speed
8K
4K
-50
495
660
-60
440
605
Unit : mW
S
e
n
s
e
A
m
p
s
&
I
/
O
DQ0
to
DQ3
Data out
Buffer
Data in
Buffer
Row Decoder
Column Decoder
VBB Generator
Refresh Timer
Refresh Control
Refresh Counter
Row Address Buffer
Col. Address Buffer
OE
Part Identification
- K4E660411D-JC(5.0V, 8K Ref., SOJ)
- K4E640411D-JC(5.0V, 4K Ref., SOJ)
- K4E660411D-TC(5.0V, 8K Ref., TSOP)
- K4E640411D-TC(5.0V, 4K Ref., TSOP)
FEATURES
Refresh Cycles
Part
NO.
Refresh
cycle
Refresh time
Normal
K4E660411D*
8K
64ms
K4E640411D
4K
* Access mode & RAS only refresh mode
: 8K cycle/64ms
CAS-before-RAS & Hidden refresh mode
: 4K cycle/64ms
CMOS DRAM
K4E660411D,
K4E640411D
V
CC
DQ0
DQ1
N.C
N.C
N.C
N.C
W
RAS
A0
A1
A2
A3
A4
A5
V
CC
V
SS
DQ3
DQ2
N.C
N.C
N.C
CAS
OE
A12(N.C)*
A11
A10
A9
A8
A7
A6
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PIN CONFIGURATION (Top Views)
* (N.C) : N.C for 4K Refresh product
Pin Name
Pin Function
A0 - A12
Address Inputs(8K Product)
A0 - A11
Address Inputs(4K Product)
DQ0 - 3
Data In/Out
V
SS
Ground
RAS
Row Address Strobe
CAS
Column Address Strobe
W
Read/Write Input
OE
Data Output Enable
V
CC
Power(+5.0V)
N.C
No Connection
V
CC
DQ0
DQ1
N.C
N.C
N.C
N.C
W
RAS
A0
A1
A2
A3
A4
A5
V
CC
V
SS
DQ3
DQ2
N.C
N.C
N.C
CAS
OE
A12(N.C)*
A11
A10
A9
A8
A7
A6
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
(T : 400mil TSOP(II))
(J : 400mil SOJ)
K4E660411D-J
K4E640411D-J
K4E660411D-T
K4E640411D-T
CMOS DRAM
K4E660411D,
K4E640411D
ABSOLUTE MAXIMUM RATINGS
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Parameter
Symbol
Rating
Units
Voltage on any pin relative to V
SS
V
IN,
V
OUT
-1.0 to +7.0
V
Voltage on V
CC
supply relative to V
SS
V
CC
-1.0 to +7.0
V
Storage Temperature
Tstg
-55 to +150
C
Power Dissipation
P
D
1
W
Short Circuit Output Current
I
OS
Address
50
mA
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to Vss, T
A
= 0 to 70
C)
*1 : V
CC
+2.0V at pulse width
20ns which is measured at V
CC
*2 : -2.0 at pulse width
20ns which is measured at V
SS
Parameter
Symbol
Min
Typ
Max
Units
Supply Voltage
V
CC
4.5
5.0
5.5
V
Ground
V
SS
0
0
0
V
Input High Voltage
V
IH
2.6
-
V
CC
+1.0
*1
V
Input Low Voltage
V
IL
-1.0
*2
-
0.7
V
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter
Symbol
Min
Max
Units
Input Leakage Current (Any input 0
V
IN
V
CC
+0.5V,
all other pins not under test=0 Volt)
I
I(L)
-5
5
uA
Output Leakage Current
(Data out is disabled, 0V
V
OUT
V
CC
)
I
O(L)
-5
5
uA
Output High Voltage Level(I
OH
=-5mA)
V
OH
2.4
-
V
Output Low Voltage Level(I
OL
=4.2mA)
V
OL
-
0.4
V
CMOS DRAM
K4E660411D,
K4E640411D
*Note :
I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
, I
CC3
and I
CC6,
address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one EDO mode cycle time,
t
HPC
.
DC AND OPERATING CHARACTERISTICS
(Continued)
I
CC1
* : Operating Current (RAS and CAS, Address cycling @
t
RC
=min.)
I
CC2
: Standby Current (RAS=CAS=W=V
IH
)
I
CC3
* : RAS-only Refresh Current (CAS=V
IH
, RAS, Address cycling @
t
RC
=min.)
I
CC4
* : Extended Data Out Mode Current (RAS=V
IL
, CAS, Address cycling @
t
HPC
=min.)
I
CC5
: Standby Current (RAS=CAS=W=V
CC
-0.2V)
I
CC6
* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @
t
RC
=min)
Symbol
Power
Speed
Max
Units
K4E660411D
K4E640411D
I
CC1
Don
t care
-50
-60
90
80
120
110
mA
mA
I
CC2
Normal
Don
t care
2
2
mA
I
CC3
Don
t care
-50
-60
90
80
120
110
mA
mA
I
CC4
Don
t care
-50
-60
100
90
110
100
mA
mA
I
CC5
Normal
Don
t care
1
1
mA
I
CC6
Don
t care
-50
-60
120
110
120
110
mA
mA
CMOS DRAM
K4E660411D,
K4E640411D
CAPACITANCE
(T
A
=25
C, V
CC
=5.0V, f=1MHz)
Parameter
Symbol
Min
Max
Units
Input capacitance [A0 ~ A12]
C
IN1
-
5
pF
Input capacitance [RAS, CAS, W, OE]
C
IN2
-
7
pF
Output capacitance [DQ0 - DQ3]
C
DQ
-
7
pF
AC CHARACTERISTICS
(0
C
T
A
70
C, See note 1,2)
Test condition : V
CC
=5.0V
10%, Vih/Vil=2.6/0.7V, Voh/Vol=2.0/0.8V
Parameter
Symbol
-50
-60
Units
Note
Min
Max
Min
Max
Random read or write cycle time
t
RC
84
104
ns
Read-modify-write cycle time
t
RWC
116
138
ns
Access time from RAS
t
RAC
50
60
ns
3,4,10
Access time from CAS
t
CAC
13
15
ns
3,4,5
Access time from column address
t
AA
25
30
ns
3,10
CAS to output in Low-Z
t
CLZ
3
3
ns
3
Output buffer turn-off delay from CAS
t
CEZ
3
13
3
13
ns
6,14
OE to output in Low-Z
t
OLZ
3
3
ns
3
Transition time (rise and fall)
t
T
1
50
1
50
ns
2
RAS precharge time
t
RP
30
40
ns
RAS pulse width
t
RAS
50
10K
60
10K
ns
RAS hold time
t
RSH
13
15
ns
CAS hold time
t
CSH
38
45
ns
CAS pulse width
t
CAS
8
10K
10
10K
ns
RAS to CAS delay time
t
RCD
20
37
20
45
ns
4
RAS to column address delay time
t
RAD
15
25
15
30
ns
10
CAS to RAS precharge time
t
CRP
5
5
ns
Row address set-up time
t
ASR
0
0
ns
Row address hold time
t
RAH
10
10
ns
Column address set-up time
t
ASC
0
0
ns
Column address hold time
t
CAH
8
10
ns
Column address to RAS lead time
t
RAL
25
30
ns
Read command set-up time
t
RCS
0
0
ns
8
Read command hold time referenced to CAS
t
RCH
0
0
ns
8
Read command hold time referenced to RAS
t
RRH
0
0
ns
Write command hold time
t
WCH
10
10
ns
Write command pulse width
t
WP
10
10
ns
Write command to RAS lead time
t
RWL
13
10
ns
Write command to CAS lead time
t
CWL
8
10
ns
Data set-up time
t
DS
0
0
ns
9
CMOS DRAM
K4E660411D,
K4E640411D
AC CHARACTERISTICS
(Continued)
Parameter
Symbol
-50
-60
Units
Note
Min
Max
Min
Max
Data hold time
t
DH
8
10
ns
9
Refresh period (4K, Normal)
t
REF
64
64
ms
Refresh period (8K, Normal)
t
REF
64
64
ms
Write command set-up time
t
WCS
0
0
ns
7
CAS to W delay time
t
CWD
30
32
ns
7
RAS to W delay time
t
RWD
67
77
ns
7
Column address to W delay time
t
AWD
42
47
ns
7
CAS set-up time (CAS -before-RAS refresh)
t
CSR
5
5
ns
CAS hold time (CAS -before-RAS refresh)
t
CHR
10
10
ns
RAS to CAS precharge time
t
RPC
5
5
ns
Access time from CAS precharge
t
CPA
28
35
ns
3
Hyper Page cycle time
t
HPC
20
25
ns
13
Hyper Page read-modify-write cycle time
t
HPRWC
47
56
ns
13
CAS precharge time (Hyper page cycle)
t
CP
8
10
ns
RAS pulse width (Hyper page cycle)
t
RASP
50
200K
60
200K
ns
RAS hold time from CAS precharge
t
RHCP
30
35
ns
OE access time
t
OEA
13
15
ns
OE to data delay
t
OED
13
13
ns
CAS precharge to W delay time
t
CPWD
45
54
ns
Output buffer turn off delay time from OE
t
OEZ
3
13
3
13
ns
6
OE command hold time
t
OEH
13
15
ns
Write command set-up time (Test mode in)
t
WTS
10
10
ns
11
Write command hold time (Test mode in)
t
WTH
10
10
ns
11
W to RAS precharge time (C-B-R refresh)
t
WRP
10
10
ns
W to RAS hold time (C-B-R refresh)
t
WRH
10
10
ns
Output data hold time
t
DOH
5
5
ns
Output buffer turn off delay from RAS
t
REZ
3
13
3
13
ns
6,14
Output buffer turn off delay from W
t
WEZ
3
13
3
13
ns
6
W to data delay
t
WED
15
15
ns
OE to CAS hold time
t
OCH
5
5
ns
CAS hold time to OE
t
CHO
5
5
ns
OE precharge time
t
OEP
5
5
ns
W pulse width (Hyper page Cycle)
t
WPE
5
5
ns
RAS pulse width (C-B-R self refresh)
t
RASS
100
100
us
15,16,17
RAS precharge time (C-B-R self refresh)
t
RPS
90
110
ns
15,16,17
CAS hold time (C-B-R self refresh)
t
CHS
-50
-50
ns
15,16,17
CMOS DRAM
K4E660411D,
K4E640411D
TEST MODE CYCLE
Parameter
Symbol
-50
-60
Units
Note
Min
Max
Min
Max
Random read or write cycle time
t
RC
89
109
ns
Read-modify-write cycle time
t
RWC
121
145
ns
Access time from RAS
t
RAC
55
65
ns
3,4,10,12
Access time from CAS
t
CAC
18
20
ns
3,4,5,12
Access time from column address
t
AA
30
35
ns
3,10,12
RAS pulse width
t
RAS
55
10K
65
10K
ns
CAS pulse width
t
CAS
13
10K
15
10K
ns
RAS hold time
t
RSH
18
20
ns
CAS hold time
t
CSH
43
50
ns
Column Address to RAS lead time
t
RAL
30
35
ns
CAS to W delay time
t
CWD
35
39
ns
7
RAS to W delay time
t
RWD
72
84
ns
7
Column Address to W delay time
t
AWD
47
54
ns
7
Hyper Page cycle time
t
HPC
25
30
ns
13
Hyper Page read-modify-write cycle time
t
HPRWC
53
61
ns
13
RAS pulse width (Hyper page cycle)
t
RASP
55
200K
65
200K
ns
Access time from CAS precharge
t
CPA
33
40
ns
3
OE access time
t
OEA
18
20
ns
OE to data delay
t
OED
18
20
ns
OE command hold time
t
OEH
18
20
ns
( Note 11 )
CMOS DRAM
K4E660411D,
K4E640411D
NOTES
An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles
before proper device operation is achieved.
V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals. Transition times are measured between
V
IH
(min) and V
IL
(max) and are assumed to be 2ns for all inputs.
Measured with a load equivalent to 2 TTL load and 100pF.
Operation within the
t
RCD
(max) limit insures that
t
RAC
(max) can be met.
t
RCD
(max) is specified as a reference point only.
If
t
RCD
is greater than the specified
t
RCD
(max) limit, then access time is controlled exclusively by
t
CAC
.
Assumes that
t
RCD
t
RCD
(max).
This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V
oh
or V
ol
.
t
WCS
,
t
RWD
,
t
CWD
and
t
AWD
are non restrictive operating parameters. They are included in the data sheet as electrical char-
acteristics only. If
t
WCS
t
WCS
(min), the cycle is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If
t
CWD
t
CWD
(min),
t
RWD
t
RWD
(min) and
t
AWD
t
AWD
(min), then the cycle is a read-modify-write cycle
and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the
condition of the data out is indeterminate.
Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in OE controlled write cycle
and read-modify-write cycles.
Operation within the
t
RAD
(max) limit insures that
t
RAC
(max) can be met.
t
RAD
(max) is specified as a reference point only.
If
t
RAD
is greater than the specified
t
RAD
(max) limit, then access time is controlled by
t
AA
.
These specifications are applied in the test mode.
In test mode read cycle, the value of
t
RAC
,
t
AA
,
t
CAC
is delayed by 2ns to 5ns for the specified values. These parameters
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
t
ASC
6ns, Assume t
T
= 2.0ns
If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes
high before RAS high going, the open circuit condition of the output is achieved by RAS high going.
If
t
RASS
100us, then RAS precharge time must use
t
RPS
instead of
t
RP
.
For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K/8K) cycles of burst refresh must be executed within
64ms before and after self refresh, in order to meet refresh specification.
For distributed CAS-before-RAS with 15.6us interval CAS-before-RAS refresh should be executed with in 15.6us immedi-
ately before and after self refresh in order to meet refresh specification.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
1.
2.
3.
4.
17.
CMOS DRAM
K4E660411D,
K4E640411D
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
V
OH
-
V
OL
-
COLUMN
ADDRESS
ROW
ADDRESS
t
RAS
t
RC
t
CRP
t
RP
t
CSH
t
RSH
t
RCD
t
CAS
t
RAL
t
ASR
t
RAH
t
ASC
t
CAH
t
CRP
t
AA
t
OEA
t
CLZ
t
RAC
OPEN
t
RCH
Don
t care
Undefined
t
RAD
t
RRH
DATA-OUT
t
REZ
t
RCS
READ CYCLE
t
OEZ
t
CEZ
t
WEZ
DQ0 ~ DQ3(7)
t
OLZ
t
CAC
CMOS DRAM
K4E660411D,
K4E640411D
t
WCS
NOTE : D
OUT
= OPEN
WRITE CYCLE ( EARLY WRITE )
RAS
V
IH
-
V
IL
-
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDRESS
t
RAS
t
RC
t
CRP
t
RP
t
CSH
t
RSH
t
RCD
t
CAS
t
RAL
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
CRP
Don
t care
Undefined
t
WCH
t
WP
CAS
t
RWL
t
CWL
t
DS
t
DH
DATA-IN
DQ0 ~ DQ3(7)
CMOS DRAM
K4E660411D,
K4E640411D
NOTE : D
OUT
= OPEN
WRITE CYCLE ( OE CONTROLLED WRITE )
RAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
V
IH
-
V
IL
-
DQ0 ~ DQ3(7)
COLUMN
ADDRESS
ROW
ADDRESS
t
RAS
t
RC
t
CRP
t
RP
t
CSH
t
RSH
t
RCD
t
CAS
t
RAL
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
CRP
t
WP
Don
t care
Undefined
CAS
V
IH
-
V
IL
-
t
RWL
t
CWL
t
DH
t
OEH
t
OED
DATA-IN
t
DS
CMOS DRAM
K4E660411D,
K4E640411D
READ - MODIFY - WRITE CYCLE
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
V
I/OH
-
V
I/OL
-
DQ0 ~ DQ3(7)
ROW
ADDR
t
RAS
t
RWC
t
RP
t
RSH
t
RCD
t
CAS
t
CSH
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
CRP
VALID
t
WP
Don
t care
t
RWL
t
CWL
t
OEZ
t
OEA
t
OED
t
AWD
t
CWD
t
RWD
DATA-OUT
Undefined
VALID
DATA-IN
t
RAC
t
AA
t
CAC
t
CLZ
t
DS
t
DH
COLUMN
ADDRESS
t
OLZ
CMOS DRAM
K4E660411D,
K4E640411D
t
DOH
HYPER PAGE READ CYCLE
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDR
t
RASP
t
RP
t
RCD
t
ASR
t
CRP
Don
t care
Undefined
V
OH
-
V
OL
-
DQ0 ~ DQ3(7)
t
OEP
COLUMN
ADDRESS
t
CAS
t
CAS
t
CAS
t
CAS
t
CP
t
CP
t
CP
t
HPC
t
HPC
t
HPC
t
RHCP
t
CSH
t
RAD
t
RAH
t
ASC
t
CAH
t
CAH
t
CAH
t
ASC
t
CAH
t
RCS
t
AA
t
RCH
t
ASC
COLUMN
ADDRESS
COLUMN
ADDR
VALID
DATA-OUT
t
OEZ
t
OEA
t
OEP
t
AA
t
CAC
t
AA
t
CPA
t
CPA
VALID
DATA-OUT
VALID
DATA-OUT
t
OEZ
t
CLZ
t
RAC
t
OEA
t
OLZ
t
CAC
t
RRH
t
CHO
t
REZ
t
OEZ
t
CAC
t
OCH
t
CPA
t
CAC
VALID
DATA-OUT
t
ASC
t
AA
t
RAL
t
OEA
CMOS DRAM
K4E660411D,
K4E640411D
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDR.
t
RASP
t
RP
t
RCD
t
ASR
t
CRP
Don
t care
HYPER PAGE WRITE CYCLE ( EARLY WRITE )
Undefined
V
IH
-
V
IL
-
DQ0 ~ DQ3(7)
t
RHCP
t
RAD
t
RAH
t
CAH
t
CAH
t
ASC
t
CAH
t
ASC
VALID
DATA-IN
t
DS
COLUMN
ADDRESS
COLUMN
ADDRESS
t
CAS
t
CP
t
CAS
t
CP
t
CAS
t
RSH
t
CSH
t
ASC
t
WP
t
WCS
t
WCH
t
WP
t
WCS
t
WCH
t
WP
t
WCH
VALID
DATA-IN
VALID
DATA-IN
t
DH
t
DS
t
DH
t
DS
t
DH
t
CWL
t
CWL
t
CWL
t
RWL
NOTE : D
OUT
= OPEN
t
HPC
t
HPC
t
WCS
t
RAL
CMOS DRAM
K4E660411D,
K4E640411D
Don
t care
HYPER PAGE READ-MODIFY-WRITE CYCLE
Undefined
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
V
I/OH
-
V
I/OL
-
ROW
ADDR
t
CSH
t
RASP
t
RP
t
ASR
t
RCD
t
CP
t
RAD
t
CAH
t
WP
t
DH
COL.
ADDR
COL.
ADDR
t
CAS
t
CAS
t
CRP
t
ASC
t
CAH
t
RAL
t
RCS
t
CWL
t
CWD
t
AWD
t
RWD
t
WP
t
CWD
t
AWD
t
CWL
t
RAC
t
OEA
t
CLZ
t
OEZ
t
CPWD
t
OED
t
ASC
t
CLZ
t
OEA
t
CAC
t
AA
t
DH
t
OED
t
RWL
t
CRP
t
DS
t
OEZ
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
t
DS
DQ0 ~ DQ3(7)
t
RSH
t
OLZ
t
OLZ
t
HPRWC
t
CAC
t
AA
t
RAH
CMOS DRAM
K4E660411D,
K4E640411D
HYPER PAGE READ AND WRITE MIXED CYCLE
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDR
t
RASP
t
RP
Don
t care
Undefined
V
I/OH
-
V
I/OL
-
DQ0 ~ DQ3(7)
t
WEZ
t
CP
t
CP
t
HPC
t
HPC
t
HPC
t
RAD
t
RAH
t
ASC
t
CAH
t
CAH
t
CAH
t
ASC
t
CAH
t
RCH
t
RCS
t
RCS
t
RCH
t
ASC
COLUMN
ADDRESS
COL.
ADDR
VALID
DATA-OUT
t
REZ
t
AA
t
WCS
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-IN
t
RAC
COL.
ADDR
t
CAS
t
ASR
t
CAS
t
CAS
t
CAS
t
ASC
t
CP
t
RCH
t
WCH
t
WPE
t
CLZ
t
CPA
t
WED
t
AA
t
WEZ
t
DS
t
DH
t
CAC
t
OEA
READ(
t
CAC
)
READ(
t
CPA
)
WRITE
READ(
t
AA
)
t
RHCP
t
RAL
t
CLZ
CMOS DRAM
K4E660411D,
K4E640411D
Don
t care
RAS - ONLY REFRESH CYCLE*
NOTE : W, OE, D
IN
= Don
t care
Undefined
D
OUT
= OPEN
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
ROW
ADDR
t
RC
t
RP
t
ASR
t
CRP
t
RAS
t
RAH
t
RPC
t
CRP
OPEN
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE , A = Don
t care
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
t
RC
t
RP
t
RAS
t
RPC
t
CP
t
RPC
t
CSR
t
CHR
t
CEZ
V
OH
-
V
OL
-
DQ0 ~ DQ3(7)
t
WRP
t
WRH
W
V
IH
-
V
IL
-
t
RP
CMOS DRAM
K4E660411D,
K4E640411D
HIDDEN REFRESH CYCLE ( READ )
t
OEZ
DATA-OUT
t
RP
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
ROW
ADDRESS
t
RAS
t
RC
t
CHR
t
RCD
t
RSH
t
RAD
t
ASR
t
RAH
t
ASC
t
CRP
Don
t care
Undefined
V
OH
-
V
OL
-
DQ0 ~ DQ3(7)
t
WRH
COLUMN
ADDRESS
t
OEA
t
RAS
t
RC
t
CAH
t
RCS
t
AA
t
RAC
t
CLZ
t
CAC
t
CEZ
OPEN
t
RP
t
WEZ
t
REZ
t
OLZ
* In Hidden refresh cycle of 64Mb A-dile & B-die, when CAS signal transits from Low to High, the valid data may be cut off.
t
RAL
CMOS DRAM
K4E660411D,
K4E640411D
t
CRP
t
WCS
t
RP
RAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
ROW
ADDRESS
t
RAS
t
RC
t
RAD
t
ASR
t
RAH
t
ASC
Don
t care
HIDDEN REFRESH CYCLE ( WRITE )
Undefined
CAS
V
IH
-
V
IL
-
V
IH
-
V
IL
-
DQ0 ~ DQ3(7)
t
RSH
t
RCD
t
WRH
COLUMN
ADDRESS
t
RAS
t
RC
t
CHR
t
CAH
t
WRP
t
DS
NOTE : D
OUT
= OPEN
t
WP
t
WCH
DATA-IN
t
DH
t
RP
t
RAL
CMOS DRAM
K4E660411D,
K4E640411D
OPEN
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE, A = Don
t care
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
t
RPS
t
RASS
t
RPC
t
CP
t
RPC
t
CSR
t
CEZ
V
OH
-
V
OL
-
DQ0 ~ DQ3(7)
t
RP
Don
t care
Undefined
t
CHS
t
WRP
t
WRH
W
V
IH
-
V
IL
-
OPEN
TEST MODE IN CYCLE
NOTE : OE , A = Don
t care
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
t
RP
t
RC
t
RPC
t
CP
t
RPC
t
CSR
t
OFF
V
OH
-
V
OL
-
DQ0 ~ DQ3(7)
t
WTS
t
WTH
W
V
IH
-
V
IL
-
t
CHR
t
RP
t
RAS
CMOS DRAM
K4E660411D,
K4E640411D
32 SOJ
400mil
0
.
4
0
0
(
1
0
.
1
6
)
0
.
4
3
5
(
1
1
.
0
6
)
0
.
4
4
5
(
1
1
.
3
0
)
0.830 (21.08)
0.820 (20.84)
MAX
0.841 (21.36)
M
A
X
0
.
1
4
8
(
3
.
7
6
)
0.032 (0.81)
0.026 (0.66)
0.021 (0.53)
0.015 (0.38)
0.027 (0.69)
0.012 (0.30)
0.006 (0.15)
0
.
3
6
0
(
9
.
1
5
)
0
.
3
8
0
(
9
.
6
5
)
MIN
#32
#1
0.0375 (0.95)
0.050 (1.27)
Units : Inches (millimeters)
PACKAGE DIMENSION
32 TSOP(II)
400mil
0
.
4
5
5
(
1
1
.
5
6
)
0
.
4
7
1
(
1
1
.
9
6
)
0.829 (21.05)
0.821 (20.85)
MAX
0.841 (21.35)
0.037 (0.95)
0.050 (1.27)
Units : Inches (millimeters)
0.047 (1.20)
MIN
0.002 (0.05)
0.020 (0.50)
0.012 (0.30)
MAX
0.010 (0.25)
0.004 (0.10)
0
.
4
0
0
(
1
0
.
1
6
)
0~8
0.030 (0.75)
0.018 (0.45)
TYP
0.010 (0.25)
O
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