CMOS DRAM

K4E661612C,K4E641612C

This is a family of 4,194,304 x 16 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random

access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption(Nor-

mal or Low power) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden

refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 4Mx16 EDO Mode DRAM family is fabricated

using Samsung

s advanced CMOS process to realize high band-width, low power consumption and high reliability.

· Extended Data Out Mode operation

· 2 CAS Byte/Word Read/Write operation

· CAS-before-RAS refresh capability

· RAS-only and Hidden refresh capability

· Fast parallel test mode capability

· Self-refresh capability (L-ver only)

· LVTTL(3.3V) compatible inputs and outputs

· Early Write or output enable controlled write

· JEDEC Standard pinout

· Available in Plastic TSOP(II) packages

· +3.3V

0.3V power supply

Control
Clocks

Lower

Data out

Buffer

RAS

UCAS

LCAS

Vcc
Vss

DQ0

DQ7

A0~A12

(A0~A11)*1

A0~A8

(A0~A9)*1

Memory Array

4,194,304 x 16

Cells

SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.

4M x 16bit CMOS Dynamic RAM with Extended Data Out

DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

Note) *1 : 4K Refresh

I
/
O

Upper

Data in

Buffer

Upper

Data out

Buffer

Lower

Data in

Buffer

DQ8

DQ15

Row Decoder

Column Decoder

VBB Generator

Refresh Timer

Refresh Control

Refresh Counter

Row Address Buffer

Col. Address Buffer

Part Identification

- K4E661612C-TC/L(3.3V, 8K Ref.)
- K4E641612C-TC/L(3.3V, 4K Ref.)

FEATURES

Refresh Cycles

Part

NO.

Refresh

cycle

Refresh time

Normal

L-ver

K4E661612C*

64ms

128ms

K4E641612C

Unit :

* Access mode & RAS only refresh mode
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)

CAS-before-RAS & Hidden refresh mode

: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)

Active Power Dissipation

Speed

-45

324

468

-50

288

432

-60

252

396

· Performance Range

Speed

RAC

CAC

HPC

-45

45ns

12ns

74ns

17ns

-50

50ns

13ns

84ns

20ns

-60

60ns

15ns

104ns

25ns

CMOS DRAM

K4E661612C,K4E641612C

DQ0
DQ1
DQ2
DQ3

DQ4
DQ5
DQ6
DQ7

N.C

RAS

N.C
N.C
N.C
N.C

A0
A1
A2
A3
A4
A5

DQ15
DQ14
DQ13
DQ12
V

DQ11
DQ10
DQ9
DQ8
N.C
V

LCAS
UCAS
OE
N.C
N.C
A12(N.C)*
A11
A10
A9
A8
A7
A6
V

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

PIN CONFIGURATION (Top Views)

Pin Name

Pin function

A0 - A12

Address Inputs(8K Product)

A0 - A11

Address Inputs(4K Product)

DQ0 - 15

Data In/Out

Ground

RAS

Row Address Strobe

UCAS

Upper Column Address Strobe

LCAS

Lower Column Address Strobe

Read/Write Input

Data Output Enable

Power(+3.3V)

N.C

No Connection

(400mil TSOP(II))

*(N.C) : N.C for 4K Refresh Product

· K4E661612C-T
· K4E641612C-T

CMOS DRAM

K4E661612C,K4E641612C

ABSOLUTE MAXIMUM RATINGS

* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to

the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

Parameter

Symbol

Rating

Units

Voltage on any pin relative to V

IN,

OUT

-0.5 to +4.6

Voltage on V

supply relative to V

-0.5 to +4.6

Storage Temperature

Tstg

-55 to +150

Power Dissipation

Short Circuit Output Current

Address

RECOMMENDED OPERATING CONDITIONS

(Voltage referenced to Vss, T

= 0 to 70

*1 : Vcc+1.3V at pulse width

15ns which is measured at V

*2 : -1.3 at pulse width

15ns which is measured at V

Parameter

Symbol

Min

Typ

Max

Units

Supply Voltage

3.0

3.3

3.6

Ground

Input High Voltage

2.0

Vcc+0.3

Input Low Voltage

-0.3

0.8

DC AND OPERATING CHARACTERISTICS

(Recommended operating conditions unless otherwise noted.)

Parameter

Symbol

Min

Max

Units

Input Leakage Current (Any input 0

+0.3V,

all other pins not under test=0 Volt)

I(L)

-5

Output Leakage Current
(Data out is disabled, 0V

OUT

)

O(L)

-5

Output High Voltage Level(I

=-2mA)

2.4

Output Low Voltage Level(I

=2mA)

0.4

CMOS DRAM

K4E661612C,K4E641612C

*Note :

CC1

, I

CC3

, I

CC4

and I

CC6

are dependent on output loading and cycle rates. Specified values are obtained with the output open.

is specified as an average current. In I

CC1

, I

CC3

and I

CC6,

address can be changed maximum once while RAS=V

. In I

CC4

address can be changed maximum once within one EDO mode cycle time,

HPC

DC AND OPERATING CHARACTERISTICS

(Continued)

CC1

* : Operating Current (RAS and UCAS, LCAS, Address cycling @

=min.)

CC2

: Standby Current (RAS=UCAS=LCAS=W=V

)

CC3

* : RAS-only Refresh Current (UCAS=LCAS=V

, RAS, Address cycling @

=min.)

CC4

* : Extended Data Out Mode Current (RAS=V

, UCAS or LCAS, Address cycling @

HPC

=min.)

CC5

: Standby Current (RAS=UCAS=LCAS=W=V

-0.2V)

CC6

* : CAS-Before-RAS Refresh Current (RAS and UCAS or LCAS cycling @

=min)

CC7

: Battery back-up current, Average power supply current, Battery back-up mode

Input high voltage(V

)=V

-0.2V, Input low voltage(V

)=0.2V, UCAS, LCAS=CAS-before-RAS cycling or 0.2V

W, OE=V

, Address=Don

t care, DQ=Open, T

=31.25us

CCS

: Self Refresh Current

RAS=UCAS=LCAS=0.2V, W=OE=A0 ~ A12(A11)=V

-0.2V or 0.2V, DQ0 ~ DQ15=V

-0.2V, 0.2V or Open

Symbol

Power

Speed

Max

Units

K4E661612C

K4E641612C

CC1

Don

t care

-45
-50
-60

90
80
70

130
120
110

mA
mA
mA

CC2

Normal

Don

t care

1
1

mA
mA

CC3

Don

t care

-45
-50
-60

90
80
70

130
120
110

mA
mA
mA

CC4

Don

t care

-45
-50
-60

100

90
80

100

90
80

mA
mA
mA

CC5

Normal

Don

t care

0.5

200

0.5

200

CC6

Don

t care

-45
-50
-60

130
120
110

mA
mA
mA

CC7

Don

t care

350

CCS

Don

t care

350

CMOS DRAM

K4E661612C,K4E641612C

CAPACITANCE

=25

C, V

=3.3V, f=1MHz)

Parameter

Symbol

Min

Max

Units

Input capacitance [A0 ~ A12]

IN1

Input capacitance [RAS, UCAS, LCAS, W, OE]

IN2

Output capacitance [DQ0 - DQ15]

AC CHARACTERISTICS

C, See note 2)

Test condition : V

=3.3V

0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V

Parameter

Symbol

-45

-50

-60

Unit

Note

Min

Max

Min

Max

Min

Max

Random read or write cycle time

104

Read-modify-write cycle time

RWC

101

113

138

Access time from RAS

RAC

3,4,10

Access time from CAS

CAC

3,4,5

Access time from column address

3,10

CAS to output in Low-Z

CLZ

Output buffer turn-off delay from CAS

CEZ

6,20

OE to output in Low-Z

OLZ

Transition time (rise and fall)

RAS precharge time

RAS pulse width

RAS

10K

RAS hold time

RSH

CAS hold time

CSH

CAS pulse width

CAS

10K

RAS to CAS delay time

RCD

RAS to column address delay time

RAD

CAS to RAS precharge time

CRP

Row address set-up time

ASR

Row address hold time

RAH

Column address set-up time

ASC

Column address hold time

CAH

Column address to RAS lead time

RAL

Read command set-up time

RCS

Read command hold time referenced to CAS

RCH

Read command hold time referenced to RAS

RRH

Write command hold time

WCH

Write command pulse width

Write command to RAS lead time

RWL

Write command to CAS lead time

CWL

Data set-up time

9,19

CMOS DRAM

K4E661612C,K4E641612C

AC CHARACTERISTICS

(Continued)

Parameter

Symbol

-45

-50

-60

Units

Note

Min

Max

Min

Max

Min

Max

Data hold time

9,19

Refresh period (Normal)

REF

Refresh period (L-ver)

REF

128

Write command set-up time

WCS

CAS to W delay time

CWD

7,15

RAS to W delay time

RWD

Column address to W delay time

AWD

CAS set-up time (CAS -before-RAS refresh)

CSR

CAS hold time (CAS -before-RAS refresh)

CHR

RAS to CAS precharge time

RPC

Access time from CAS precharge

CPA

Hyper Page cycle time

HPC

Hyper Page read-modify-write cycle time

HPRWC

CAS precharge time (Hyper page cycle)

6.5

RAS pulse width (Hyper page cycle)

RASP

200K

RAS hold time from CAS precharge

RHCP

OE access time

OEA

OE to data delay

OED

CAS precharge to W delay time

CPWD

Output buffer turn off delay time from OE

OEZ

OE command hold time

OEH

Write command set-up time (Test mode in)

WTS

Write command hold time (Test mode in)

WTH

W to RAS precharge time (C-B-R refresh)

WRP

W to RAS hold time (C-B-R refresh)

WRH

Output data hold time

DOH

Output buffer turn off delay from RAS

REZ

6,20

Output buffer turn off delay from W

WEZ

W to data delay

WED

OE to CAS hold time

OCH

CAS hold time to OE

CHO

OE precharge time

OEP

W pulse width (Hyper Page Cycle)

WPE

RAS pulse width (C-B-R self refresh)

RASS

100

22,23,24

RAS precharge time (C-B-R self refresh)

RPS

110

22,23,24

CAS hold time (C-B-R self refresh)

CHS

-50

22,23,24

CMOS DRAM

K4E661612C,K4E641612C

TEST MODE CYCLE

Parameter

Symbol

-45

-50

-60

Units

Note

Min

Max

Min

Max

Min

Max

Random read or write cycle time

109

Read-modify-write cycle time

RWC

110

121

145

Access time from RAS

RAC

3,4,10,12

Access time from CAS

CAC

3,4,5,12

Access time from column address

3,10,12

RAS pulse width

RAS

10K

CAS pulse width

CAS

10K

RAS hold time

RSH

CAS hold time

CSH

Column Address to RAS lead time

RAL

CAS to W delay time

CWD

RAS to W delay time

RWD

Column Address to W delay time

AWD

Hyper Page cycle time

HPC

Hyper Page read-modify-write cycle time

HPRWC

RAS pulse width (Hyper page cycle)

RASP

200K

Access time from CAS precharge

CPA

OE access time

OEA

OE to data delay

OED

OE command hold time

OEH

( Note 11 )

CMOS DRAM

K4E661612C,K4E641612C

NOTES

An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before

proper device operation is achieved.

Input voltage levels are Vih/Vil. V

(min) and V

(max) are reference levels for measuring timing of input signals. Transition

times are measured between V

(min) and V

(max) and are assumed to be 2ns for all inputs.

Measured with a load equivalent to 1 TTL load and 100pF.

Operation within the

RCD

(max) limit insures that

RAC

(max) can be met.

RCD

(max) is specified as a reference point only.

RCD

is greater than the specified

RCD

(max) limit, then access time is controlled exclusively by

CAC

Assumes that

RCD

(max).

This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V

or V

WCS

RWD

CWD

and

AWD

are non restrictive operating parameters. They are included in the data sheet as electric charac-

teristics only. If

WCS

(min), the cycles is an early write cycle and the data output will remain high impedance for the

duration of the cycle. If

CWD

(min),

RWD

(min) and

AWD

(min), then the cycle is a read-modify-write cycle

and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the

condition of the data out is indeterminate.

Either

RCH

RRH

must be satisfied for a read cycle.

This parameters are referenced to the CAS leading edge in early write cycles and to the W falling edge in OE controlled write

cycle and read-modify-write cycles.

Operation within the

RAD

(max) limit insures that

RAC

(max) can be met.

RAD

(max) is specified as a reference point only. If

RAD

is greater than the specified

RAD

(max) limit, then access time is controlled by

These specifiecations are applied in the test mode.

In test mode read cycle, the value of

RAC

CAC

is delayed by 2ns to 5ns for the specified values. These parameters

should be specified in test mode cycles by adding the above value to the specified value in this data sheet.

ASC

CAH

are referenced to the earlier CAS falling edge.

is specified from the last CAS rising edge in the previous cycle to the first CAS falling edge in the next cycle.

CWD

is referenced to the later CAS falling edge at word read-modify-write cycle.

K4E64(6)1612C Truth Table

RAS

LCAS

UCAS

DQ0 - DQ7

DQ8-DQ15

STATE

Hi-Z

Standby

Hi-Z

Refresh

DQ-OUT

Hi-Z

Byte Read

Hi-Z

DQ-OUT

Byte Read

DQ-OUT

Word Read

DQ-IN

Byte Write

DQ-IN

Byte Write

DQ-IN

Word Write

Hi-Z

10.

13.

12.

11.

15.

14.

CMOS DRAM

K4E661612C,K4E641612C

CWL

is specified from W falling edge to the earlier CAS rising edge.

CSR

is referenced to earlier CAS falling before RAS transition low.

CHR

is referenced to the later CAS rising high after RAS transition low.

is specified for the earlier CAS falling edge and

is specified by the later CAS falling edge in early write cycle.

If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going.

ASC

6ns, Assume t

=2.0ns, if t

ASC

6ns, then t

HPC

(min) and t

CAS

(min) must be increased by the value of "6ns-t

ASC

RASS

100us, then RAS precharge time must use

RPS

instead of

For RAS-only-Refresh and Burst CAS-before-RAS refresh mode, 4096 cycles(4K/8K) of burst refresh must be executed within

64ms before and after self refresh, in order to meet refresh specification.

For distributed CAS-before-RAS with 15.6us interval, CBR refresh should be executed with in 15.6us immediately before and

after self refresh in order to meet refresh specification.

CSR

CHR

RAS

LCAS

UCAS

LCAS

UCAS

DQ0 ~ DQ15

Din

22.

21.

20.

19.

18.

17.

16.

23.

24.

CMOS DRAM

K4E661612C,K4E641612C

CRP

RAS

UCAS

DQ0 ~ DQ7

COLUMN

ADDRESS

ROW

ADDRESS

RAS

CRP

CSH

RSH

RCD

CAS

RAL

ASR

RAH

ASC

CAH

CRP

OEA

CAC

CLZ

RAC

OPEN

CEZ

RCH

Don

t care

Undefined

LCAS

CRP

CSH

RSH

RCD

CAS

RAD

RRH

DQ8 ~ DQ15

CAC

CLZ

RAC

OPEN

DATA-OUT

CEZ

OEZ

RCS

WORD READ CYCLE

OLZ

CMOS DRAM

K4E661612C,K4E641612C

RAS

UCAS

ROW

ADDRESS

RAS

CRP

CSH

RSH

RCD

CAS

RAL

RAD

ASR

RAH

ASC

CRP

Don

t care

WORD WRITE CYCLE ( OE CONTROLLED WRITE )

NOTE : D

OUT

= OPEN

Undefined

LCAS

DQ0 ~ DQ7

DQ8 ~ DQ15

CRP

RSH

RCD

CAS

CRP

RWL

CWL

DATA-IN

COLUMN

ADDRESS

OEH

OED

DATA-IN

CSH

CAH

CMOS DRAM

K4E661612C,K4E641612C

RWL

RAS

UCAS

COLUMN

ADDRESS

ROW

ADDR.

RAS

RWC

RSH

RCD

CAS

CSH

RAD

ASR

RAH

ASC

CAH

CRP

Don

t care

WORD READ - MODIFY - WRITE CYCLE

Undefined

LCAS

I/OH

I/OL

DQ0 ~ DQ7

I/OH

I/OL

DQ8 ~ DQ15

CWL

RSH

RCD

CAS

CRP

AWD

CWD

OEA

RWD

OED

OEZ

RAC

OEZ

RAC

OED

VALID

DATA-OUT

VALID

DATA-IN

VALID

DATA-OUT

VALID

DATA-IN

CAC

CLZ

CAC

CLZ

OLZ

CMOS DRAM

K4E661612C,K4E641612C

RWL

RAS

UCAS

COLUMN

ADDRESS

ROW

ADDR.

RAS

RWC

CSH

RAD

ASR

RAH

ASC

CAH

CRP

Don

t care

LOWER-BYTE READ - MODIFY - WRITE CYCLE

Undefined

LCAS

I/OH

I/OL

DQ0 ~ DQ7

DQ8 ~ DQ15

CWL

RSH

RCD

CAS

CRP

AWD

CWD

OEA

RWD

OED

OEZ

RAC

VALID

DATA-OUT

VALID

DATA-IN

RPC

CAC

CLZ

OPEN

OLZ

CMOS DRAM

K4E661612C,K4E641612C

RWL

RAS

UCAS

COLUMN

ADDRESS

ROW

ADDR

RAS

RWC

RSH

RCD

CAS

CSH

RAD

ASR

RAH

ASC

CAH

CRP

Don

t care

UPPER-BYTE READ - MODIFY - WRITE CYCLE

Undefined

LCAS

DQ0 ~ DQ7

I/OH

I/OL

DQ8 ~ DQ15

CWL

AWD

CWD

OEA

RWD

OEZ

RAC

OED

VALID

DATA-OUT

VALID

DATA-IN

CRP

RPC

CAC

CLZ

OPEN

OLZ

CMOS DRAM

K4E661612C,K4E641612C

ASC

OLZ

CLZ

OLZ

CLZ

RAS

UCAS

COLUMN

ADDRESS

ROW

ADDR

RASP

RCD

CRP

Don

t care

HYPER PAGE MODE WORD READ CYCLE

Undefined

LCAS

DQ0 ~ DQ7

DQ8 ~ DQ15

COLUMN

ADDRESS

CAS

REZ

HPC

RHCP

CSH

RCD

CRP

CAS

RAD

RCS

OEA

RCH

RRH

COLUMN

ADDRESS

COLUMN

ADDR

OEZ

OEP

CHO

CPA

CAC

VALID

DATA-OUT

OEP

OEZ

RAC

CAC

DOH

VALID

DATA-OUT

VALID

DATA-OUT

OCH

CPA

CAC

CPA

OEZ

VALID

DATA-OUT

VALID

DATA-OUT

VALID

DATA-OUT

OEP

OEZ

RAC

CAC

VALID

DATA-OUT

VALID

DATA-OUT

OEZ

VALID

DATA-OUT

VALID

DATA-OUT

DOH

OEA

ASR

RAH

ASC

CAH

ASC

CAH

ASC

RAL

CMOS DRAM

K4E661612C,K4E641612C

OEA

OLZ

CLZ

RAS

UCAS

COLUMN

ADDRESS

ROW

ADDR

RASP

CRP

Don

t care

HYPER PAGE MODE LOWER BYTE READ CYCLE

Undefined

LCAS

DQ0 ~ DQ7

DQ8 ~ DQ15

COLUMN

ADDRESS

REZ

RHCP

CSH

RCD

CAS

RAD

RCS

RCH

RRH

COLUMN

ADDRESS

COLUMN

ADDR

OEZ

OEP

CHO

CPA

CAC

VALID

DATA-OUT

OEP

OEZ

RAC

CAC

DOH

VALID

DATA-OUT

VALID

DATA-OUT

OCH

CPA

CAC

CPA

OEZ

VALID

DATA-OUT

VALID

DATA-OUT

OPEN

¡ó

RPC

ASR

RAH

ASC

CAH

ASC

CAH

ASC

CAH

ASC

HPC

OEA

RAL

CMOS DRAM

K4E661612C,K4E641612C

RAS

UCAS

COLUMN

ADDRESS

ROW

ADDR.

RASP

RCD

ASR

CRP

Don

t care

HYPER PAGE MODE UPPER BYTE READ CYCLE

Undefined

LCAS

DQ0 ~ DQ7

DQ8 ~ DQ15

COLUMN

ADDRESS

CAS

REZ

HPC

RHCP

CSH

CRP

RAH

ASC

CAH

ASC

CAH

RCS

OEA

RCH

RRH

COLUMN

ADDRESS

COLUMN

ADDR.

OEZ

OEP

CHO

CPA

CAC

VALID

DATA-OUT

OEP

OEZ

RAC

CAC

OLZ

CLZ

DOH

VALID

DATA-OUT

VALID

DATA-OUT

OCH

CPA

CAC

CPA

OEZ

VALID

DATA-OUT

VALID

DATA-OUT

OPEN

¡ó

ASC

RPC

RAD

ASC

OEA

RAL

CMOS DRAM

K4E661612C,K4E641612C

RAS

UCAS

COLUMN

ADDRESS

ROW

ADDR

RASP

RCD

ASR

CRP

Don

t care

HYPER PAGE MODE WORD WRITE CYCLE ( EARLY WRITE )

Undefined

LCAS

DQ0 ~ DQ7

DQ8 ~ DQ15

CRP

HPC

RHCP

RAD

RAH

CAH

ASC

CAH

ASC

VALID

DATA-IN

¡ó

COLUMN

ADDRESS

COLUMN

ADDRESS

CAS

RSH

¡ó

RCD

CRP

HPC

CAS

RSH

¡ó

CSH

ASC

¡ó

WCS

WCH

WCS

WCH

WCS

WCH

¡ó

VALID

DATA-IN

VALID

DATA-IN

¡ó

VALID

DATA-IN

VALID

DATA-IN

VALID

DATA-IN

¡ó

NOTE : D

OUT

= OPEN

HPC

RAL

CMOS DRAM

K4E661612C,K4E641612C

RAS

UCAS

COLUMN

ADDRESS

ROW

ADDR

RASP

ASR

CRP

Don

t care

HYPER PAGE MODE LOWER BYTE WRITE CYCLE ( EARLY WRITE )

Undefined

LCAS

DQ0 ~ DQ7

DQ8 ~ DQ15

RPC

RHCP

RAD

RAH

CAH

ASC

CAH

ASC

VALID

DATA-IN

¡ó

COLUMN

ADDRESS

COLUMN

ADDRESS

RCD

CRP

HPC

CAS

RSH

¡ó

CSH

ASC

¡ó

WCS

WCH

WCS

WCH

WCS

WCH

¡ó

VALID

DATA-IN

VALID

DATA-IN

¡ó

NOTE : D

OUT

= OPEN

RAL

CMOS DRAM

K4E661612C,K4E641612C

WCS

RAS

UCAS

COLUMN

ADDRESS

ROW

ADDR

RASP

ASR

CRP

Don

t care

HYPER PAGE MODE UPPER BYTE WRITE CYCLE ( EARLY WRITE )

Undefined

LCAS

DQ0 ~ DQ7

DQ8 ~ DQ15

RPC

RHCP

RAD

RAH

CAH

ASC

CAH

ASC

VALID

DATA-IN

¡ó

COLUMN

ADDRESS

COLUMN

ADDRESS

RCD

CRP

HPC

CAS

RSH

¡ó

CSH

ASC

¡ó

WCH

WCS

WCH

WCS

WCH

¡ó

VALID

DATA-IN

VALID

DATA-IN

¡ó

NOTE : D

OUT

= OPEN

¡ó

RAL

CMOS DRAM

K4E661612C,K4E641612C

RAS

UCAS

I/OH

I/OL

DQ0 ~ DQ7

ROW

ADDR

CSH

RASP

ASR

Don

t care

HYPER PAGE MODE WORD READ - MODIFY - WRITE CYCLE

Undefined

RCD

RAD

CAH

COL.

ADDR

COL.

ADDR

CAS

CRP

ASC

CAH

RAL

RCS

CWL

CWD

AWD

RWD

CWD

AWD

CWL

RAC

OEA

CLZ

CAC

OEZ

CPWD

OED

ASC

CLZ

OEA

CAC

OED

LCAS

RCD

CAS

CRP

I/OH

I/OL

DQ8 ~ DQ15

VALID

DATA-OUT

RAC

CLZ

CAC

VALID

DATA-IN

VALID

DATA-OUT

VALID

DATA-IN

CLZ

CAC

OEZ

OED

OEZ

VALID

DATA-OUT

VALID

DATA-IN

VALID

DATA-OUT

VALID

DATA-IN

HPRWC

RSH

RWL

RCS

RAH

CMOS DRAM

K4E661612C,K4E641612C

ASC

RAS

I/OH

I/OL

DQ0 ~ DQ7

ROW

ADDR

CSH

RASP

ASR

Don

t care

HYPER PAGE MODE LOWER BYTE READ - MODIFY - WRITE CYCLE

Undefined

RAD

CAH

COL.

ADDR

COL.

ADDR

ASC

CAH

RAL

RCS

CWL

CWD

AWD

RWD

CWD

AWD

CWL

RAC

OEA

CLZ

CAC

OEZ

CPWD

OED

CLZ

OEA

CAC

OED

RWL

RCD

CAS

CRP

I/OH

I/OL

DQ8 ~ DQ15

OEZ

VALID

DATA-OUT

VALID

DATA-IN

VALID

DATA-OUT

VALID

DATA-IN

RPC

RSH

OPEN

LCAS

UCAS

HPRWC

RCS

OLZ

RAH

CMOS DRAM

K4E661612C,K4E641612C

ASC

CRP

RAS

I/OH

I/OL

DQ0 ~ DQ7

ROW

ADDR

CSH

RASP

ASR

Don

t care

HYPER PAGE MODE UPPER BYTE READ - MODIFY - WRITE CYCLE

Undefined

RAD

CAH

COL.

ADDR

COL.

ADDR

CAH

RAL

RCS

CWL

CWD

AWD

RWD

CWD

AWD

CWL

RAC

OEA

CLZ

CAC

OEZ

CPWD

OED

CLZ

OEA

CAC

OED

RWL

RCD

CAS

CRP

I/OH

I/OL

DQ8 ~ DQ15

OEZ

VALID

DATA-OUT

VALID

DATA-IN

VALID

DATA-OUT

VALID

DATA-IN

RPC

RSH

OPEN

LCAS

UCAS

HPRWC

ASC

RCS

RAH

OLZ

CMOS DRAM

K4E661612C,K4E641612C

HYPER PAGE READ AND WRITE MIXED CYCLE

RAS

COLUMN

ADDRESS

ROW

ADDR

RASP

Don

t care

Undefined

I/OH

I/OL

DQ0 ~ DQ7

WEZ

HPC

RCD

RAH

ASC

CAH

ASC

CAH

RCH

RCS

RCH

ASC

COLUMN

ADDRESS

COL.

ADDR

VALID

DATA-OUT

REZ

WCS

VALID

DATA-OUT

VALID

DATA-OUT

VALID

DATA-IN

RAC

COL.

ADDR

CAS

ASR

CAS

ASC

RCH

WCH

WPE

CLZ

CPA

WED

WEZ

CAC

OEA

HPC

CAS

I/OH

I/OL

DQ8 ~ DQ15

WEZ

VALID

DATA-OUT

REZ

VALID

DATA-OUT

VALID

DATA-OUT

VALID

DATA-IN

RAC

WEZ

CAC

OEA

LCAS

UCAS

HPC

READ(

CAC

)

READ(

CPA

)

WRITE

READ(

)

RAD

RHCP

RAL

CMOS DRAM

K4E661612C,K4E641612C

CRP

OPEN

RAS

UCAS

ROW

ADDR

ASR

CRP

RAS - ONLY REFRESH CYCLE

LCAS

RAS

RAH

NOTE : W, OE , D

= Don

t care

OUT

= OPEN

RPC

CAS - BEFORE - RAS REFRESH CYCLE

NOTE : OE, A = Don

t care

RAS

UCAS

LCAS

RAS

RPC

CSR

CHR

CSR

CHR

CEZ

OPEN

DQ0 ~ DQ7

DQ8 ~ DQ15

WRP

WRH

Don

t care

Undefined

CMOS DRAM

K4E661612C,K4E641612C

OEZ

DATA-IN

DATA-OUT

RAS

UCAS

ROW

ADDRESS

RAS

CHR

RCD

RSH

RAD

ASR

RAH

ASC

CRP

Don

t care

HIDDEN REFRESH CYCLE ( READ )

Undefined

LCAS

DQ0 ~ DQ7

DQ8 ~ DQ15

RSH

RCD

CRP

WRH

COLUMN

ADDRESS

OEA

RAS

CHR

CAH

RCS

RAC

CLZ

CAC

DATA-OUT

CEZ

OPEN

REZ

WEZ

OLZ

* In Hidden refresh cycle of 64Mb A-die & B-die, when CAS signal transits from Low to High, the valid data may be cut off.

RAL

CMOS DRAM

K4E661612C,K4E641612C

OPEN

CAS - BEFORE - RAS SELF REFRESH CYCLE

NOTE : OE , A = Don

t care

RAS

UCAS

RPS

LCAS

RASS

RPC

CSR

CEZ

OPEN

DQ0 ~ DQ7

DQ8 ~ DQ15

WRP

WRH

CHS

CSR

CHS

TEST MODE IN CYCLE

NOTE : OE , A = Don

t care

RAS

UCAS

LCAS

RPC

CSR

OPEN

DQ0 ~ DQ15

CHR

CSR

CHR

Don

t care

Undefined

WTS

WTH

CEZ

RAS

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: K4E661612C-L45

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: K4E661612C-L45