DRAM MODULE
M366F040(8)4DT1-C
REV. 0.1 Oct. 2000
M366F040(8)4DT1-C EDO Mode without buffer
4M x 64 DRAM DIMM Using 4Mx16, 4K & 8K Refresh, 3.3V
The Samsung M366F040(8)4DT1-C is a 4Mx64bits Dynamic
RAM high density memory module. The Samsung
M366F040(8)4DT1-C consists of four CMOS 4Mx16bits
DRAMs in TSOP 400mil packages and one 2K EEPROM for
SPD in 8-pin TSSOP package mounted on a 168-pin glass-
epoxy substrate. A 0.1 or 0.22uF decoupling capacitor is
mounted on the printed circuit board for each DRAM. The
M366F040(8)4DT1-C is a Dual In-line Memory Module and is
intended for mounting into 168 pin edge connector sockets.
GENERAL DESCRIPTION
FEATURES
PERFORMANCE RANGE
Speed
t
RAC
t
CAC
t
RC
t
HPC
-C50
50ns
13ns
84ns
20ns
-C60
60ns
15ns
104ns
25ns
PIN CONFIGURATIONS
Note : A12 is used for only M366F0484DT1-C (8K ref.)
Pin
Front
Pin
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V
SS
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
CC
DQ14
DQ15
*CB0
*CB1
V
SS
NC
NC
V
CC
W0
CAS0
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
CAS1
RAS0
OE0
V
SS
A0
A2
A4
A6
A8
A10
A12
V
CC
V
CC
DU
V
SS
OE2
RAS2
CAS2
CAS3
W2
V
CC
NC
NC
*CB2
*CB3
V
SS
DQ16
DQ17
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
DQ18
DQ19
V
CC
DQ20
NC
DU
NC
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
CC
DQ28
DQ29
DQ30
DQ31
V
SS
NC
NC
NC
SDA
SCL
V
CC
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
V
SS
DQ32
DQ33
DQ34
DQ35
V
CC
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
CC
DQ46
DQ47
*CB4
*CB5
V
SS
NC
NC
V
CC
DU
CAS4
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
CAS5
*RAS1
DU
V
SS
A1
A3
A5
A7
A9
A11
*A13
V
CC
DU
DU
V
SS
DU
*RAS3
CAS6
CAS7
DU
V
CC
NC
NC
*CB6
*CB7
V
SS
DQ48
DQ49
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
DQ50
DQ51
V
CC
DQ52
NC
DU
NC
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
CC
DQ60
DQ61
DQ62
DQ63
V
SS
NC
NC
SA0
SA1
SA2
V
CC
PIN NAMES
* These pins are not used in this module.
Pin Name
Function
A0 - A11
Address Input (4K ref.)
A0 - A12
Address Input (8K ref.)
DQ0 - DQ63
Data In/Out
W0, W2
Read/Write Enable
OE0, OE2
Output Enable
RAS0, RAS2
Row Address Strobe
CAS0 - CAS7
Column Address Strobe
V
CC
Power(+3.3V)
V
SS
Ground
NC
No Connection
DU
Don
t use
SDA
Serial Address /Data I/O
SCL
Serial Clock
SA0 -SA2
Address in EEPROM
*CB0 - CB7
Check Bit
Part Identification
New JEDEC standard proposal without buffer
Serial Presence Detect with EEPROM
Extended Data Out Mode Operation
CAS-before-RAS Refresh capability
RAS-only and Hidden refresh capability
LVTTL compatible inputs and outputs
Single +3.3V
0.3V power supply
PCB : Height(1000mil), single sided component
Part number
PKG
Ref.
CBR Ref.
ROR Ref.
M366F0404DT1-C
TSOP
4K
4K/64ms
M366F0484DT1-C
TSOP
8K
4K/64ms
8K/64ms
DRAM MODULE
M366F040(8)4DT1-C
REV. 0.1 Oct. 2000
FUNCTIONAL BLOCK DIAGRAM
V
CC
Vss
0.1 or 0.22uF Capacitor
under each DRAM
To all DRAMs
RAS0
W0
OE0
A0-A11(A12)
CAS1
LCAS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
UCAS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
U0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
Serial PD
SDA
SCL
A1
A2
A0
SA1 SA2
SA0
CAS2
CAS3
U1
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
CAS4
CAS5
U2
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
CAS6
CAS7
U3
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
RAS2
W2
OE2
CAS0
LCAS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
UCAS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LCAS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
UCAS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LCAS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
UCAS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
Note : A12 is used for only M366F0484DT1 (8K ref.)
DRAM MODULE
M366F040(8)4DT1-C
REV. 0.1 Oct. 2000
I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
and I
CC3
, address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one EDO mode cycle time,
t
HPC
.
* NOTE :
ABSOLUTE MAXIMUM RATINGS *
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.
Item
Symbol
Rating
Unit
Voltage on any pin relative V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Output Current
V
IN
, V
OUT
V
CC
T
stg
P
D
I
OS
-0.5 to +4.6
-0.5 to +4.6
-55 to +150
4
50
V
V
C
W
mA
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to V
SS
, T
A
= 0 to 70
C)
*1 : V
CC
+1.3V at pulse width
15ns which is measured at V
CC
.
*2 : -1.3V at pulse width
15ns which is measured at V
SS
.
Item
Symbol
Min
Typ
Max
Unit
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
V
CC
V
SS
V
IH
V
IL
3.0
0
2.0
*2
-0.3
3.3
0
-
-
3.6
0
V
CC
+0.3
*1
0.8
V
V
V
V
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
I
CC1
I
CC2
I
CC3
I
CC4
I
CC5
I
CC6
I(
IL)
I(
OL)
V
OH
V
OL
Symbol
Speed
M366F0484DT1
M366F0404DT1
Unit
Min
Max
Min
Max
I
CC1
-50
-60
-
-
320
280
-
-
480
440
mA
mA
I
CC2
Don
t care
-
4
-
4
mA
I
CC3
-50
-60
-
-
320
280
-
-
480
440
mA
mA
I
CC4
-50
-60
-
-
360
320
-
-
360
320
mA
mA
I
CC5
Don
t care
-
2
-
2
mA
I
CC6
-50
-60
-
-
480
440
-
-
480
440
mA
mA
I
I(L)
I
O(L)
Don
t care
-10
-5
10
5
-10
-5
10
5
uA
uA
V
OH
V
OL
Don
t care
2.4
-
-
0.4
2.4
-
-
0.4
V
V
: Operating Current * (RAS, CAS, Address cycling @
t
RC
=min)
: Standby Current (RAS=CAS=W=V
IH
)
: RAS Only Refresh Current * (CAS=V
IH
, RAS cycling @
t
RC
=min)
: Extended Data Out Mode Current * (RAS=V
IL
, CAS cycling :
t
HPC
=min)
: Standby Current (RAS=CAS=W=V
CC
-0.2V)
: CAS-Before-RAS Refresh Current * (RAS and CAS cycling @
t
RC
=min)
: Input Leakage Current (Any input 0
V
IN
V
CC
+0.3V, all other pins not under test=0 V)
: Output Leakage Current(Data Out is disabled, 0V
V
OUT
V
CC
)
: Output High Voltage Level (I
OH
= -2mA)
: Output Low Voltage Level (I
OL
= 2mA)
DRAM MODULE
M366F040(8)4DT1-C
REV. 0.1 Oct. 2000
AC CHARACTERISTICS
(0
C
T
A
70
C, V
CC
=3.3V
0.3V. See notes 1,2.)
CAPACITANCE
(T
A
= 25
C, V
CC
=3.3V, f = 1MHz)
Item
Symbol
Min
Max
Unit
Input capacitance[A0-A12]
Input capacitance[W0, W2, OE0, OE2]
Input capacitance[RAS0, RAS2]
Input capacitance[CAS0 - CAS7]
Input/Output capacitance[DQ0-DQ63]
C
IN1
C
IN2
C
IN3
C
IN4
CDQ
-
-
-
-
-
30
24
24
17
17
pF
pF
pF
pF
pF
Test condition : V
ih
/V
il
=2.2/0.7V, V
oh
/V
ol
=2.0/0.8V, output loading C
L
=100pF
Parameter
Symbol
-50
-60
Unit
Note
Min
Max
Min
Max
Random read or write cycle time
t
RC
84
104
ns
Read-modify-write cycle time
t
RWC
128
153
ns
Access time from RAS
t
RAC
50
60
ns
3,4,9
Access time from CAS
t
CAC
13
15
ns
3,4,5
Access time from column address
t
AA
25
30
ns
3,9
CAS to output in Low-Z
t
CLZ
3
3
ns
3
OE to output in Low-Z
t
OLZ
3
3
ns
3
Output buffer turn-off delay from CAS
t
CEZ
3
13
3
13
ns
6,12
Transition time(rise and fall)
t
T
1
50
1
50
ns
2
RAS precharge time
t
RP
30
40
ns
RAS pulse width
t
RAS
50
10K
60
10K
ns
RAS hold time
t
RSH
8
10
ns
CAS hold time
t
CSH
38
40
ns
CAS pulse width
t
CAS
8
10K
10
10K
ns
RAS to CAS delay time
t
RCD
17
37
20
45
ns
4
RAS to column address delay time
t
RAD
12
25
15
30
ns
9
CAS to RAS precharge time
t
CRP
5
5
ns
Row address set-up time
t
ASR
0
0
ns
Row address hold time
t
RAH
7
10
ns
Column address set-up time
t
ASC
0
0
ns
13
Column address hold time
t
CAH
7
10
ns
13
Column address to RAS lead time
t
RAL
25
30
ns
Read command set-up time
t
RCS
0
0
ns
Read command hold referenced to CAS
t
RCH
0
0
ns
8
Read command hold referenced to RAS
t
RRH
0
0
ns
8
Write command hold time
t
WCH
7
10
ns
Write command pulse width
t
WP
7
10
ns
Write command to RAS lead time
t
RWL
8
10
ns
Write command to CAS lead time
t
CWL
7
10
ns
16
Data set-up time
t
DS
0
0
ns
Data hold time
t
DH
7
10
ns
Refresh period (4K & 8K Ref.)
t
REF
64
64
ms
Write command set-up time
t
WCS
0
0
ns
7
CAS to W dealy time
t
CWD
33
38
ns
7, 15
RAS to W dealy time
t
RWD
70
84
ns
7
DRAM MODULE
M366F040(8)4DT1-C
REV. 0.1 Oct. 2000
AC CHARACTERISTICS
(0
C
T
A
70
C, V
CC
=3.3V
0.3V. See notes 1,2.)
Test condition : V
ih
/V
il
=2.2/0.7V, V
oh
/V
ol
=2.0/0.8V, output loading C
L
=100pF
Parameter
Symbol
-50
-60
Unit
Note
Min
Max
Min
Max
Column address to W delay time
t
AWD
45
53
ns
7
CAS precharge to W delay time
t
CPWD
47
58
ns
CAS setup time (CAS-before-RAS refresh)
t
CSR
5
5
ns
17
CAS hold time (CAS-before-RAS refresh)
t
CHR
10
10
ns
RAS to CAS precharge time
t
RPC
5
5
ns
Access time from CAS precharge
t
CPA
28
35
ns
3
Hyper page mode cycle time
t
HPC
20
25
ns
10
Hyper page mode read-modify write cycle time
t
HPRWC
67
73
ns
10
CAS precharge time (Hyper page cycle)
t
CP
7
10
ns
14
RAS pulse width (Hyper page cycle)
t
RASP
50
200K
60
200K
ns
RAS hold time from CAS precharge
t
RHCP
30
35
ns
OE access time
t
OEA
13
15
ns
OE to data delay
t
OED
10
13
ns
Output buffer turn off delay time from OE
t
OEZ
3
13
3
13
ns
6
OE command hold time
t
OEH
5
5
ns
Output data hold time
t
DOH
5
5
ns
Output buffer turn off delay from RAS
t
REZ
3
13
3
13
ns
6,12
Output buffer turn off delay from W
t
WEZ
3
13
3
13
ns
6
W to data delay
t
WED
15
15
ns
OE to CAS hold time
t
OCH
5
5
ns
CAS hold time to OE
t
CHO
5
5
ns
OE precharge time
t
OEP
5
5
ns
W pulse width (Hyper page cycle)
t
WPE
5
5
ns
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