K4F171611D, K4F151611D

CMOS DRAM

K4F171612D, K4F151612D

This is a family of 1,048,576 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory
cells within the same row. Power supply voltage (+5.0V or +3.3V), refresh cycle (1K Ref. or 4K Ref.), access time (-50 or -60), power
consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-
before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This
1Mx16 Fast Page Mode DRAM family is fabricated using Samsung

s advanced CMOS process to realize high band-width, low power

consumption and high reliability. It may be used as graphic memory unit for microcomputer, personal computer and portable machines.

Part Identification

- K4F171611D-J(T) (5V, 4K Ref.)

- K4F151611D-J(T) (5V, 1K Ref.)

- K4F171612D-J(T) (3.3V, 4K Ref.)

- K4F151612D-J(T) (3.3V, 1K Ref.)

· Fast Page Mode operation
· 2 CAS Byte/Word Read/Write operation
· CAS-before-RAS refresh capability
· RAS-only and Hidden refresh capability
· Self-refresh capability (L-ver only)
· TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
· Early Write or output enable controlled write
· JEDEC Standard pinout
· Available in 42-pin SOJ 400mil and 50(44)-pin TSOP(II)
400mil packages

· Single +5V

10% power supply (5V product)

· Single +3.3V

0.3V power supply (3.3V product)

Control

Clocks

VBB Generator

Refresh Timer

Refresh Control

Refresh Counter

Row Address Buffer

Col. Address Buffer

Row Decoder

Column Decoder

Lower

Data out

Buffer

RAS

UCAS

LCAS

Vcc

Vss

DQ0

DQ7

A0-A11

(A0 - A9)

A0 - A7

(A0 - A9)

Memory Array

1,048,576 x16

Cells

SAMSUNG ELECTRONICS CO., LTD.

reserves the right to

change products and specifications without notice.

1M x 16Bit CMOS Dynamic RAM with Fast Page Mode

DESCRIPTION

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Refresh Cycles

Part
NO.

Refresh

cycle

Refresh period

Normal

L-ver

K4F171611D

64ms

128ms

K4F171612D

3.3V

K4F151611D

16ms

K4F151612D

3.3V

Perfomance Range
Speed

RAC

CAC

Remark

-50

50ns

15ns

90ns

35ns

5V/3.3V

-60

60ns

15ns

110ns

40ns

5V/3.3V

Active Power Dissipation

Speed

3.3V

-50

324

504

495

770

-60

288

468

440

715

Unit : mW

e
n
s
e

A

p
s

&

I
/
O

Upper

Data in

Buffer

Upper

Data out

Buffer

Lower

Data in

Buffer

DQ8

DQ15

Note)

: 1K Refresh

K4F171611D, K4F151611D

CMOS DRAM

K4F171612D, K4F151612D

C C

DQ0

DQ1

DQ2

DQ3

C C

DQ4

DQ5

DQ6

DQ7

N.C

RAS

*A11(N.C)

*A10(N.C)

C C

DQ15

DQ14

DQ13

DQ12

DQ11

DQ10

DQ9

DQ8

N.C

LCAS

UCAS

PIN CONFIGURATION

(Top Views)

Pin Name

Pin Function

A0 - A11

Address Inputs (4K Product)

A0 - A9

Address Inputs (1K Product)

DQ0 - 15

Data In/Out

Ground

RAS

Row Address Strobe

UCAS

Upper Column Address Strobe

LCAS

Lower Column Address Strobe

Read/Write Input

Data Output Enable

C C

Power(+5V)

Power(+3.3V)

N.C

No Connection

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

N.C

RAS

*A11(N.C)

*A10(N.C)

DQ15

DQ14

DQ13

DQ12

DQ11

DQ10

DQ9

DQ8

N.C

LCAS

UCAS

*A10 and A11 are N.C for K4F151611(2)D(5V/3.3V, 1K Ref. product)

J : 400mil 42 SOJ

T : 400mil 50(44) TSOP II

· K4F17(5)1611(2)D-J

· K4F17(5)1611(2)D-T

K4F171611D, K4F151611D

CMOS DRAM

K4F171612D, K4F151612D

ABSOLUTE MAXIMUM RATINGS

* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted

to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Parameter

Symbol

Rating

Units

3.3V

Voltage on any pin relative to V

IN,

O U T

-0.5 to +4.6

-1.0 to +7.0

Voltage on V

supply relative to V

-0.5 to +4.6

-1.0 to +7.0

Storage Temperature

Tstg

-55 to +150

Power Dissipation

Short Circuit Output Current

Address

RECOMMENDED OPERATING CONDITIONS

(Voltage referenced to Vss, T

= 0 to 70

*1 : V

C C

+1.3V/15ns(3.3V), V

+2.0V/20ns(5V), Pulse width is measured at V

C C

*2 : -1.3V/15ns(3.3V), -2.0V/20ns(5V), Pulse width is measured at V

Parameter

Symbol

3.3V

Units

Min

Typ

Max

Min

Typ

Max

Supply Voltage

C C

3.0

3.3

3.6

4.5

5.0

5.5

Ground

Input High Voltage

2.0

+0.3

2.4

+1.0

Input Low Voltage

-0.3

0.8

-1.0

0.8

DC AND OPERATING CHARACTERISTICS

(Recommended operating conditions unless otherwise noted.)

Max

Parameter

Symbol

Min

Max

Units

3.3V

Input Leakage Current (Any input 0

+0.3V,

all other input pins not under test=0 Volt)

I(L)

-5

Output Leakage Current

(Data out is disabled, 0V

OUT

)

O(L)

-5

Output High Voltage Level(I

=-2mA)

2.4

Output Low Voltage Level(I

=2mA)

0.4

Input Leakage Current (Any input 0

+0.5V,

all other input pins not under test=0 Volt)

I(L)

-5

Output Leakage Current

(Data out is disabled, 0V

OUT

)

O(L)

-5

Output High Voltage Level(I

=-5mA)

2.4

Output Low Voltage Level(I

=4.2mA)

0.4

K4F171611D, K4F151611D

CMOS DRAM

K4F171612D, K4F151612D

*Note :

CC1

, I

CC3

, I

CC4

and I

CC6

are dependent on output loading and cycle rates. Specified values are obtained with the output open.

is specified as an average current. In I

CC1

, I

CC3

and I

CC6,

address can be changed maximum once while RAS=V

. In I

CC4

address can be changed maximum once within one fast page mode cycle time, t

DC AND OPERATING CHARACTERISTICS

(Continued)

CC1

* : Operating Current (RAS and UCAS, LCAS cycling @t

=min.)

CC2

: Standby Current (RAS=UCAS=LCAS=W=V

)

CC3

* : RAS-only Refresh Current (UCAS=LCAS=V

, RAS cycling @t

R C

=min.)

CC4

* : Fast Page Mode Current (RAS=V

, UCAS or LCAS, Address cycling @t

=min.)

CC5

: Standby Current (RAS=UCAS=LCAS=W=V

-0.2V)

CC6

* : CAS-Before-RAS Refresh Current (RAS, UCAS or LCAS cycling @t

=min.)

CC7

: Battery back-up current, Average power supply current, Battery back-up mode

Input high voltage(V

)=V

C C

-0.2V, Input low voltage(V

)=0.2V, UCAS, LCAS=0.2V,

DQ=Don

t care, T

R C

=31.25us(4K/L-ver), 125us(1K/L-ver),

RAS

min~300ns

C C S

: Self Refresh Current

RAS=UCAS=LCAS=V

, W=OE=A0 ~ A11=V

C C

-0.2V or 0.2V,

DQ0 ~ DQ15=V

-0.2V, 0.2V or Open

Symbol

Power

Speed

Max

Units

K4F171612D

K4F151612D

K4F171611D

K4F151611D

CC1

Don

t care

-50

-60

140

130

140

130

CC2

Normal

Don

t care

CC3

Don

t care

-50

-60

140

130

140

130

CC4

Don

t care

-50

-60

CC5

Normal

Don

t care

0.5

200

0.5

200

CC6

Don

t care

-50

-60

140

130

140

130

CC7

Don

t care

300

200

350

250

CCS

Don

t care

150

200

K4F171611D, K4F151611D

CMOS DRAM

K4F171612D, K4F151612D

CAPACITANCE

=25

C, V

=5V or 3.3V, f=1MHz)

Parameter

Symbol

Min

Max

Units

Input capacitance [A0 ~ A11]

IN1

Input capacitance [RAS, UCAS, LCAS, W, OE]

IN2

Output capacitance [DQ0 - DQ15]

Test condition (5V device) : V

C C

=5.0V

10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V

Parameter

Symbol

-50

-60

Units

Notes

Min

Max

Min

Max

Random read or write cycle time

R C

110

Read-modify-write cycle time

RWC

133

155

Access time from RAS

RAC

3,4,10

Access time from CAS

CAC

3,4,5

Access time from column address

3,10

CAS to output in Low-Z

CLZ

Output buffer turn-off delay

OFF

Transition time (rise and fall)

RAS precharge time

R P

RAS pulse width

RAS

10K

RAS hold time

RSH

CAS hold time

CSH

CAS pulse width

CAS

10K

RAS to CAS delay time

RCD

RAS to column address delay time

RAD

CAS to RAS precharge time

CRP

Row address set-up time

ASR

Row address hold time

RAH

Column address set-up time

ASC

Column address hold time

CAH

Column address to RAS lead time

RAL

Read command set-up time

RCS

Read command hold time referenced to CAS

RCH

Read command hold time referenced to RAS

RRH

Write command hold time

WCH

Write command pulse width

W P

Write command to RAS lead time

RWL

Write command to CAS lead time

CWL

AC CHARACTERISTICS

C, See note 1,2)

Test condition (3.3V device) : V

=3.3V

0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V

K4F171611D, K4F151611D

CMOS DRAM

K4F171612D, K4F151612D

AC CHARACTERISTICS

(Continued)

Parameter

Symbol

-50

-60

Units

Notes

Min

Max

Min

Max

Data set-up time

D S

9,17

Data hold time

D H

9,17

Refresh period (1K, Normal)

REF

Refresh period (4K, Normal)

REF

Refresh period (L-ver)

REF

128

Write command set-up time

WCS

CAS to W delay time

CWD

7,13

RAS to W delay time

RWD

Column address to W delay time

AWD

CAS precharge to W delay time

CPWD

CAS set-up time (CAS-before-RAS refresh)

CSR

CAS hold time (CAS-before-RAS refresh)

CHR

RAS to CAS precharge time

RPC

Access time from CAS precharge

CPA

Fast Page mode cycle time

Fast Page read-modify-write cycle time

PRWC

CAS precharge time (Fast Page cycle)

C P

RAS pulse width (Fast Page cycle)

RASP

200K

RAS hold time from CAS precharge

RHCP

OE access time

OEA

OE to data delay

OED

Output buffer turn off delay time from OE

OEZ

OE command hold time

OEH

RAS pulse width (C-B-R self refresh)

RASS

100

18,19,20

RAS precharge time (C-B-R self refresh)

RPS

110

18,19,20

CAS hold time (C-B-R self refresh)

CHS

-50

18,19,20

K4F171611D, K4F151611D

CMOS DRAM

K4F171612D, K4F151612D

NOTES

An initial pause of 200us is required after power-up followed by any 8 RAS -only refresh or CAS-before-RAS refresh cycles
before proper device operation is achieved.
Input voltage levels are Vih/Vil. V

(min) and V

(max) are reference levels for measuring timing of input signals.

Transition times are measured between V

(min) and V

(max) and are assumed to be 5ns for all inputs.

Measured with a load equivalent to 2 TTL(5V)/1TTL(3.3V) loads and 100pF.
Operation within the

RCD

(max) limit insures that

RAC

(max) can be met.

RCD

(max) is specified as a reference point only.

RCD

is greater than the specified

RCD

(max) limit, then access time is controlled exclusively by

CAC

Assumes that t

RCD

(max).

This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V

or V

W C S

RWD

CWD

AWD

and

CPWD

are non restrictive operating parameters. They are included in the data sheet as electrical

characteristics only. If

W C S

WCS

(min), the cycle is an early write cycle and the data output will remain high impedance for the

duration of the cycle. If

CWD

(min),

RWD

(min),

AWD

(min) and

CPWD

(min), then the cycle is a read-

modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions
is satisfied, the condition of the data out is indeterminate.
Either

RCH

RRH

must be satisfied for a read cycle.

These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in OE controlled write cycle
and read-modify-write cycles.
Operation within the

RAD

(max) limit insures that

RAC

(max) can be met.

RAD

(max) is specified as a reference point only.

RAD

is greater than the specified

RAD

(max) limit, then access time is controlled by

ASC

, t

CAH

are referenced to the earlier CAS falling edge.

C P

is specified from the later CAS rising edge in the previous cycle to the earlier CAS falling edge in the next cycle.

K4F17(5)1611(2)D Truth Table

RAS

LCAS

UCAS

DQ0 - DQ7

DQ8-DQ15

STATE

Hi-Z

Standby

Hi-Z

Refresh

DQ-OUT

Hi-Z

Byte Read

Hi-Z

DQ-OUT

Byte Read

DQ-OUT

Word Read

DQ-IN

Byte Write

DQ-IN

Byte Write

DQ-IN

Word Write

Hi-Z

10.

11.
12.

K4F171611D, K4F151611D

CMOS DRAM

K4F171612D, K4F151612D

CWD

is referenced to the later CAS falling edge at word read-modify-write cycle.

CWL

is specified from W falling edge to the earlier CAS rising edge

CSR

is referenced to the earlier CAS falling edge before RAS transition low.

CHR

is referenced to the later CAS rising edge after RAS transition low.

CSR

CHR

RAS

LCAS

UCAS

16.

15.

14.

13.

DS,

is independently specified for lower byte DQ(0-7), upper byte DQ(8-15)

RASS

100us, then RAS precharge time must use

RPS

instead of

For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K)/1024(1K) cycles of burst refresh must be executed
within 64ms/16ms before and after self refresh, in order to meet refresh specification.
For distributed CAS-before-RAS with 15.6us interval CAS-before-RAS refresh should be executed with in 15.6us immediately
before and after self refresh in order to meet refresh specification.

17.
18.
19.

20.

K4F171611D, K4F151611D

CMOS DRAM

K4F171612D, K4F151612D

RAS

UCAS

DQ0 ~ DQ7

COLUMN

ADDRESS

ROW

ADDRESS

RAS

CRP

R P

CSH

RSH

RCD

CAS

RAL

ASR

RAH

ASC

CAH

CRP

OEA

CAC

CLZ

RAC

OPEN

OFF

RCH

Don

t care

Undefined

LCAS

CRP

CSH

RSH

RCD

CAS

RAD

C R P

RRH

DQ8 ~ DQ15

CAC

CLZ

RAC

OPEN

DATA-OUT

OFF

OEZ

RCS

WORD READ CYCLE

K4F171611D, K4F151611D

CMOS DRAM

K4F171612D, K4F151612D

CRP

NOTE : D

= OPEN

LOWER BYTE READ CYCLE

RAS

LCAS

DQ0 ~ DQ7

COLUMN

ADDRESS

ROW

ADDRESS

RAS

R C

CSH

RSH

RCD

CAS

RAL

RAD

ASR

RAH

ASC

CAH

CRP

OEA

CAC

CLZ

RAC

OPEN

DATA-OUT

OEZ

OFF

RCH

Don

t care

Undefined

RPC

UCAS

OPEN

DQ8 ~ DQ15

R C S

RRH

K4F171611D, K4F151611D

CMOS DRAM

K4F171612D, K4F151612D

NOTE : D

= OPEN

UPPER BYTE READ CYCLE

RAS

LCAS

DQ0 ~ DQ7

COLUMN

ADDRESS

ROW

ADDRESS

RAS

CRP

CSH

RSH

RCD

CAS

RAL

RAD

ASR

RAH

ASC

CAH

CRP

OEA

CAC

CLZ

RAC

OPEN

DATA-OUT

OEZ

OFF

RRH

RCH

Don

t care

Undefined

UCAS

OPEN

DQ8 ~ DQ15

CRP

RPC

R C S

K4F171611D, K4F151611D

CMOS DRAM

K4F171612D, K4F151612D

RAS

UCAS

COLUMN

ADDRESS

ROW

ADDRESS

RAS

R C

C R P

CSH

RSH

RCD

CAS

RAL

RAD

ASR

RAH

ASC

CAH

C R P

Don

t care

WORD WRITE CYCLE ( EARLY WRITE )

NOTE : D

OUT

= OPEN

Undefined

LCAS

WCS

DQ0 ~ DQ7

DQ8 ~ DQ15

CRP

CSH

RSH

RCD

CAS

C R P

WCH

W P

D H

DATA-IN

D H

DATA-IN

K4F171611D, K4F151611D

CMOS DRAM

K4F171612D, K4F151612D

CRP

RAS

UCAS

COLUMN

ADDRESS

ROW

ADDRESS

RAS

R C

RAL

RAD

ASR

RAH

ASC

CAH

Don

t care

LOWER BYTE WRITE CYCLE ( EARLY WRITE )

NOTE : D

OUT

= OPEN

Undefined

LCAS

WCS

DQ0 ~ DQ7

DQ8 ~ DQ15

CRP

CSH

RSH

RCD

CAS

WCH

W P

D H

DATA-IN

CRP

RPC

K4F171611D, K4F151611D

CMOS DRAM

K4F171612D, K4F151612D

RAS

UCAS

COLUMN

ADDRESS

ROW

ADDRESS

RAS

C R P

R P

CSH

RSH

RCD

CAS

RAL

RAD

ASR

RAH

ASC

CAH

C R P

Don

t care

UPPER BYTE WRITE CYCLE ( EARLY WRITE )

NOTE : D

OUT

= OPEN

Undefined

LCAS

WCS

DQ0 ~ DQ7

DQ8 ~ DQ15

WCH

D H

DATA-IN

C R P

RPC

K4F171611D, K4F151611D

CMOS DRAM

K4F171612D, K4F151612D

RAS

UCAS

ROW

ADDRESS

RAS

R C

C R P

CSH

RSH

RCD

CAS

RAL

RAD

ASR

RAH

ASC

C R P

Don

t care

WORD WRITE CYCLE ( OE CONTROLLED WRITE )

NOTE : D

OUT

= OPEN

Undefined

LCAS

DQ0 ~ DQ7

DQ8 ~ DQ15

CRP

RSH

RCD

CAS

C R P

R W L

C W L

DATA-IN

COLUMN

ADDRESS

OEH

OED

DATA-IN

CSH

CAH

K4F171611D, K4F151611D

CMOS DRAM

K4F171612D, K4F151612D

RAS

UCAS

COLUMN

ADDRESS

ROW

ADDRESS

RAS

R C

R P

RAL

RAD

ASR

RAH

ASC

CAH

Don

t care

LOWER BYTE WRITE CYCLE ( OE CONTROLLED WRITE )

NOTE : D

OUT

= OPEN

Undefined

LCAS

R W L

DQ0 ~ DQ7

DQ8 ~ DQ15

C R P

CSH

RSH

RCD

CAS

C R P

C W L

DATA-IN

CRP

RPC

OEH

OED

K4F171611D, K4F151611D

CMOS DRAM

K4F171612D, K4F151612D

RAS

UCAS

COLUMN

ADDRESS

ROW

ADDRESS

RAS

C R P

CSH

RSH

RCD

CAS

RAL

RAD

ASR

RAH

ASC

CAH

CRP

Don

t care

UPPER BYTE WRITE CYCLE ( OE CONTROLLED WRITE )

NOTE : D

OUT

= OPEN

Undefined

LCAS

CRP

RWL

C W L

DATA-IN

OEH

OED

DQ0 ~ DQ7

DQ8 ~ DQ15

RPC

K4F171611D, K4F151611D

CMOS DRAM

K4F171612D, K4F151612D

RWL

RAS

UCAS

COLUMN

ADDRESS

ROW

ADDR

RAS

RWC

R P

RSH

RCD

CAS

CSH

RAD

ASR

RAH

ASC

CAH

CRP

Don

t care

WORD READ - MODIFY - WRITE CYCLE

Undefined

LCAS

I/OH

I/OL

DQ0 ~ DQ7

I/OH

I/OL

DQ8 ~ DQ15

CWL

RSH

RCD

CAS

CRP

AWD

CWD

OEA

RWD

OED

OEZ

RAC

OEZ

RAC

OED

VALID

DATA-OUT

VALID

DATA-IN

VALID

DATA-OUT

VALID

DATA-IN

CAC

CLZ

CAC

CLZ

K4F171611D, K4F151611D

CMOS DRAM

K4F171612D, K4F151612D

RWL

RAS

UCAS

COLUMN

ADDRESS

ROW

ADDR

RAS

RWC

R P

CSH

RAD

ASR

RAH

ASC

CAH

CRP

Don

t care

LOWER-BYTE READ - MODIFY - WRITE CYCLE

Undefined

LCAS

I/OH

I/OL

DQ0 ~ DQ7

I/OH

I/OL

DQ8 ~ DQ15

CWL

D S

D H

RSH

RCD

CAS

C R P

AWD

CWD

OEA

RWD

OED

OEZ

RAC

VALID

DATA-OUT

VALID

DATA-IN

RPC

CAC

CLZ

OPEN

K4F171611D, K4F151611D

CMOS DRAM

K4F171612D, K4F151612D

CRP

RWL

RAS

UCAS

COLUMN

ADDRESS

ROW

ADDR

RAS

RWC

R P

RSH

RCD

CAS

CSH

RAD

ASR

RAH

ASC

CAH

CRP

Don

t care

UPPER-BYTE READ - MODIFY - WRITE CYCLE

Undefined

LCAS

I/OH

I/OL

DQ0 ~ DQ7

I/OH

I/OL

DQ8 ~ DQ15

CWL

AWD

CWD

OEA

RWD

OEZ

RAC

OED

D H

VALID

DATA-OUT

VALID

DATA-IN

RPC

CAC

CLZ

OPEN

K4F171611D, K4F151611D

CMOS DRAM

K4F171612D, K4F151612D

RAS

UCAS

COLUMN

ADDRESS

ROW

ADDR

RASP

RCD

ASR

CRP

Don

t care

FAST PAGE MODE WORD READ CYCLE

Undefined

LCAS

DQ0 ~ DQ7

DQ8 ~ DQ15

OEZ

OFF

COLUMN

ADDRESS

CAS

C P

RPC

RHCP

CSH

RCD

C R P

CAS

C P

RPC

RAD

RAH

ASC

CAH

ASC

CAH

RCS

R C S

OEA

RCS

RCH

R C S

RCH

RRH

ASC

COLUMN

ADDRESS

COLUMN

ADDR

VALID

DATA-OUT

OEZ

OFF

OEA

CPA

CAC

OEA

CPA

CAC

OEA

CPA

CAC

VALID

DATA-OUT

VALID

DATA-OUT

VALID

DATA-OUT

OEZ

OFF

OEZ

OFF

OEZ

OFF

VALID

DATA-OUT

OEZ

OFF

VALID

DATA-OUT

VALID

DATA-OUT

VALID

DATA-OUT

OEZ

OFF

OEZ

OFF

CLZ

RAC

CAC

CLZ

RAC

¡ó

ASC

C P

RAL

K4F171611D, K4F151611D

CMOS DRAM

K4F171612D, K4F151612D

C R P

CRP

RAS

UCAS

COLUMN

ADDRESS

ROW

ADDR

RASP

R P

RCD

ASR

Don

t care

FAST PAGE MODE LOWER BYTE READ CYCLE

Undefined

LCAS

DQ0 ~ DQ7

DQ8 ~ DQ15

OEZ

OFF

COLUMN

ADDRESS

CAS

RPC

RHCP

CSH

RAD

RAH

ASC

CAH

ASC

CAH

ASC

CAH

R C S

RCS

OEA

R C S

RCH

RCS

RCH

RRH

ASC

COLUMN

ADDRESS

COLUMN

ADDR

VALID

DATA-OUT

OEZ

OFF

OEA

CPA

CAC

OEA

CPA

CAC

OEA

CPA

CAC

VALID

DATA-OUT

VALID

DATA-OUT

VALID

DATA-OUT

OEZ

OFF

OEZ

OFF

CLZ

RAC

CAC

¡ó

RPC

OPEN

RAL

C P

K4F171611D, K4F151611D

CMOS DRAM

K4F171612D, K4F151612D

RAS

UCAS

COLUMN

ADDRESS

ROW

ADDR

RASP

R P

RCD

ASR

C R P

Don

t care

FAST PAGE MODE UPPER BYTE READ CYCLE

Undefined

LCAS

DQ0 ~ DQ7

DQ8 ~ DQ15

COLUMN

ADDRESS

CAS

C P

RPC

RHCP

CSH

CRP

RPC

RAD

RAH

ASC

CAH

ASC

CAH

R C S

OEA

RCS

RCH

R C S

RCH

RRH

ASC

COLUMN

ADDRESS

COLUMN

ADDR

OEA

CPA

OEA

CPA

OEA

CPA

OEZ

OFF

VALID

DATA-OUT

OEZ

OFF

VALID

DATA-OUT

VALID

DATA-OUT

VALID

DATA-OUT

OEZ

OFF

OEZ

OFF

CAC

CLZ

RAC

OPEN

¡ó

CAC

RAL

ASC

K4F171611D, K4F151611D

CMOS DRAM

K4F171612D, K4F151612D

ASC

RAS

UCAS

COLUMN

ADDRESS

ROW

ADDR

RASP

RCD

ASR

CRP

Don

t care

FAST PAGE MODE WORD WRITE CYCLE ( EARLY WRITE )

Undefined

LCAS

DQ0 ~ DQ7

DQ8 ~ DQ15

C R P

RHCP

RAD

RAH

CAH

ASC

VALID

DATA-IN

¡ó

COLUMN

ADDRESS

COLUMN

ADDRESS

CAS

C P

CAS

RSH

¡ó

RCD

C R P

CAS

C P

CAS

C P

CAS

RSH

¡ó

CSH

ASC

¡ó

WCS

WCH

W P

W C S

WCH

W C S

WCH

¡ó

VALID

DATA-IN

VALID

DATA-IN

¡ó

D S

VALID

DATA-IN

VALID

DATA-IN

VALID

DATA-IN

¡ó

D S

NOTE : D

OUT

= OPEN

RAL

K4F171611D, K4F151611D

CMOS DRAM

K4F171612D, K4F151612D

RAS

UCAS

COLUMN

ADDRESS

ROW

ADDR

RASP

ASR

CRP

Don

t care

FAST PAGE MODE LOWER BYTE WRITE CYCLE ( EARLY WRITE )

Undefined

LCAS

DQ0 ~ DQ7

DQ8 ~ DQ15

RPC

RHCP

RAD

RAH

CAH

ASC

CAH

ASC

VALID

DATA-IN

¡ó

COLUMN

ADDRESS

COLUMN

ADDRESS

RCD

CRP

CAS

RSH

¡ó

CSH

ASC

¡ó

WCS

WCH

WCS

WCH

W P

WCS

WCH

¡ó

VALID

DATA-IN

VALID

DATA-IN

¡ó

D H

NOTE : D

OUT

= OPEN

¡ó

RAL

K4F171611D, K4F151611D

CMOS DRAM

K4F171612D, K4F151612D

RAS

UCAS

COLUMN

ADDRESS

ROW

ADDR.

RASP

ASR

CRP

Don

t care

FAST PAGE MODE UPPER BYTE WRITE CYCLE ( EARLY WRITE )

Undefined

LCAS

DQ0 ~ DQ7

DQ8 ~ DQ15

RPC

RHCP

RAD

RAH

CAH

ASC

CAH

ASC

VALID

DATA-IN

¡ó

COLUMN

ADDRESS

COLUMN

ADDRESS

RCD

CRP

CAS

RSH

¡ó

CSH

ASC

¡ó

W P

W C S

WCH

WCS

WCH

W P

W C S

WCH

¡ó

VALID

DATA-IN

VALID

DATA-IN

¡ó

D H

NOTE : D

OUT

= OPEN

¡ó

RAL

K4F171611D, K4F151611D

CMOS DRAM

K4F171612D, K4F151612D

RAS

UCAS

I/OH

I/OL

DQ0 ~ DQ7

ROW

ADDR

CSH

RASP

R P

ASR

Don

t care

FAST PAGE MODE WORD READ-MODIFY-WRITE CYCLE

Undefined

RCD

C P

RAD

CAH

D H

COL.

ADDR

COL.

ADDR

CAS

C R P

ASC

CAH

RAL

R C S

C W L

CWD

AWD

RWD

CWD

A W D

CWL

RAC

OEA

CLZ

CAC

OEZ

CPWD

OED

ASC

CLZ

OEA

CAC

OED

RWL

LCAS

RCD

C P

CAS

C R P

I/OH

I/OL

DQ8 ~ DQ15

VALID

DATA-OUT

RAC

CLZ

CAC

VALID

DATA-IN

VALID

DATA-OUT

VALID

DATA-IN

CLZ

CAC

D H

OEZ

OED

D S

OEZ

VALID

DATA-OUT

VALID

DATA-IN

VALID

DATA-OUT

VALID

DATA-IN

PRWC

RSH

W P

RCS

RAH

OED

K4F171611D, K4F151611D

CMOS DRAM

K4F171612D, K4F151612D

RAS

UCAS

I/OH

I/OL

DQ0 ~ DQ7

ROW

ADDR

CSH

RASP

R P

ASR

Don

t care

FAST PAGE MODE LOWER BYTE READ - MODIFY - WRITE CYCLE

Undefined

RAD

CAH

D H

COL.

ADDR

COL.

ADDR

ASC

CAH

RAL

RCS

CWL

CWD

A W D

RWD

W P

CWD

AWD

C W L

RAC

OEA

CLZ

CAC

OEZ

CPWD

OED

ASC

CLZ

OEA

CAC

D H

OED

R W L

LCAS

RCD

CAS

CRP

C R P

I/OH

I/OL

DQ8 ~ DQ15

D S

OEZ

VALID

DATA-OUT

VALID

DATA-IN

VALID

DATA-OUT

VALID

DATA-IN

RPC

RSH

PRWC

OPEN

RCS

RAH

K4F171611D, K4F151611D

CMOS DRAM

K4F171612D, K4F151612D

RAS

I/OH

I/OL

DQ0 ~ DQ7

ROW

ADDR

CSH

RASP

ASR

Don

t care

FAST PAGE MODE UPPER BYTE READ - MODIFY - WRITE CYCLE

Undefined

RAD

CAH

COL.

ADDR

COL.

ADDR

ASC

CAH

RAL

R C S

CWL

CWD

AWD

RWD

CWD

A W D

CWL

RAC

OEA

CLZ

CAC

OEZ

CPWD

OED

ASC

CLZ

OEA

CAC

OED

RWL

RCD

C P

CAS

C R P

I/OH

I/OL

DQ8 ~ DQ15

OEZ

VALID

DATA-OUT

VALID

DATA-IN

VALID

DATA-OUT

VALID

DATA-IN

D S

RPC

RSH

PRWC

OPEN

UCAS

LCAS

RCS

RAH

K4F171611D, K4F151611D

CMOS DRAM

K4F171612D, K4F151612D

CSR

OPEN

RAS

UCAS

ROW

ADDR

ASR

CRP

RAS - ONLY REFRESH CYCLE

LCAS

RAS

RAH

NOTE : W, OE , D

= Don

t care

OUT

= OPEN

RPC

CRP

CAS - BEFORE - RAS REFRESH CYCLE

NOTE : OE , A = Don

t care

RAS

UCAS

LCAS

RAS

RPC

C R P

CHR

CSR

CHR

OFF

OPEN

DQ0 ~ DQ7

DQ8 ~ DQ15

Don

t care

Undefined

K4F171611D, K4F151611D

CMOS DRAM

K4F171612D, K4F151612D

OEZ

DATA-IN

DATA-OUT

RAS

UCAS

ROW

ADDRESS

RAS

CHR

RCD

RSH

RAD

ASR

RAH

ASC

CRP

Don

t care

HIDDEN REFRESH CYCLE ( READ )

Undefined

LCAS

DQ0 ~ DQ7

DQ8 ~ DQ15

RSH

RCD

C R P

WRH

COLUMN

ADDRESS

OEA

RAS

CHR

CAH

RCS

RAC

CLZ

CAC

DATA-OUT

OFF

OPEN

RAL

K4F171611D, K4F151611D

CMOS DRAM

K4F171612D, K4F151612D

WCS

R P

RAS

UCAS

ROW

ADDRESS

RAS

CHR

RCD

RSH

RAD

ASR

RAH

ASC

C R P

Don

t care

HIDDEN REFRESH CYCLE ( WRITE )

Undefined

LCAS

DQ0 ~ DQ7

DQ8 ~ DQ15

RSH

RCD

CRP

WRH

COLUMN

ADDRESS

RAS

R C

CHR

CAH

WRP

NOTE : D

OUT

= OPEN

WCH

DATA-IN

D S

DATA-IN

R P

RAL

K4F171611D, K4F151611D

CMOS DRAM

K4F171612D, K4F151612D

CSR

OPEN

CAS - BEFORE - RAS SELF REFRESH CYCLE

NOTE : OE , A = Don

t care

RAS

UCAS

RPS

LCAS

RASS

RPC

C P

RPC

CSR

OFF

OPEN

DQ0 ~ DQ7

DQ8 ~ DQ15

WRP

WRH

CHS

C P

CHS

TEST MODE IN CYCLE

NOTE : OE , A = Don

t care

RAS

UCAS

LCAS

R C

RPC

C R P

CSR

OPEN

DQ0 ~ DQ15

CHR

CSR

CHR

RAS

R P

Don

t care

Undefined

WTS

WTH

OFF

K4F171611D, K4F151611D

CMOS DRAM

K4F171612D, K4F151612D

42 SOJ

400mil

0
.
4
0
0

(
1
0
.
1
6
)

0
.
4
3
5

(
1
1
.
0
6
)

0
.
4
4
5

(
1
1
.
3
0
)

1.080 (27.43)

1.070 (27.19)

MAX

1.091 (27.71)

0
.
1
4
8

(
3
.
7
6
)

0.032 (0.81)

0.026 (0.66)

0.021 (0.53)

0.015 (0.38)

0.027 (0.69)

0.012 (0.30)

0.006 (0.15)

0
.
3
6
0

(
9
.
1
5
)

0
.
3
8
0

(
9
.
6
5
)

MIN

#42

0.0375 (0.95)

0.050 (1.27)

Units : Inches (millimeters)

50(44) TSOP(II) 400mil

Units : Inches (millimeters)

MAX

0.047 (1.20)

MIN

0.002 (0.05)

0.018 (0.45)

0.010 (0.25)

0.0315 (0.80)

0.034 (0.875)

0.821 (20.85)
0.829 (21.05)

0.841 (21.35)

MAX

0.010 (0.25)

0.004 (0.10)

0
.
4
0
0

(
1
0
.
1
6
)

0
.
4
7
1

(
1
1
.
9
6
)

0
.
4
5
5

(
1
1
.
5
6
)

0~8

0.030 (0.75)

0.018 (0.45)

TYP

0.010 (0.25)

PACKAGE DIMENSION

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: K4F151611D-50

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: K4F151611D-50