CMOS DRAM
K4F170111C, K4F170112C
This is a family of 16,777,216 x 1 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory
cells within the same row. Power supply voltage (+5.0V or +3.3V), access time (-50 or -60), power consumption(Normal or Low power)
and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh
and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version.
This 16Mx1 Fast Page Mode DRAM family is fabricated using Samsung
s advanced CMOS process to realize high band-width, low
power consumption and high reliability. It may be used as main memory unit for high level computer and microcomputer.
Part Identification
- K4F170111C-B(F) (5V, 4K Ref.)
- K4F170112C-B(F) (3.3V, 4K Ref.)
Fast Page Mode operation
CAS-before-RAS refresh capability
RAS-only and Hidden refresh capability
Self-refresh capability (L-ver only)
Fast Parallel test mode capability
TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
Early Write Operation
JEDEC Standard pinout
Available in Plastic SOJ and TSOP(II) packages
Single +5V
10% power supply (5V product)
Single +3.3V
0.3V power supply (3.3V product)
Control
Clocks
RAS
CAS
W
Vcc
Vss
A0-A11
Memory Array
16,777,216 x1
Cells
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
16M x1Bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Refresh Cycles
Part
NO.
V
CC
Refresh
cycle
Refresh period
Normal
L-ver
K4F170111C
5V
4K
64ms
128ms
K4F170112C
3.3V
Performance Range
Speed
t
RAC
t
CAC
t
RC
t
PC
Remark
-50
50ns
13ns
90ns
35ns
5V/3.3V
-60
60ns
15ns
110ns
40ns
5V/3.3V
Active Power Dissipation
Speed
3.3V
5V
-50
324
495
-60
288
440
Unit : mW
S
e
n
s
e
A
m
p
s
&
I
/
O
Data out
Buffer
Data in
Buffer
D
Q
Col. Address Buffer
Row Address Buffer
Refresh Counter
Refresh Control
Refresh Timer
Column Decoder
Row Decoder
VBB Generator
A0-A11
CMOS DRAM
K4F170111C, K4F170112C
V
CC
D
N.C
W
RAS
A11
A10
A0
A1
A2
A3
V
CC
V
SS
Q
N.C
CAS
N.C
A9
A8
A7
A6
A5
A4
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
PIN CONFIGURATION (Top Views)
Pin Name
Pin Function
A0 - A11
Address Inputs (4K Product)
D
Data In
Q
Data Out
V
SS
Ground
RAS
Row Address Strobe
CAS
Column Address Strobe
W
Read/Write Input
V
CC
Power(+5.0V)
Power(+3.3V)
N.C
No Connection
V
CC
D
N.C
W
RAS
A11
A10
A0
A1
A2
A3
V
CC
V
SS
Q
N.C
CAS
N.C
A9
A8
A7
A6
A5
A4
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
B:300mil 26(24) SOJ
F:300mil 26(24) TSOP II
K4F170111(2)C-B
K4F170111(2)C-F
CMOS DRAM
K4F170111C, K4F170112C
ABSOLUTE MAXIMUM RATINGS
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted
to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Parameter
Symbol
Rating
Units
3.3V
5V
Voltage on any pin relative to V
SS
V
IN,
V
OUT
-0.5 to +4.6
-1.0 to +7.0
V
Voltage on V
CC
supply relative to V
SS
V
CC
-0.5 to +4.6
-1.0 to +7.0
V
Storage Temperature
Tstg
-55 to +150
-55 to +150
C
Power Dissipation
P
D
1
1
W
Short Circuit Output Current
I
OS
Address
50
50
mA
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to Vss, T
A
= 0 to 70
C)
*1 : V
CC
+1.3V/15ns(3.3V), V
CC
+2.0/20ns(5V), Pulse width is measured at V
CC
*2 : -1.3V/15ns(3.3V), -2.0/20ns(5V), Pulse width is measured at V
SS
Parameter
Symbol
3.3V
5V
Units
Min
Typ
Max
Min
Typ
Max
Supply Voltage
V
CC
3.0
3.3
3.6
4.5
5.0
5.5
V
Ground
V
SS
0
0
0
0
0
0
V
Input High Voltage
V
IH
2.0
-
V
CC
+0.3
*1
2.4
-
V
CC
+1.0
*1
V
Input Low Voltage
V
IL
-0.3
*2
-
0.8
-1.0
*2
-
0.8
V
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Max
Parameter
Symbol
Min
Max
Units
3.3V
Input Leakage Current (Any input 0
V
IN
V
IN
+0.3V,
all other input pins not under test=0 Volt)
I
I(L)
-5
5
uA
Output Leakage Current
(Data out is disabled, 0V
V
OUT
V
CC
)
I
O(L)
-5
5
uA
Output High Voltage Level(I
OH
=-2mA)
V
OH
2.4
-
V
Output Low Voltage Level(I
OL
=2mA)
V
OL
-
0.4
V
5V
Input Leakage Current (Any input 0
V
IN
V
IN
+0.5V,
all other input pins not under test=0 Volt)
I
I(L)
-5
5
uA
Output Leakage Current
(Data out is disabled, 0V
V
OUT
V
CC
)
I
O(L)
-5
5
uA
Output High Voltage Level(I
OH
=-5mA)
V
OH
2.4
-
V
Output Low Voltage Level(I
OL
=4.2mA)
V
OL
-
0.4
V
CMOS DRAM
K4F170111C, K4F170112C
*Note :
I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
, I
CC3
and I
CC6
address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one fast page mode cycle time, t
PC
.
DC AND OPERATING CHARACTERISTICS
(Continued)
I
CC1
* : Operating Current (RAS and CAS cycling @t
RC
=min.)
I
CC2
: Standby Current (RAS=CAS=W=V
IH
)
I
CC3
* : RAS-only Refresh Current (CAS=V
IH
, RAS cycling @t
RC
=min.)
I
CC4
* : Fast Page Mode Current (RAS=V
IL
, CAS, Address cycling @t
PC
=min.)
I
CC5
: Standby Current (RAS=CAS=W=V
CC
-0.2V)
I
CC6
* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @t
RC
=min.)
I
CC7
: Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(V
IH
)=V
CC
-0.2V, Input low voltage(V
IL
)=0.2V, CAS=0.2V,
DQ=Don
t care, T
RC
=31.25us(L-ver), T
RAS
=T
RAS
min~300ns
I
CCS
: Self Refresh Current
RAS=CAS=0.2V, W=A0 ~ A11=V
CC
-0.2V or 0.2V,
D, Q=V
CC
-0.2V, 0.2V or Open
Symbol
Power
Speed
Max
Units
K4F170112C
K4F170111C
I
CC1
Don
t care
-50
-60
90
80
90
80
mA
mA
I
CC2
Normal
L
Don
t care
1
1
2
1
mA
mA
I
CC3
Don
t care
-50
-60
90
80
100
90
mA
mA
I
CC4
Don
t care
-50
-60
90
80
90
80
mA
mA
I
CC5
Normal
L
Don
t care
0.5
200
1
250
mA
uA
I
CC6
Don
t care
-50
-60
90
80
100
90
mA
mA
I
CC7
L
Don
t care
200
300
uA
I
CCS
L
Don
t care
150
250
uA
CMOS DRAM
K4F170111C, K4F170112C
CAPACITANCE
(T
A
=25
C, V
CC
=5V or 3.3V, f=1MHz)
Parameter
Symbol
Min
Max
Units
Input capacitance [D]
C
IN1
-
7
pF
Input capacitance [A0 ~ A11]
C
IN2
-
5
pF
Input capacitance [RAS, CAS, W, OE]
C
IN3
-
7
pF
Output capacitance [Q]
C
OUT
-
7
pF
Test condition (5V device) : V
CC
=5.0V
10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V
Parameter
Symbol
-50
-60
Units
Notes
Min
Max
Min
Max
Random read or write cycle time
t
RC
90
110
ns
Read-modify-write cycle time
t
RWC
110
130
ns
Access time from RAS
t
RAC
50
60
ns
3,4,10
Access time from CAS
t
CAC
13
15
ns
3,5
Access time from column address
t
AA
25
30
ns
3,10
CAS to output in Low-Z
t
CLZ
0
0
ns
3
Output buffer turn-off delay
t
OFF
0
13
0
15
ns
6
Transition time (rise and fall)
t
T
3
50
3
50
ns
2
RAS precharge time
t
RP
30
40
ns
RAS pulse width
t
RAS
50
10K
60
10K
ns
RAS hold time
t
RSH
13
15
ns
CAS hold time
t
CSH
50
60
ns
CAS pulse width
t
CAS
13
10K
15
10K
ns
RAS to CAS delay time
t
RCD
20
37
20
45
ns
4
RAS to column address delay time
t
RAD
15
25
15
30
ns
10
CAS to RAS precharge time
t
CRP
5
5
ns
Row address set-up time
t
ASR
0
0
ns
Row address hold time
t
RAH
10
10
ns
Column address set-up time
t
ASC
0
0
ns
Column address hold time
t
CAH
10
10
ns
Column address to RAS lead time
t
RAL
25
30
ns
Read command set-up time
t
RCS
0
0
ns
Read command hold time referenced to CAS
t
RCH
0
0
ns
8
Read command hold time referenced to RAS
t
RRH
0
0
ns
8
Write command hold time
t
WCH
10
10
ns
Write command pulse width
t
WP
10
10
ns
Write command to RAS lead time
t
RWL
13
15
ns
Write command to CAS lead time
t
CWL
13
15
ns
AC CHARACTERISTICS
(0
C
T
A
70
C, See note 1,2)
Test condition (3.3V device) : V
CC
=3.3V
0.3V, Vih/Vil=2.0/0.8V, Voh/Vol=2.0/0.8V
CMOS DRAM
K4F170111C, K4F170112C
AC CHARACTERISTICS
(Continued)
Parameter
Symbol
-50
-60
Units
Notes
Min
Max
Min
Max
Data set-up time
t
DS
0
0
ns
9
Data hold time
t
DH
10
10
ns
9
Refresh period (Normal)
t
REF
64
64
ms
Refresh period (L-ver)
t
REF
128
128
ms
Write command set-up time
t
WCS
0
0
ns
7
CAS to W delay time
t
CWD
13
15
ns
7
RAS to W delay time
t
RWD
50
60
ns
7
Column address to W delay time
t
AWD
25
30
ns
7
CAS precharge to W delay time
t
CPWD
30
35
ns
CAS set-up time (CAS -before-RAS refresh)
t
CSR
5
5
ns
CAS hold time (CAS -before-RAS refresh)
t
CHR
10
10
ns
RAS to CAS precharge time
t
RPC
5
5
ns
Access time from CAS precharge
t
CPA
30
35
ns
3
Fast Page mode cycle time
t
PC
35
40
ns
Fast Page read-modify-write cycle time
t
PRWC
53
60
ns
CAS precharge time (Fast Page cycle)
t
CP
10
10
ns
RAS pulse width (Fast Page cycle)
t
RASP
50
200K
60
200K
ns
RAS hold time from CAS precharge
t
RHCP
30
35
ns
Write command set-up time (Test mode in)
t
WTS
10
10
ns
11
Write command hold time (Test mode in)
t
WTH
10
10
ns
11
W to RAS precharge time(C-B-R refresh)
t
WRP
10
10
ns
W to RAS hold time(C-B-R refresh)
t
WRH
10
10
ns
RAS pulse width (C-B-R self refresh)
t
RASS
100
100
us
13,14,15
RAS precharge time (C-B-R self refresh)
t
RPS
90
110
ns
13,14,15
CAS hold time (C-B-R self refresh)
t
CHS
-50
-50
ns
13,14,15
CMOS DRAM
K4F170111C, K4F170112C
TEST MODE CYCLE
Parameter
Symbol
-50
-60
Units
Notes
Min
Max
Min
Max
Random read or write cycle time
t
RC
95
115
ns
Read-modify-write cycle time
t
RWC
115
135
ns
Access time from RAS
t
RAC
55
65
ns
3,4,10,12
Access time from CAS
t
CAC
18
20
ns
3,5,12
Access time from column address
t
AA
30
35
ns
3,10,12
RAS pulse width
t
RAS
55
10K
65
10K
ns
CAS pulse width
t
CAS
18
10K
20
10K
ns
RAS hold time
t
RSH
18
20
ns
CAS hold time
t
CSH
55
65
ns
Column address to RAS lead time
t
RAL
30
35
ns
CAS to W delay time
t
CWD
18
20
ns
7
RAS to W delay time
t
RWD
55
65
ns
7
Column address to W delay time
t
AWD
30
35
ns
7
CAS precharge to W delay time
t
CPWD
35
40
ns
Fast Page mode cycle time
t
PC
40
45
ns
Fast Page read-modify-write cycle time
t
PRWC
58
65
ns
RAS pulse width (Fast Page cycle)
t
RASP
55
200K
65
200K
ns
Access time from CAS precharge
t
CPA
35
40
ns
3
( Note 11 )
CMOS DRAM
K4F170111C, K4F170112C
NOTES
An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles
before proper device operation is achieved.
V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals. Transition times are measured between
V
IH
(min) and V
IL
(max) and are assumed to be 5ns for all inputs.
Measured with a load equivalent to 2 TTL(5V)/1 TTL(3.3V) loads and 100pF.
Operation within the
t
RCD
(max) limit insures that
t
RAC
(max) can be met.
t
RCD
(max) is specified as a reference point only.
If
t
RCD
is greater than the specified
t
RCD
(max) limit, then access time is controlled exclusively by
t
CAC
.
Assumes that
t
RCD
t
RCD
(max).
t
OFF
(min)and
t
OEZ
(max) define the time at which the output achieves the open circuit condition and are not referenced V
oh
or V
ol
.
t
WCS
,
t
RWD
,
t
CWD
and
t
AWD
are non restrictive operating parameters. They are included in the data sheet as electrical char-
acteristics only. If
t
WCS
t
WCS
(min), the cycle is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If
t
CWD
t
CWD
(min),
t
RWD
t
RWD
(min) and
t
AWD
t
AWD
(min), then the cycle is a read-modify-write cycle
and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the
condition of the data out is indeterminate.
Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in read-modify-write cycles.
Operation within the
t
RAD
(max) limit insures that
t
RAC
(max) can be met.
t
RAD
(max) is specified as a reference point only.
If
t
RAD
is greater than the specified
t
RAD
(max) limit, then access time is controlled by
t
AA
.
These specifications are applied in the test mode.
In test mode read cycle, the value of
t
RAC
,
t
AA
,
t
CAC
is delayed by 2ns to 5ns for the specified values. These parameters
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
If
t
RASS
100us, then RAS precharge time must use
t
RPS
instead of
t
RP
.
For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K) cycles of burst refresh must be executed within
64ms before and after self refresh, in order to meet refresh specification.
For distributed CAS-before-RAS with 15.6us interval CAS-before-RAS refresh should be executed with in 15.6us immedi-
ately before and after self refresh in order to meet refresh specification.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
1.
2.
3.
4.
15.
CMOS DRAM
K4F170111C, K4F170112C
t
CRP
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
V
IH
-
V
IL
-
READ CYCLE
COLUMN
ADDRESS
ROW
ADDRESS
t
RAS
t
RC
t
CRP
t
RP
t
CSH
t
RSH
t
RCD
t
CAS
t
RAL
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
AA
t
CAC
t
CLZ
t
RAC
OPEN
DATA-OUT
t
RRH
t
RCH
Don
t care
Undefined
t
RCS
t
OFF
Q
CMOS DRAM
K4F170111C, K4F170112C
t
WCS
WRITE CYCLE ( EARLY WRITE )
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDRESS
t
RAS
t
RC
t
CRP
t
RP
t
CSH
t
RSH
t
RCD
t
CAS
t
RAL
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
CRP
t
WP
t
DS
t
DH
t
WCH
t
CWL
t
RWL
Don
t care
DATA-IN
Undefined
D
CMOS DRAM
K4F170111C, K4F170112C
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
V
IH
-
V
IL
-
ROW
ADDR
t
RAS
t
RWC
t
RP
t
RSH
t
RCD
t
CAS
t
CSH
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
CRP
t
WP
Don
t care
READ-WRITE / READ - MODIFY - WRTIE CYCLE
t
RWL
t
CWL
t
AWD
t
CWD
Undefined
t
RAC
t
AA
t
CAC
t
CLZ
COLUMN
ADDRESS
V
IH
-
V
IL
-
t
DS
t
DH
DATA-IN
D
DATA-OUT
Q
t
OFF
CMOS DRAM
K4F170111C, K4F170112C
t
RCH
t
CLZ
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDR
t
RHCP
t
RASP
t
CAS
t
ASC
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
CRP
VALID
Don
t care
FAST PAGE READ CYCLE
t
RRH
DATA-OUT
Undefined
VALID
DATA-OUT
COLUMN
ADDRESS
COLUMN
ADDRESS
t
RSH
t
CAS
t
RCD
t
PC
t
CSH
t
CAH
t
ASC
t
CAH
t
RCH
t
RCS
t
RCS
t
RCS
VALID
DATA-OUT
t
CLZ
t
OFF
t
AA
t
OFF
t
AA
t
CLZ
t
OFF
t
RAC
t
AA
t
CP
t
CAS
t
RP
t
CP
t
CAC
t
CAC
t
CAC
Q
t
RAL
CMOS DRAM
K4F170111C, K4F170112C
t
ASC
t
CAH
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDR
t
RHCP
t
RASP
t
CAS
t
RAD
t
ASR
t
RAH
t
ASC
t
CRP
VALID
Don
t care
FAST PAGE WRITE CYCLE ( EARLY WRITE )
DATA-IN
Undefined
VALID
DATA-IN
t
DS
COLUMN
ADDRESS
COLUMN
ADDRESS
t
RSH
t
CAS
t
RCD
t
PC
t
CSH
t
CAH
t
ASC
t
CAH
t
WCS
t
WCH
t
WCS
VALID
DATA-IN
t
WP
t
CWL
t
WP
t
WCH
t
WP
t
WCS
t
WCH
t
CWL
t
RWL
t
CWL
t
DH
t
DS
t
DH
t
DS
t
DH
t
RP
t
CP
t
CP
t
CAS
t
PC
D
t
RAL
CMOS DRAM
K4F170111C, K4F170112C
t
ASC
t
ASC
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
V
IH
-
V
IL
-
ROW
ADDR
t
CSH
t
RASP
t
ASR
Don
t care
FAST PAGE READ - MODIFY - WRITE CYCLE
Undefined
t
RCD
t
CP
t
RAD
t
CAH
t
WP
COL.
ADDR
COL.
ADDR
t
CAS
t
CAS
t
CRP
t
CAH
t
RAL
t
PRWC
t
RCS
t
CWL
t
CWD
t
AWD
t
RWD
t
WP
t
CWD
t
AWD
t
CWL
t
AA
t
RAC
t
CLZ
t
CAC
t
CPWD
t
CLZ
t
AA
t
RWL
t
RP
t
RSH
t
RAH
V
IH
-
V
IL
-
VALID
DATA-IN
t
DS
t
DH
D
VALID
DATA-IN
t
DS
t
DH
VALID
DATA-OUT
VALID
DATA-OUT
t
CAC
t
OFF
t
OFF
Q
CMOS DRAM
K4F170111C, K4F170112C
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
ROW
ADDR
t
RAS
t
RC
t
RP
t
ASR
t
RAH
t
CRP
Don
t care
RAS - ONLY REFRESH CYCLE
Undefined
NOTE : W, D
IN
= Don
t care
D
OUT
= OPEN
t
RPC
t
CRP
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : A = Don
t care
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
t
RAS
t
RC
t
RP
t
WRP
t
RPC
t
RP
t
CP
t
CHR
t
CSR
W
V
IH
-
V
IL
-
t
WRH
t
OFF
t
RPC
V
IH
-
V
IL
-
OPEN
Q
CMOS DRAM
K4F170111C, K4F170112C
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
V
IH
-
V
IL
-
HIDDEN REFRESH CYCLE ( READ )
COLUMN
ADDRESS
ROW
ADDRESS
t
RAS
t
RC
t
CHR
t
RCD
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
CRP
t
RCS
t
AA
t
CAC
t
CLZ
t
RAC
OPEN
Don
t care
t
RSH
t
WEZ
Undefined
t
RC
DATA-OUT
t
RP
t
RP
t
RAS
Q
t
OFF
t
WRH
t
RAL
CMOS DRAM
K4F170111C, K4F170112C
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
V
IH
-
V
IL
-
HIDDEN REFRESH CYCLE ( WRITE )
COLUMN
ADDRESS
ROW
ADDRESS
t
RAS
t
RC
t
CHR
t
RCD
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
CRP
Don
t care
t
RSH
DATA-IN
t
WRP
t
WRH
Undefined
t
RC
NOTE : D
OUT
= OPEN
t
WCH
t
WP
t
DH
t
RP
t
RP
t
RAS
t
DS
t
WCS
D
t
RAL
CMOS DRAM
K4F170111C, K4F170112C
Don
t care
Undefined
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : A = Don
t care
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
t
RASS
t
RPS
t
RPC
t
WRP
t
CHR
t
RP
t
CP
t
CSR
W
V
IH
-
V
IL
-
t
WRH
t
OFF
t
RPC
OPEN
V
OH
-
V
OL
-
Q
t
WRP
TEST MODE IN CYCLE
NOTE : D, A = Don
t care
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
t
RAS
t
RC
t
RP
t
RPC
t
WTS
t
RPC
t
RP
t
CP
t
CHR
t
CSR
W
V
IH
-
V
IL
-
t
WTH
t
OFF
OPEN
V
IH
-
V
IL
-
D
CMOS DRAM
K4F170111C, K4F170112C
0
.
3
0
0
(
7
.
6
2
)
0
.
3
3
0
(
8
.
3
9
)
0
.
3
4
0
(
8
.
6
3
)
0.680 (17.28)
0.670 (17.03)
MAX
0.691 (17.55)
M
A
X
0
.
1
4
8
(
3
.
7
6
)
0.0375 (0.95)
0.032 (0.81)
0.026 (0.66)
0.021 (0.53)
0.015 (0.38)
0.027 (0.69)
0.012 (0.30)
0.006 (0.15)
0
.
2
6
0
(
6
.
6
1
)
0
.
2
8
0
(
7
.
1
1
)
MIN
#26(24)
0.050 (1.27)
26(24) SOJ
300mil
Units : Inches (millimeters)
PACKAGE DIMENSION
26(24) TSOP(II) 300mil
MAX
0.047 (1.20)
MIN
0.002 (0.05)
0.020 (0.50)
0.012 (0.30)
0.050 (1.27)
0.037 (0.95)
0.671 (17.04)
0.679 (17.24)
0.691 (17.54)
MAX
0.010 (0.25)
0.004 (0.10)
0
.
3
0
0
(
7
.
6
2
)
0
.
3
7
1
(
9
.
4
2
)
0
.
3
5
5
(
9
.
0
2
)
Units : Inches (millimeters)
0~8
0.030 (0.75)
0.018 (0.45)
TYP
0.010 (0.25)
O
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