K4F170411C, K4F160411C

CMOS DRAM

K4F170412C, K4F160412C

This is a family of 4,194,304 x 4 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells

within the same row. Power supply voltage (+5.0V or +3.3V), refresh cycle (2K Ref. or 4K Ref.), access time (-50 or -60), power con-

sumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-

before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version.

This 4Mx4 Fast Page Mode DRAM family is fabricated using Samsung

s advanced CMOS process to realize high band-width, low power

consumption and high reliability. It may be used as main memory for high level computer, microcomputer and personal computer.

Part Identification

- K4F170411C-B(F) (5V, 4K Ref.)
- K4F160411C-B(F) (5V, 2K Ref.)
- K4F170412C-B(F) (3.3V, 4K Ref.)
- K4F160412C-B(F) (3.3V, 2K Ref.)

Fast Page Mode operation

CAS-before-RAS refresh capability

RAS-only and Hidden refresh capability

Self-refresh capability (L-ver only)

Fast parallel test mode capability

TTL(5V)/LVTTL(3.3V) compatible inputs and outputs

Early Write or output enable controlled write

JEDEC Standard pinout

Available in Plastic SOJ and TSOP(II) packages

Single +5V

10% power supply (5V product)

Single +3.3V

0.3V power supply (3.3V product)

Control
Clocks

RAS
CAS

Vcc
Vss

DQ0

DQ3

A0-A11

(A0 - A10)

A0 - A9

(A0 - A10)

Memory Array

4,194,304 x 4

Cells

SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.

4M x 4Bit CMOS Dynamic RAM with Fast Page Mode

DESCRIPTION

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Refresh Cycles

Part
NO.

Refresh

cycle

Refresh period

Nor-

L-ver

K4F170411C

64ms

128ms

K4F170412C

3.3V

K4F160411C

32ms

K4F160412C

3.3V

· Performance Range

Speed

RAC

CAC

Remark

-50

50ns

13ns

90ns

35ns

5V/3.3V

-60

60ns

15ns

110ns

40ns

5V/3.3V

Active Power Dissipation

Speed

3.3V

-50

324

396

495

605

-60

288

360

440

550

Unit : mW

I
/
O

Data out

Buffer

Data in

Buffer

Note)

: 2K Refresh

Col. Address Buffer

Row Address Buffer

Refresh Counter

Refresh Control

Refresh Timer

Column Decoder

Row Decoder

VBB Generator

K4F170411C, K4F160411C

CMOS DRAM

K4F170412C, K4F160412C

DQ0
DQ1

RAS

*A11(N.C)

A10

A0
A1
A2
A3

DQ3
DQ2
CAS
OE
A9

A8
A7
A6
A5
A4
V

1
2
3
4
5
6

7
8
9
10
11
12

24
23
22
21
20
19

18
17
16
15
14
13

PIN CONFIGURATION (Top Views)

Pin Name

Pin Function

A0 - A11

Address Inputs (4K Product)

A0 - A10

Address Inputs (2K Product)

DQ0 - 3

Data In/Out

Ground

RAS

Row Address Strobe

CAS

Column Address Strobe

Read/Write Input

Data Output Enable

Power(+5V)

Power(+3.3V)

N.C

No Connection (2K Ref. product)

DQ0
DQ1

RAS

*A11(N.C)

A10

A0
A1
A2
A3

DQ3
DQ2
CAS
OE
A9

A8
A7
A6
A5
A4
V

1
2
3
4
5
6

7
8
9
10
11
12

24
23
22
21
20
19

18
17
16
15
14
13

*A11 is N.C for K4F160411(2)C (5V/3.3V, 2K Ref. product)

B : 300mil 26(24) SOJ
F : 300mil 26(24) TSOP II

· K4F17(6)0411(2)C-B

· K4F17(6)0411(2)C-F

K4F170411C, K4F160411C

CMOS DRAM

K4F170412C, K4F160412C

ABSOLUTE MAXIMUM RATINGS

* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to

the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

Parameter

Symbol

Rating

Units

3.3V

Voltage on any pin relative to V

IN,

OUT

-0.5 to +4.6

-1.0 to +7.0

Voltage on V

supply relative to V

-0.5 to +4.6

-1.0 to +7.0

Storage Temperature

Tstg

-55 to +150

Power Dissipation

Short Circuit Output Current

Address

RECOMMENDED OPERATING CONDITIONS

(Voltage referenced to Vss, T

= 0 to 70

*1 : V

+1.3V/15ns(3.3V), V

+2.0V/20ns(5V), Pulse width is measured at V

*2 : -1.3V/15ns(3.3V), -2.0V/20ns(5V), Pulse width is measured at V

Parameter

Symbol

3.3V

Units

Min

Typ

Max

Min

Typ

Max

Supply Voltage

3.0

3.3

3.6

4.5

5.0

5.5

Ground

Input High Voltage

2.0

+0.3

2.4

+1.0

Input Low Voltage

-0.3

0.8

-1.0

0.8

DC AND OPERATING CHARACTERISTICS

(Recommended operating conditions unless otherwise noted.)

Max

Parameter

Symbol

Min

Max

Units

3.3V

Input Leakage Current (Any input 0

+0.3V,

all other input pins not under test=0 Volt)

I(L)

-5

Output Leakage Current
(Data out is disabled, 0V

OUT

)

O(L)

-5

Output High Voltage Level(I

=-2mA)

2.4

Output Low Voltage Level(I

=2mA)

0.4

Input Leakage Current (Any input 0

+0.5V,

all other input pins not under test=0 Volt)

I(L)

-5

Output Leakage Current
(Data out is disabled, 0V

OUT

)

O(L)

-5

Output High Voltage Level(I

=-5mA)

2.4

Output Low Voltage Level(I

=4.2mA)

0.4

K4F170411C, K4F160411C

CMOS DRAM

K4F170412C, K4F160412C

*Note :

CC1

, I

CC3

, I

CC4

and I

CC6

are dependent on output loading and cycle rates. Specified values are obtained with the output open.

is specified as an average current. In I

CC1

, I

CC3

and I

CC6

address can be changed maximum once while RAS=V

. In I

CC4

address can be changed maximum once within one fast page mode cycle time, t

DC AND OPERATING CHARACTERISTICS

(Continued)

CC1

* : Operating Current (RAS and CAS, Address cycling @t

=min.)

CC2

: Standby Current (RAS=CAS=W=V

)

CC3

* : RAS-only Refresh Current (CAS=V

, RAS, Address cycling @t

=min.)

CC4

* : Fast Page Mode Current (RAS=V

, CAS, Address cycling @t

=min.)

CC5

: Standby Current (RAS=CAS=W=V

-0.2V)

CC6

* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @t

=min.)

CC7

: Battery back-up current, Average power supply current, Battery back-up mode

Input high voltage(V

)=V

-0.2V, Input low voltage(V

)=0.2V, CAS=0.2V,

DQ=Don

t care, T

=31.25us(4K/L-ver), 62.5us(2K/L-ver), T

RAS

min~300ns

CCS

: Self Refresh Current

RAS=CAS=0.2V, W=OE=A0 ~ A11=V

-0.2V or 0.2V,

DQ0 ~ DQ3=V

-0.2V, 0.2V or Open

Symbol

Power

Speed

Max

Units

K4F170412C

K4F160412C

K4F170411C

K4F160411C

CC1

Don

t care

-50
-60

90
80

110

100

90
80

110
100

mA
mA

CC2

Normal

Don

t care

1
1

2
1

mA
mA

CC3

Don

t care

-50
-60

90
80

110

100

90
80

110
100

mA
mA

CC4

Don

t care

-50
-60

80
70

90
80

80
70

90
80

mA
mA

CC5

Normal

Don

t care

0.5

200

0.5

200

250

CC6

Don

t care

-50
-60

90
80

110

100

90
80

110
100

mA
mA

CC7

Don

t care

250

300

CCS

Don

t care

200

250

K4F170411C, K4F160411C

CMOS DRAM

K4F170412C, K4F160412C

CAPACITANCE

=25

C, V

=5V or 3.3V, f=1MHz)

Parameter

Symbol

Min

Max

Units

Input capacitance [A0 ~ A11]

IN1

Input capacitance [RAS, CAS, W, OE]

IN2

Output capacitance [DQ0 - DQ3]

Test condition (5V device) : V

=5.0V

10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V

Parameter

Symbol

-50

-60

Units

Notes

Min

Max

Min

Max

Random read or write cycle time

110

Read-modify-write cycle time

RWC

133

155

Access time from RAS

RAC

3,4,10

Access time from CAS

CAC

3,4,5

Access time from column address

3,10

CAS to output in Low-Z

CLZ

Output buffer turn-off delay

OFF

Transition time (rise and fall)

RAS precharge time

RAS pulse width

RAS

10K

RAS hold time

RSH

CAS hold time

CSH

CAS pulse width

CAS

10K

RAS to CAS delay time

RCD

RAS to column address delay time

RAD

CAS to RAS precharge time

CRP

Row address set-up time

ASR

Row address hold time

RAH

Column address set-up time

ASC

Column address hold time

CAH

Column address to RAS lead time

RAL

Read command set-up time

RCS

Read command hold time referenced to CAS

RCH

Read command hold time referenced to RAS

RRH

Write command hold time

WCH

Write command pulse width

Write command to RAS lead time

RWL

Write command to CAS lead time

CWL

AC CHARACTERISTICS

C, See note 1,2)

Test condition (3.3V device) : V

=3.3V

0.3V, Vih/Vil=2.0/0.8V, Voh/Vol=2.0/0.8V

K4F170411C, K4F160411C

CMOS DRAM

K4F170412C, K4F160412C

AC CHARACTERISTICS

(Continued)

Parameter

Symbol

-50

-60

Units

Note

Min

Max

Min

Max

Data set-up time

Data hold time

Refresh period (2K, Normal)

REF

Refresh period (4K, Normal)

REF

Refresh period (L-ver)

REF

128

Write command set-up time

WCS

CAS to W delay time

CWD

RAS to W delay time

RWD

Column address to W delay time

AWD

CAS precharge to W delay time

CPWD

CAS set-up time (CAS -before-RAS refresh)

CSR

CAS hold time (CAS -before-RAS refresh)

CHR

RAS to CAS precharge time

RPC

Access time from CAS precharge

CPA

Fast Page cycle time

Fast Page read-modify-write cycle time

PRWC

CAS precharge time (Fast Page cycle)

RAS pulse width (Fast Page cycle)

RASP

200K

RAS hold time from CAS precharge

RHCP

OE access time

OEA

OE to data delay

OED

Output buffer turn off delay time from OE

OEZ

OE command hold time

OEH

Write command set-up time (Test mode in)

WTS

Write command hold time (Test mode in)

WTH

W to RAS precharge time(C-B-R refresh)

WRP

W to RAS hold time(C-B-R refresh)

WRH

RAS pulse width (C-B-R self refresh)

RASS

100

13,14,15

RAS precharge time (C-B-R self refresh)

RPS

110

13,14,15

CAS hold time (C-B-R self refresh)

CHS

-50

13,14,15

K4F170411C, K4F160411C

CMOS DRAM

K4F170412C, K4F160412C

TEST MODE CYCLE

Parameter

Symbol

-50

-60

Units

Notes

Min

Max

Min

Max

Random read or write cycle time

115

Read-modify-write cycle time

RWC

138

160

Access time from RAS

RAC

3,4,10,12

Access time from CAS

CAC

3,4,5,12

Access time from column address

3,10,12

RAS pulse width

RAS

10K

CAS pulse width

CAS

10K

RAS hold time

RSH

CAS hold time

CSH

Column address to RAS lead time

RAL

CAS to W delay time

CWD

RAS to W delay time

RWD

Column address to W delay time

AWD

CAS precharge to W delay time

CPWD

Fast Page cycle time

Fast Page read-modify-write cycle time

PRWC

RAS pulse width (Fast Page cycle)

RASP

200K

Access time from CAS precharge

CPA

OE access time

OEA

OE to data delay

OED

OE command hold time

OEH

( Note 11 )

K4F170411C, K4F160411C

CMOS DRAM

K4F170412C, K4F160412C

NOTES

An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles

before proper device operation is achieved.

(min) and V

(max) are reference levels for measuring timing of input signals. Transition times are measured between

(min) and V

(max) and are assumed to be 5ns for all inputs.

Measured with a load equivalent to 2 TTL(5V)/1 TTL(3.3V) loads and 100pF.

Operation within the

RCD

(max) limit insures that

RAC

(max) can be met.

RCD

(max) is specified as a reference point only.

RCD

is greater than the specified

RCD

(max) limit, then access time is controlled exclusively by

CAC

Assumes that

RCD

(max).

OFF

(min)and

OEZ

(max) define the time at which the output achieves the open circuit condition and are not referenced V

WCS

RWD

CWD

and

AWD

are non restrictive operating parameters. They are included in the data sheet as electrical charac-

teristics only. If

WCS

(min), the cycle is an early write cycle and the data output will remain high impedance for the dura-

tion of the cycle. If

CWD

(min),

RWD

(min) and

AWD

(min), then the cycle is a read-modify-write cycle and the

data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition

of the data out is indeterminate.

Either

RCH

RRH

must be satisfied for a read cycle.

These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in read-modify-write cycles.

Operation within the

RAD

(max) limit insures that

RAC

(max) can be met.

RAD

(max) is specified as a reference point only.

RAD

is greater than the specified

RAD

(max) limit, then access time is controlled by

These specifications are applied in the test mode.

In test mode read cycle, the value of

RAC

CAC

is delayed by 2ns to 5ns for the specified values. These parameters

should be specified in test mode cycles by adding the above value to the specified value in this data sheet.

RASS

100us, then RAS precharge time must use

RPS

instead of

For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K)/2048(2K) cycles of burst refresh must be exe-

cuted within 64ms/32ms before and after self refresh, in order to meet refresh specification.

For distributed CAS-before-RAS with 15.6us interval CAS-before-RAS refresh should be executed with in 15.6us immedi-

ately before and after self refresh in order to meet refresh specification.

10.

11.

12.

13.

14.

15.

K4F170411C, K4F160411C

CMOS DRAM

K4F170412C, K4F160412C

RCH

OEZ

CLZ

RAS

CAS

DQ0 ~ DQ3(7)

COLUMN

ADDRESS

ROW

ADDR

RHCP

RASP

CAS

ASC

RAD

ASR

RAH

ASC

CAH

CRP

VALID

Don

t care

FAST PAGE READ CYCLE

OEZ

RRH

DATA-OUT

Undefined

VALID

DATA-OUT

COLUMN

ADDRESS

COLUMN

ADDRESS

RSH

CAS

RCD

¡ó

CSH

CAH

ASC

CAH

¡ó

RCH

¡ó

RCS

OEA

CAC

OEA

CAC

OEA

CAC

VALID

DATA-OUT

CLZ

OFF

CLZ

OFF

OEZ

RAC

¡ó

CAS

RAL

K4F170411C, K4F160411C

CMOS DRAM

K4F170412C, K4F160412C

ASC

CAH

RAS

CAS

DQ0 ~ DQ3(7)

COLUMN

ADDRESS

ROW

ADDR

RHCP

RASP

CAS

RAD

ASR

RAH

ASC

CRP

VALID

Don

t care

FAST PAGE WRITE CYCLE ( EARLY WRITE )

DATA-IN

Undefined

VALID

DATA-IN

NOTE : D

OUT

= OPEN

COLUMN

ADDRESS

COLUMN

ADDRESS

RSH

CAS

RCD

¡ó

CSH

CAH

¡ó

WCS

WCH

WCS

VALID

DATA-IN

¡ó

CWL

WCH

WCS

WCH

CWL

RWL

CWL

¡ó

CAS

RAL

ASC

K4F170411C, K4F160411C

CMOS DRAM

K4F170412C, K4F160412C

CAC

ASC

RAS

CAS

I/OH

I/OL

DQ0 ~ DQ3(7)

ROW

ADDR

CSH

RASP

ASR

VALID

Don

t care

FAST PAGE READ - MODIFY - WRITE CYCLE

DATA-OUT

Undefined

RCD

RAD

CAH

COL.

ADDR

COL.

ADDR

CAS

CRP

CAH

RAL

PRWC

RCS

CWL

CWD

AWD

RWD

CWD

AWD

CWL

RAC

OEA

CLZ

CAC

OEZ

CPWD

OED

VALID

DATA-IN

VALID

DATA-OUT

VALID

DATA-IN

CLZ

OEA

OEZ

OED

RWL

RSH

RAH

K4F170411C, K4F160411C

CMOS DRAM

K4F170412C, K4F160412C

RAS

CAS

ROW

ADDR

RAS

ASR

RAH

CRP

Don

t care

RAS - ONLY REFRESH CYCLE

Undefined

NOTE : W, OE, D

= Don

t care

OUT

= OPEN

RPC

CRP

CAS - BEFORE - RAS REFRESH CYCLE

NOTE : OE, A = Don

t care

RAS

CAS

RAS

WRP

RPC

CHR

CSR

WRH

OFF

RPC

DQ0 ~ DQ3(7)

OPEN

K4F170411C, K4F160411C

CMOS DRAM

K4F170412C, K4F160412C

Don

t care

Undefined

CAS - BEFORE - RAS SELF REFRESH CYCLE

NOTE : OE, A = Don

t care

RAS

CAS

RASS

RPS

RPC

WRP

CHS

CSR

WRH

OFF

RPC

OPEN

DQ0 ~ DQ3(7)

TEST MODE IN CYCLE

NOTE : OE, A = Don

t care

RAS

CAS

RAS

RPC

WTS

RPC

CHR

CSR

WTH

OFF

OPEN

DQ0 ~ DQ3(7)

K4F170411C, K4F160411C

CMOS DRAM

K4F170412C, K4F160412C

.
3

(
7

.
6

)

.
3

(
8

.
3

)

.
3

(
8

.
6

)

0.680 (17.28)

0.670 (17.03)

MAX

0.691 (17.55)

.
1

(
3

.
7

)

0.0375 (0.95)

0.032 (0.81)

0.026 (0.66)

0.021 (0.53)

0.015 (0.38)

0.027 (0.69)

0.012 (0.30)

0.006 (0.15)

.
2

(
6

.
6

)

.
2

(
7

.
1

)

MIN

#26(24)

0.050 (1.27)

26(24) SOJ

300mil

Units : Inches (millimeters)

PACKAGE DIMENSION

26(24) TSOP(II) 300mil

MAX

0.047 (1.20)

MIN

0.002 (0.05)

0.020 (0.50)

0.012 (0.30)

0.050 (1.27)

0.037 (0.95)

0.671 (17.04)
0.679 (17.24)

0.691 (17.54)

MAX

0.010 (0.25)

0.004 (0.10)

.
3

(
7

.
6

)

.
3

(
9

.
4

)

.
3

(
9

.
0

)

Units : Inches (millimeters)

0~8

0.030 (0.75)

0.018 (0.45)

TYP

0.010 (0.25)

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