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Электронный компонент: K4F641611D

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CMOS DRAM
K4F661611D,
K4F641611D
This is a family of 4,194,304 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory
cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time ( -50 or -60) are optional features of this family. All of this family
have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. This 4Mx16 Fast Page Mode DRAM family is fabri-
cated using Samsung
s advanced CMOS process to realize high band-width, low power consumption and high reliability.
Fast Page Mode operation
2CAS Byte/Word Read/Write operation
CAS-before-RAS refresh capability
RAS-only and Hidden refresh capability
Fast parallel test mode capability
TTL(5.0V) compatible inputs and outputs
Early Write or output enable controlled write
JEDEC Standard pinout
Available in Plastic TSOP(II) package
+5.0V
10% power supply
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
4M x 16bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
Control
Clocks
Lower
Data out
Buffer
RAS
UCAS
LCAS
W
Vcc
Vss
DQ0
to
DQ7
A0~A12
(A0~A11)*1
A0~A8
(A0~A9)*1
Memory Array
4,194,304 x 16
Cells
FUNCTIONAL BLOCK DIAGRAM
Note) *1 : 4K Refresh
S
e
n
s
e

A
m
p
s

&

I
/
O
Upper
Data in
Buffer
Upper
Data out
Buffer
Lower
Data in
Buffer
DQ8
to
DQ15
OE
Row Decoder
Column Decoder
VBB Generator
Refresh Timer
Refresh Control
Refresh Counter
Row Address Buffer
Col. Address Buffer
Part Identification
- K4F661611D-TC(5.0V, 8K Ref.)
- K4F641611D-TC(5.0V, 4K Ref.)
FEATURES
Refresh Cycles
Part
NO.
Refresh
cycle
Refresh time
Normal
K4F661611D*
8K
64ms
K4F641611D
4K
Performance Range
Speed
t
RAC
t
CAC
t
RC
t
PC
-50
50ns
13ns
90ns
35ns
-60
60ns
15ns
110ns
40ns
Active Power Dissipation
Speed
8K
4K
-50
495
660
-60
440
605
Unit : mW
* Access mode & RAS only refresh mode
: 8K cycle/64ms
CAS-before-RAS & Hidden refresh mode
: 4K cycle/64ms
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CMOS DRAM
K4F661611D,
K4F641611D
PIN CONFIGURATION (Top Views)
V
CC
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
N.C
V
CC
W
RAS
N.C
N.C
N.C
N.C
A0
A1
A2
A3
A4
A5
V
CC
V
SS
DQ15
DQ14
DQ13
DQ12
V
SS
DQ11
DQ10
DQ9
DQ8
N.C
V
SS
LCAS
UCAS
OE
N.C
N.C
A12(N.C)*
A11
A10
A9
A8
A7
A6
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
Pin Name
Pin function
A0 - A12
Address Inputs(8K Product)
A0 - A11
Address Inputs(4K Product)
DQ0 - 15
Data In/Out
V
SS
Ground
RAS
Row Address Strobe
UCAS
Upper Column Address Strobe
LCAS
Lower Column Address Strobe
W
Read/Write Input
OE
Data Output Enable
V
CC
Power(+5.0V)
N.C
No Connection
(400mil TSOP(II))
*(N.C) : N.C for 4K Refresh Product
K4F661611D-T
 K4F641611D-T
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CMOS DRAM
K4F661611D,
K4F641611D
ABSOLUTE MAXIMUM RATINGS
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Parameter
Symbol
Rating
Units
Voltage on any pin relative to V
SS
V
IN,
V
OUT
-1.0 to +7.0
V
Voltage on V
CC
supply relative to V
SS
V
CC
-1.0 to +7.0
V
Storage Temperature
Tstg
-55 to +150
C
Power Dissipation
P
D
1
W
Short Circuit Output Current
I
OS
Address
50
mA
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to Vss, T
A
= 0 to 70
C)
*1 : V
CC
+2.0V at pulse width
20ns which is measured at V
CC
*2 : -2.0 at pulse width
20ns which is measured at V
SS
Parameter
Symbol
Min
Typ
Max
Units
Supply Voltage
V
CC
4.5
5.0
5.5
V
Ground
V
SS
0
0
0
V
Input High Voltage
V
IH
2.6
-
V
CC
+1.0
*1
V
Input Low Voltage
V
IL
-1.0
-
0.7
V
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter
Symbol
Min
Max
Units
Input Leakage Current (Any input 0
V
IN
V
CC
+0.5V,
all other pins not under test=0 Volt)
I
I(L)
-5
5
uA
Output Leakage Current
(Data out is disabled, 0V
V
OUT
V
CC
)
I
O(L)
-5
5
uA
Output High Voltage Level(I
OH
=-5mA)
V
OH
2.4
-
V
Output Low Voltage Level(I
OL
=4.2mA)
V
OL
-
0.4
V
*2
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CMOS DRAM
K4F661611D,
K4F641611D
*Note :
I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
, I
CC3
and I
CC6,
address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one fast page mode cycle time,
t
PC
.
DC AND OPERATING CHARACTERISTICS
(Continued)
I
CC1
* : Operating Current (RAS and UCAS, LCAS, Address cycling @
t
RC
=min.)
I
CC2
: Standby Current (RAS=UCAS=LCAS=W=V
IH
)
I
CC3
* : RAS-only Refresh Current (UCAS=LCAS=V
IH
, RAS, Address cycling @
t
RC
=min.)
I
CC4
* : Fast Page Mode Current (RAS=V
IL
, UCAS or LCAS, Address cycling @
t
PC
=min.)
I
CC5
: Standby Current (RAS=UCAS=LCAS=W=V
CC
-0.2V)
I
CC6
* : CAS-Before-RAS Refresh Current (RAS and UCAS or LCAS cycling @
t
RC
=min)
Symbol
Power
Speed
Max
Units
K4F661611D
K4F641611D
I
CC1
Don
t care
-50
-60
90
80
120
110
mA
mA
I
CC2
Normal
Don
t care
2
2
mA
I
CC3
Don
t care
-50
-60
90
80
120
110
mA
mA
I
CC4
Don
t care
-50
-60
60
50
70
60
mA
mA
I
CC5
Normal
Don
t care
1
1
mA
I
CC6
Don
t care
-50
-60
120
110
120
110
mA
mA
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CMOS DRAM
K4F661611D,
K4F641611D
CAPACITANCE
(T
A
=25
C, V
CC
=5.0V, f=1MHz)
Parameter
Symbol
Min
Max
Units
Input capacitance [A0 ~ A12]
C
IN1
-
5
pF
Input capacitance [RAS, UCAS, LCAS, W, OE]
C
IN2
-
7
pF
Output capacitance [DQ0 - DQ15]
C
DQ
-
7
pF
Test condition : V
CC
=5.0V
10%, Vih/Vil=2.6/0.7V, Voh/Vol=2.4/0.6V
Parameter
Symbol
-50
-60
Units
Note
Min
Max
Min
Max
Random read or write cycle time
t
RC
90
110
ns
Read-modify-write cycle time
t
RWC
133
153
ns
Access time from RAS
t
RAC
50
60
ns
3,4,10
Access time from CAS
t
CAC
13
15
ns
3,4,5
Access time from column address
t
AA
25
30
ns
3,10
CAS to output in Low-Z
t
CLZ
0
0
ns
3
Output buffer turn-off delay
t
OFF
0
13
0
13
ns
6
Transition time (rise and fall)
t
T
1
50
1
50
ns
2
RAS precharge time
t
RP
30
40
ns
RAS pulse width
t
RAS
50
10K
60
10K
ns
RAS hold time
t
RSH
13
15
ns
CAS hold time
t
CSH
50
60
ns
CAS pulse width
t
CAS
13
10K
15
10K
ns
RAS to CAS delay time
t
RCD
20
37
20
45
ns
4
RAS to column address delay time
t
RAD
15
25
15
30
ns
10
CAS to RAS precharge time
t
CRP
5
5
ns
Row address set-up time
t
ASR
0
0
ns
Row address hold time
t
RAH
10
10
ns
Column address set-up time
t
ASC
0
0
ns
13
Column address hold time
t
CAH
10
10
ns
13
Column address to RAS lead time
t
RAL
25
30
ns
Read command set-up time
t
RCS
0
0
ns
Read command hold time referenced to CAS
t
RCH
0
0
ns
8
Read command hold time referenced to RAS
t
RRH
0
0
ns
8
Write command hold time
t
WCH
10
10
ns
Write command pulse width
t
WP
10
10
ns
Write command to RAS lead time
t
RWL
15
15
ns
Write command to CAS lead time
t
CWL
13
15
ns
16
Data set-up time
t
DS
0
0
ns
9,19
Data hold time
t
DH
10
10
ns
9,19
AC CHARACTERISTICS
(0
C
T
A
70
C, See note 1,2)
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CMOS DRAM
K4F661611D,
K4F641611D
AC CHARACTERISTICS
(Continued)
Parameter
Symbol
-50
-60
Units
Note
Min
Max
Min
Max
Refresh period (4K, Normal)
t
REF
64
64
ms
Refresh period (8K, Normal)
t
REF
64
64
ms
Write command set-up time
t
WCS
0
0
ns
7
CAS to W delay time
t
CWD
36
38
ns
7,15
RAS to W delay time
t
RWD
73
83
ns
7
Column address to W delay time
t
AWD
48
53
ns
7
CAS precharge W delay time
t
CPWD
53
60
ns
CAS set-up time (CAS -before-RAS refresh)
t
CSR
5
5
ns
17
CAS hold time (CAS -before-RAS refresh)
t
CHR
10
10
ns
18
RAS to CAS precharge time
t
RPC
5
5
ns
Access time from CAS precharge
t
CPA
30
35
ns
3
Fast Page mode cycle time
t
PC
35
40
ns
Fast Page mode read-modify-write cycle time
t
PRWC
76
85
ns
CAS precharge time (Fast Page cycle)
t
CP
10
10
ns
14
RAS pulse width (Fast Page cycle)
t
RASP
50
200K
60
200K
ns
RAS hold time from CAS precharge
t
RHCP
30
35
ns
OE access time
t
OEA
13
15
ns
OE to data delay
t
OED
13
13
ns
Output buffer turn off delay time from OE
t
OEZ
0
13
0
13
ns
6
OE command hold time
t
OEH
13
15
ns
Write command set-up time (Test mode in)
t
WTS
10
10
ns
11
Write command hold time (Test mode in)
t
WTH
15
15
ns
11
W to RAS precharge time (C-B-R refresh)
t
WRP
10
10
ns
W to RAS hold time (C-B-R refresh)
t
WRH
10
10
ns
RAS pulse width (C-B-R self refresh)
t
RASS
100
100
us
20,21,22
RAS precharge time (C-B-R self refresh)
t
RPS
90
110
ns
20,21,22
CAS hold time (C-B-R self refresh)
t
CHS
-50
-50
ns
20,21,22
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CMOS DRAM
K4F661611D,
K4F641611D
TEST MODE CYCLE
Parameter
Symbol
-50
-60
Units
Note
Min
Max
Min
Max
Random read or write cycle time
t
RC
95
115
ns
Read-modify-write cycle time
t
RWC
138
160
ns
Access time from RAS
t
RAC
55
65
ns
3,4,10,12
Access time from CAS
t
CAC
18
20
ns
3,4,5,12
Access time from column address
t
AA
30
35
ns
3,10,12
RAS pulse width
t
RAS
55
10K
65
10K
ns
CAS pulse width
t
CAS
18
10K
20
10K
ns
RAS hold time
t
RSH
18
20
ns
CAS hold time
t
CSH
55
65
ns
Column Address to RAS lead time
t
RAL
30
35
ns
CAS to W delay time
t
CWD
41
43
ns
7
RAS to W delay time
t
RWD
78
88
ns
7
Column Address to W delay time
t
AWD
53
58
ns
7
Fast Page mode cycle time
t
PC
40
45
ns
Fast Page mode read-modify-write cycle time
t
PRWC
81
90
ns
RAS pulse width (Fast Page cycle)
t
RASP
55
200K
65
200K
ns
Access time from CAS precharge
t
CPA
35
40
ns
3
OE access time
t
OEA
18
20
ns
OE to data delay
t
OED
18
18
ns
OE command hold time
t
OEH
18
20
ns
( Note 11 )
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CMOS DRAM
K4F661611D,
K4F641611D
K4F64(6)1611C Truth Table
RAS
LCAS
UCAS
W
OE
DQ0 - DQ7
DQ8-DQ15
STATE
H
X
X
X
X
Hi-Z
Hi-Z
Standby
L
H
H
X
X
Hi-Z
Hi-Z
Refresh
L
L
H
H
L
DQ-OUT
Hi-Z
Byte Read
L
H
L
H
L
Hi-Z
DQ-OUT
Byte Read
L
L
L
H
L
DQ-OUT
DQ-OUT
Word Read
L
L
H
L
H
DQ-IN
-
Byte Write
L
H
L
L
H
-
DQ-IN
Byte Write
L
L
L
L
H
DQ-IN
DQ-IN
Word Write
L
L
L
H
H
Hi-Z
Hi-Z
-
NOTES
An initial pause of 200
us
is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles
before proper device operation is achieved.
V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals. Transition times are measured between
V
IH
(min) and V
IL
(max) and are assumed to be 5ns for all inputs.
Measured with a load equivalent to 2 TTL load and 100pF.
Operation within the
t
RCD
(max) limit insures that
t
RAC
(max) can be met,
t
RCD
(max) is specified as a reference point only.
If
t
RCD
is greater than the specified
t
RCD
(max) limit, then access time is controlled exclusively by
t
CAC
.
Assumes that
t
RCD
t
RCD
(max).
t
OFF
(min)and
t
OEZ
(max) define the time at which the output achieves the open circuit condition and are not referenced V
oh
or V
ol
.
t
WCS
,
t
RWD
,
t
CWD
and
t
AWD
are non restrictive operating parameters. They are included in the data sheet as electrical char-
acteristics only. If
t
WCS
t
WCS
(min), the cycle is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If
t
CWD
t
CWD
(min),
t
RWD
t
RWD
(min) and
t
AWD
t
AWD
(min), then the cycle is a read-modify-write cycle
and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the
condition of the data out is indeterminate.
Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in read-modify-write cycles.
Operation within the
t
RAD
(max) limit insures that
t
RAC
(max) can be met.
t
RAD
(max) is specified as a reference point only.
If
t
RAD
is greater than the specified
t
RAD
(max) limit, then access time is controlled by
t
AA
.
These specifications are applied in the test mode.
In test mode read cycle, the value of
t
RAC
,
t
AA
,
t
CAC
is delayed by 2ns to 5ns for the specified values. These parameters
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
5.
6.
7.
8.
9.
10.
11.
12.
1.
2.
3.
4.
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CMOS DRAM
K4F661611D,
K4F641611D
t
ASC
,
t
CAH
are referenced to the earlier CAS falling edge.
t
CP
is specified from the later CAS rising edge in the previous cycle to the earlier CAS falling edge in the next cycle.
t
CWD
is referenced to the later CAS falling edge at word read-modify-write cycle.
t
CWL
is specified from W falling edge to the earlier CAS rising edge.
t
CSR
is referenced to the earlier CAS falling edge before RAS transition low.
t
CHR
is referenced to the later CAS rising edge after RAS transition low.
t
DS
is specified for the earlier CAS falling edge and
t
DH
is specified by the later CAS falling edge.
If
t
RASS
100us, then RAS precharge time must use
t
RPS
instead of
t
RP
.
For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K/8K) cycles of burst refresh must be executed within
64ms before and after self refresh, in order to meet refresh specification.
For distributed CAS-before-RAS with 15.6us interval CAS-before-RAS refresh should be executed with in 15.6us immediately
before and after self refresh in order to meet refresh specification.
t
CSR
t
CHR
RAS
LCAS
UCAS
t
DS
t
DH
LCAS
UCAS
DQ0 ~ DQ15
Din
21.
20.
19.
15.
14.
13.
18.
17.
16.
22.
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CMOS DRAM
K4F661611D,
K4F641611D
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
V
OH
-
V
OL
-
DQ0 ~ DQ7
COLUMN
ADDRESS
ROW
ADDRESS
t
RAS
t
RC
t
CRP
t
RP
t
CSH
t
RSH
t
RCD
t
CAS
t
RAL
t
ASR
t
RAH
t
ASC
t
CAH
t
CRP
t
AA
t
OEA
t
CAC
t
CLZ
t
RAC
OPEN
t
OFF
t
RCH
Don
t care
Undefined
LCAS
V
IH
-
V
IL
-
t
CRP
t
CSH
t
RSH
t
RCD
t
CAS
t
RAD
t
CRP
t
RRH
V
OH
-
V
OL
-
DQ8 ~ DQ15
t
CAC
t
CLZ
t
RAC
OPEN
DATA-OUT
DATA-OUT
t
OFF
t
OEZ
t
OEZ
t
RCS
WORD READ CYCLE
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CMOS DRAM
K4F661611D,
K4F641611D
t
CRP
NOTE : D
IN
= OPEN
LOWER BYTE READ CYCLE
RAS
V
IH
-
V
IL
-
LCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
V
OH
-
V
OL
-
DQ0 ~ DQ7
COLUMN
ADDRESS
ROW
ADDRESS
t
RAS
t
RC
t
RP
t
CSH
t
RSH
t
RCD
t
CAS
t
RAL
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
CRP
t
AA
t
OEA
t
CAC
t
CLZ
t
RAC
OPEN
DATA-OUT
t
OEZ
t
OFF
t
RCH
Don
t care
Undefined
t
RPC
UCAS
V
IH
-
V
IL
-
OPEN
V
OH
-
V
OL
-
DQ8 ~ DQ15
t
RCS
t
RRH
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CMOS DRAM
K4F661611D,
K4F641611D
NOTE : D
IN
= OPEN
UPPER BYTE READ CYCLE
RAS
V
IH
-
V
IL
-
LCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
V
OH
-
V
OL
-
DQ0 ~ DQ7
COLUMN
ADDRESS
ROW
ADDRESS
t
RAS
t
RC
t
CRP
t
RP
t
CSH
t
RSH
t
RCD
t
CAS
t
RAL
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
CRP
t
AA
t
OEA
t
CAC
t
CLZ
t
RAC
OPEN
DATA-OUT
t
OEZ
t
OFF
t
RRH
t
RCH
Don
t care
Undefined
UCAS
V
IH
-
V
IL
-
OPEN
V
OH
-
V
OL
-
DQ8 ~ DQ15
t
CRP
t
RPC
t
RCS
background image
CMOS DRAM
K4F661611D,
K4F641611D
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDRESS
t
RAS
t
RC
t
CRP
t
RP
t
CSH
t
RSH
t
RCD
t
CAS
t
RAL
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
CRP
Don
t care
WORD WRITE CYCLE ( EARLY WRITE )
NOTE : D
OUT
= OPEN
Undefined
LCAS
V
IH
-
V
IL
-
t
WCS
V
IH
-
V
IL
-
DQ0 ~ DQ7
t
DS
V
IH
-
V
IL
-
DQ8 ~ DQ15
t
CRP
t
CSH
t
RSH
t
RCD
t
CAS
t
CRP
t
WCH
t
WP
t
DH
DATA-IN
t
DS
t
DH
DATA-IN
background image
CMOS DRAM
K4F661611D,
K4F641611D
t
CRP
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDRESS
t
RAS
t
RC
t
RP
t
RAL
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
Don
t care
LOWER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : D
OUT
= OPEN
Undefined
LCAS
V
IH
-
V
IL
-
t
WCS
V
IH
-
V
IL
-
DQ0 ~ DQ7
t
DS
V
IH
-
V
IL
-
DQ8 ~ DQ15
t
CRP
t
CSH
t
RSH
t
RCD
t
CAS
t
WCH
t
WP
t
DH
DATA-IN
t
CRP
t
RPC
background image
CMOS DRAM
K4F661611D,
K4F641611D
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDRESS
t
RAS
t
RC
t
CRP
t
RP
t
CSH
t
RSH
t
RCD
t
CAS
t
RAL
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
CRP
Don
t care
UPPER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : D
OUT
= OPEN
Undefined
LCAS
V
IH
-
V
IL
-
t
WCS
V
IH
-
V
IL
-
DQ0 ~ DQ7
V
IH
-
V
IL
-
DQ8 ~ DQ15
t
WCH
t
WP
t
DS
t
DH
DATA-IN
t
CRP
t
RPC
background image
CMOS DRAM
K4F661611D,
K4F641611D
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
ROW
ADDRESS
t
RAS
t
RC
t
CRP
t
RP
t
CSH
t
RSH
t
RCD
t
CAS
t
RAL
t
RAD
t
ASR
t
RAH
t
ASC
t
CRP
Don
t care
WORD WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : D
OUT
= OPEN
Undefined
LCAS
V
IH
-
V
IL
-
V
IH
-
V
IL
-
DQ0 ~ DQ7
V
IH
-
V
IL
-
DQ8 ~ DQ15
t
CRP
t
RSH
t
RCD
t
CAS
t
CRP
t
RWL
t
WP
t
CWL
t
DH
t
DH
DATA-IN
COLUMN
ADDRESS
t
OEH
t
OED
t
DS
t
DS
DATA-IN
t
CSH
t
CAH
background image
CMOS DRAM
K4F661611D,
K4F641611D
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDRESS
t
RAS
t
RC
t
RP
t
RAL
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
Don
t care
LOWER BYTE WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : D
OUT
= OPEN
Undefined
LCAS
V
IH
-
V
IL
-
t
RWL
V
IH
-
V
IL
-
DQ0 ~ DQ7
t
DS
V
IH
-
V
IL
-
DQ8 ~ DQ15
t
CRP
t
CSH
t
RSH
t
RCD
t
CAS
t
CRP
t
WP
t
CWL
t
DH
DATA-IN
t
CRP
t
RPC
t
OEH
t
OED
background image
CMOS DRAM
K4F661611D,
K4F641611D
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDRESS
t
RAS
t
RC
t
CRP
t
RP
t
CSH
t
RSH
t
RCD
t
CAS
t
RAL
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
CRP
Don
t care
UPPER BYTE WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : D
OUT
= OPEN
Undefined
LCAS
V
IH
-
V
IL
-
V
IH
-
V
IL
-
V
IH
-
V
IL
-
t
CRP
t
RWL
t
WP
t
CWL
t
DS
t
DH
DATA-IN
t
OEH
t
OED
DQ0 ~ DQ7
DQ8 ~ DQ15
t
RPC
background image
CMOS DRAM
K4F661611D,
K4F641611D
t
RWL
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDR
t
RAS
t
RWC
t
RP
t
RSH
t
RCD
t
CAS
t
CSH
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
CRP
Don
t care
WORD READ - MODIFY - WRITE CYCLE
Undefined
LCAS
V
IH
-
V
IL
-
V
I/OH
-
V
I/OL
-
DQ0 ~ DQ7
V
I/OH
-
V
I/OL
-
DQ8 ~ DQ15
t
WP
t
CWL
t
DS
t
DH
t
RSH
t
RCD
t
CAS
t
CRP
t
AWD
t
CWD
t
OEA
t
RWD
t
OED
t
OEZ
t
RAC
t
AA
t
OEZ
t
RAC
t
AA
t
DS
t
OED
t
DH
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
t
CAC
t
CLZ
t
CAC
t
CLZ
background image
CMOS DRAM
K4F661611D,
K4F641611D
t
RWL
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDR
t
RAS
t
RWC
t
RP
t
CSH
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
CRP
Don
t care
LOWER-BYTE READ - MODIFY - WRITE CYCLE
Undefined
LCAS
V
IH
-
V
IL
-
V
I/OH
-
V
I/OL
-
DQ0 ~ DQ7
V
I/OH
-
V
I/OL
-
DQ8 ~ DQ15
t
WP
t
CWL
t
DS
t
DH
t
RSH
t
RCD
t
CAS
t
CRP
t
AWD
t
CWD
t
OEA
t
RWD
t
OED
t
OEZ
t
RAC
t
AA
VALID
DATA-OUT
VALID
DATA-IN
t
RPC
t
CAC
t
CLZ
OPEN
background image
CMOS DRAM
K4F661611D,
K4F641611D
t
CRP
t
RWL
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDR
t
RAS
t
RWC
t
RP
t
RSH
t
RCD
t
CAS
t
CSH
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
CRP
Don
t care
UPPER-BYTE READ - MODIFY - WRITE CYCLE
Undefined
LCAS
V
IH
-
V
IL
-
V
I/OH
-
V
I/OL
-
DQ0 ~ DQ7
V
I/OH
-
V
I/OL
-
DQ8 ~ DQ15
t
WP
t
CWL
t
AWD
t
CWD
t
OEA
t
RWD
t
OEZ
t
RAC
t
AA
t
DS
t
OED
t
DH
VALID
DATA-OUT
VALID
DATA-IN
t
RPC
t
CAC
t
CLZ
OPEN
background image
CMOS DRAM
K4F661611D,
K4F641611D
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDR
t
RASP
t
RP
t
RCD
t
ASR
t
CRP
Don
t care
FAST PAGE MODE WORD READ CYCLE
Undefined
LCAS
V
IH
-
V
IL
-
V
OH
-
V
OL
-
DQ0 ~ DQ7
V
OH
-
V
OL
-
DQ8 ~ DQ15
t
OEZ
t
OFF
COLUMN
ADDRESS
t
CAS
t
CAS
t
CAS
t
CAS
t
CP
t
CP
t
CP
t
RPC
t
PC
t
PC
t
PC
t
RHCP
t
CSH
t
RCD
t
CRP
t
CAS
t
CAS
t
CAS
t
CAS
t
CP
t
CP
t
RPC
t
RAD
t
RAH
t
ASC
t
CAH
t
CAH
t
CAH
t
ASC
t
CAH
t
RCS
t
RCS
t
OEA
t
AA
t
RCS
t
RCH
t
RCH
t
RCS
t
RCH
t
RCH
t
RRH
t
ASC
COLUMN
ADDRESS
COLUMN
ADDR
VALID
DATA-OUT
t
OEZ
t
OFF
t
OEA
t
CPA
t
AA
t
CAC
t
OEA
t
CPA
t
AA
t
CAC
t
OEA
t
CPA
t
AA
t
CAC
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-OUT
t
OEZ
t
OFF
t
OEZ
t
OFF
t
OEZ
t
OFF
VALID
DATA-OUT
t
OEZ
t
OFF
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-OUT
t
OEZ
t
OFF
t
OEZ
t
OFF
t
CLZ
t
RAC
t
CAC
t
CAC
t
CLZ
t
RAC
t
ASC
t
CP
t
RAL
background image
CMOS DRAM
K4F661611D,
K4F641611D
t
CRP
t
CRP
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDR
t
RASP
t
RP
t
RCD
t
ASR
Don
t care
FAST PAGE MODE LOWER BYTE READ CYCLE
Undefined
LCAS
V
IH
-
V
IL
-
V
OH
-
V
OL
-
DQ0 ~ DQ7
V
OH
-
V
OL
-
DQ8 ~ DQ15
t
OEZ
t
OFF
COLUMN
ADDRESS
t
CAS
t
CAS
t
CAS
t
CAS
t
CP
t
CP
t
RPC
t
PC
t
PC
t
PC
t
RHCP
t
CSH
t
RAD
t
RAH
t
ASC
t
CAH
t
ASC
t
CAH
t
CAH
t
ASC
t
CAH
t
RCS
t
RCS
t
OEA
t
AA
t
RCS
t
RCH
t
RCH
t
RCS
t
RCH
t
RCH
t
RRH
t
ASC
COLUMN
ADDRESS
COLUMN
ADDR
VALID
DATA-OUT
t
OEZ
t
OFF
t
OEA
t
CPA
t
AA
t
CAC
t
OEA
t
CPA
t
AA
t
CAC
t
OEA
t
CPA
t
AA
t
CAC
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-OUT
t
OEZ
t
OFF
t
OEZ
t
OFF
t
CLZ
t
RAC
t
CAC
t
RPC
OPEN
t
RAL
t
CP
background image
CMOS DRAM
K4F661611D,
K4F641611D
t
CP
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDR
t
RASP
t
RP
t
RCD
t
ASR
t
CRP
Don
t care
FAST PAGE MODE UPPER BYTE READ CYCLE
Undefined
LCAS
V
IH
-
V
IL
-
V
OH
-
V
OL
-
DQ0 ~ DQ7
V
OH
-
V
OL
-
DQ8 ~ DQ15
COLUMN
ADDRESS
t
CAS
t
CAS
t
CAS
t
CAS
t
CP
t
CP
t
RPC
t
PC
t
PC
t
PC
t
RHCP
t
CSH
t
CRP
t
RPC
t
RAD
t
RAH
t
ASC
t
CAH
t
ASC
t
CAH
t
CAH
t
CAH
t
RCS
t
RCS
t
OEA
t
AA
t
RCS
t
RCH
t
RCH
t
RCS
t
RCH
t
RCH
t
RRH
t
ASC
COLUMN
ADDRESS
COLUMN
ADDR
t
OEA
t
CPA
t
OEA
t
CPA
t
OEA
t
CPA
t
OEZ
t
OFF
VALID
DATA-OUT
t
OEZ
t
OFF
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-OUT
t
OEZ
t
OFF
t
OEZ
t
OFF
t
CAC
t
CLZ
t
RAC
OPEN
t
AA
t
CAC
t
AA
t
CAC
t
AA
t
CAC
t
RAL
t
ASC
background image
CMOS DRAM
K4F661611D,
K4F641611D
t
ASC
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDR
t
RASP
t
RP
t
RCD
t
ASR
t
CRP
Don
t care
FAST PAGE MODE WORD WRITE CYCLE ( EARLY WRITE )
Undefined
LCAS
V
IH
-
V
IL
-
V
IH
-
V
IL
-
DQ0 ~ DQ7
V
IH
-
V
IL
-
DQ8 ~ DQ15
t
CRP
t
PC
t
PC
t
RHCP
t
RAD
t
RAH
t
CAH
t
CAH
t
CAH
t
ASC
VALID
DATA-IN
t
DS
COLUMN
ADDRESS
COLUMN
ADDRESS
t
CAS
t
CP
t
CAS
t
CP
t
CAS
t
RSH
t
RCD
t
CRP
t
PC
t
PC
t
CAS
t
CP
t
CAS
t
CP
t
CAS
t
RSH
t
CSH
t
ASC
t
WP
t
WCS
t
WCH
t
WP
t
WCS
t
WCH
t
WP
t
WCS
t
WCH
VALID
DATA-IN
VALID
DATA-IN
t
DH
t
DS
t
DH
t
DS
t
DH
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
t
DH
t
DH
t
DH
t
DS
t
DS
t
DS
NOTE : D
OUT
= OPEN
t
RAL
background image
CMOS DRAM
K4F661611D,
K4F641611D
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDR
t
RASP
t
RP
t
ASR
t
CRP
Don
t care
FAST PAGE MODE LOWER BYTE WRITE CYCLE ( EARLY WRITE )
Undefined
LCAS
V
IH
-
V
IL
-
V
IH
-
V
IL
-
DQ0 ~ DQ7
V
IH
-
V
IL
-
DQ8 ~ DQ15
t
RPC
t
RHCP
t
RAD
t
RAH
t
CAH
t
CAH
t
ASC
t
CAH
t
ASC
VALID
DATA-IN
t
DS
COLUMN
ADDRESS
COLUMN
ADDRESS
t
RCD
t
CRP
t
PC
t
PC
t
CAS
t
CP
t
CAS
t
CP
t
CAS
t
RSH
t
CSH
t
ASC
t
WP
t
WCS
t
WCH
t
WP
t
WCS
t
WCH
t
WP
t
WCS
t
WCH
VALID
DATA-IN
VALID
DATA-IN
t
DH
t
DS
t
DH
t
DS
t
DH
NOTE : D
OUT
= OPEN
t
RAL
background image
CMOS DRAM
K4F661611D,
K4F641611D
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
COLUMN
ADDRESS
ROW
ADDR.
t
RASP
t
RP
t
ASR
t
CRP
Don
t care
FAST PAGE MODE UPPER BYTE WRITE CYCLE ( EARLY WRITE )
Undefined
LCAS
V
IH
-
V
IL
-
V
IH
-
V
IL
-
DQ0 ~ DQ7
V
IH
-
V
IL
-
DQ8 ~ DQ15
t
RPC
t
RHCP
t
RAD
t
RAH
t
CAH
t
CAH
t
ASC
t
CAH
t
ASC
VALID
DATA-IN
t
DS
COLUMN
ADDRESS
COLUMN
ADDRESS
t
RCD
t
CRP
t
PC
t
PC
t
CAS
t
CP
t
CAS
t
CP
t
CAS
t
RSH
t
CSH
t
ASC
t
WP
t
WCS
t
WCH
t
WP
t
WCS
t
WCH
t
WP
t
WCS
t
WCH
VALID
DATA-IN
VALID
DATA-IN
t
DH
t
DS
t
DH
t
DS
t
DH
NOTE : D
OUT
= OPEN
t
RAL
background image
CMOS DRAM
K4F661611D,
K4F641611D
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
V
I/OH
-
V
I/OL
-
DQ0 ~ DQ7
ROW
ADDR
t
CSH
t
RASP
t
RP
t
ASR
Don
t care
FAST PAGE MODE WORD READ-MODIFY-WRITE CYCLE
Undefined
t
RCD
t
CP
t
RAD
t
CAH
t
WP
t
DH
COL.
ADDR
COL.
ADDR
t
CAS
t
CAS
t
CRP
t
ASC
t
CAH
t
RAL
t
RCS
t
CWL
t
CWD
t
AWD
t
RWD
t
CWD
t
AWD
t
CWL
t
AA
t
RAC
t
OEA
t
CLZ
t
CAC
t
OEZ
t
CPWD
t
OED
t
ASC
t
CLZ
t
OEA
t
CAC
t
AA
t
DH
t
OED
t
RWL
LCAS
V
IH
-
V
IL
-
t
RCD
t
CP
t
CAS
t
CAS
t
CRP
t
CRP
t
CRP
V
I/OH
-
V
I/OL
-
DQ8 ~ DQ15
VALID
DATA-OUT
t
DH
t
AA
t
RAC
t
CLZ
t
CAC
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
t
CLZ
t
CAC
t
AA
t
DH
t
OEZ
t
OED
t
DS
t
DS
t
DS
t
OEZ
t
OEZ
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
t
DS
t
PRWC
t
RSH
t
WP
t
RCS
t
RAH
t
OED
background image
CMOS DRAM
K4F661611D,
K4F641611D
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
V
I/OH
-
V
I/OL
-
DQ0 ~ DQ7
ROW
ADDR
t
CSH
t
RASP
t
RP
t
ASR
Don
t care
FAST PAGE MODE LOWER BYTE READ - MODIFY - WRITE CYCLE
Undefined
t
RAD
t
CAH
t
WP
t
DH
COL.
ADDR
COL.
ADDR
t
ASC
t
CAH
t
RAL
t
RCS
t
CWL
t
CWD
t
AWD
t
RWD
t
WP
t
CWD
t
AWD
t
CWL
t
AA
t
RAC
t
OEA
t
CLZ
t
CAC
t
OEZ
t
CPWD
t
OED
t
ASC
t
CLZ
t
OEA
t
CAC
t
AA
t
DH
t
OED
t
RWL
LCAS
V
IH
-
V
IL
-
t
RCD
t
CP
t
CAS
t
CAS
t
CRP
t
CRP
t
CRP
V
I/OH
-
V
I/OL
-
DQ8 ~ DQ15
t
DS
t
OEZ
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
t
DS
t
RPC
t
RSH
t
PRWC
OPEN
t
RCS
t
RAH
background image
CMOS DRAM
K4F661611D,
K4F641611D
RAS
V
IH
-
V
IL
-
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
V
I/OH
-
V
I/OL
-
DQ0 ~ DQ7
ROW
ADDR
t
CSH
t
RASP
t
RP
t
ASR
Don
t care
FAST PAGE MODE UPPER BYTE READ - MODIFY - WRITE CYCLE
Undefined
t
RAD
t
CAH
t
WP
t
DH
COL.
ADDR
COL.
ADDR
t
ASC
t
CAH
t
RAL
t
RCS
t
CWL
t
CWD
t
AWD
t
RWD
t
WP
t
CWD
t
AWD
t
CWL
t
AA
t
RAC
t
OEA
t
CLZ
t
CAC
t
OEZ
t
CPWD
t
OED
t
ASC
t
CLZ
t
OEA
t
CAC
t
AA
t
DH
t
OED
t
RWL
V
IH
-
V
IL
-
t
RCD
t
CP
t
CAS
t
CAS
t
CRP
t
CRP
t
CRP
V
I/OH
-
V
I/OL
-
DQ8 ~ DQ15
t
DS
t
OEZ
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
t
DS
t
RPC
t
RSH
t
PRWC
OPEN
UCAS
LCAS
t
RCS
t
RAH
background image
CMOS DRAM
K4F661611D,
K4F641611D
t
CSR
OPEN
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
ROW
ADDR
t
RC
t
RP
t
ASR
t
CRP
RAS - ONLY REFRESH CYCLE
LCAS
V
IH
-
V
IL
-
t
RAS
t
RAH
NOTE : W, OE , D
IN
= Don
t care
D
OUT
= OPEN
t
RPC
t
CRP
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE , A = Don
t care
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
t
RC
t
RP
LCAS
V
IH
-
V
IL
-
t
RAS
t
RPC
t
CP
t
CRP
t
CHR
t
CP
t
CSR
t
CHR
t
OFF
OPEN
V
OH
-
V
OL
-
DQ0 ~ DQ7
V
OH
-
V
OL
-
DQ8 ~ DQ15
t
WRP
t
WRH
W
V
IH
-
V
IL
-
Don
t care
t
RP
Undefined
background image
CMOS DRAM
K4F661611D,
K4F641611D
t
OEZ
DATA-IN
DATA-OUT
t
RP
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
ROW
ADDRESS
t
RAS
t
RC
t
CHR
t
RCD
t
RSH
t
RAD
t
ASR
t
RAH
t
ASC
t
CRP
Don
t care
HIDDEN REFRESH CYCLE ( READ )
Undefined
LCAS
V
IH
-
V
IL
-
V
OH
-
V
OL
-
DQ0 ~ DQ7
V
OH
-
V
OL
-
DQ8 ~ DQ15
t
RSH
t
RCD
t
CRP
t
WRH
COLUMN
ADDRESS
t
OEA
t
RAS
t
RC
t
CHR
t
CAH
t
RCS
t
AA
t
RAC
t
CLZ
t
CAC
DATA-OUT
t
OFF
OPEN
OPEN
t
RP
t
RAL
background image
CMOS DRAM
K4F661611D,
K4F641611D
t
WCS
t
RP
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
ROW
ADDRESS
t
RAS
t
RC
t
CHR
t
RCD
t
RSH
t
RAD
t
ASR
t
RAH
t
ASC
t
CRP
Don
t care
HIDDEN REFRESH CYCLE ( WRITE )
Undefined
LCAS
V
IH
-
V
IL
-
V
IH
-
V
IL
-
DQ0 ~ DQ7
V
IH
-
V
IL
-
DQ8 ~ DQ15
t
RSH
t
RCD
t
CRP
t
WRH
COLUMN
ADDRESS
t
RAS
t
RC
t
CHR
t
CAH
t
WRP
t
DS
NOTE : D
OUT
= OPEN
t
WP
t
WCH
DATA-IN
t
DH
t
DS
DATA-IN
t
DH
t
RP
t
RAL
background image
CMOS DRAM
K4F661611D,
K4F641611D
t
CSR
OPEN
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE , A = Don
t care
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
t
RPS
LCAS
V
IH
-
V
IL
-
t
RASS
t
RPC
t
CP
t
RPC
t
CSR
t
OFF
OPEN
V
OH
-
V
OL
-
DQ0 ~ DQ7
V
OH
-
V
OL
-
DQ8 ~ DQ15
t
WRP
t
WRH
W
V
IH
-
V
IL
-
t
CHS
t
CP
t
CHS
TEST MODE IN CYCLE
NOTE : OE , A = Don
t care
RAS
V
IH
-
V
IL
-
UCAS
V
IH
-
V
IL
-
t
RP
LCAS
V
IH
-
V
IL
-
t
RC
t
RPC
t
CP
t
CRP
t
CSR
OPEN
V
OH
-
V
OL
-
DQ0 ~ DQ15
t
CHR
t
CP
t
CSR
t
CHR
t
RP
t
RAS
t
RP
Don
t care
Undefined
t
WTS
t
WTH
W
V
IH
-
V
IL
-
t
OFF
background image
CMOS DRAM
K4F661611D,
K4F641611D
50 TSOP(II) 400mil
Units : Inches (millimeters)
MAX
0.047 (1.20)
MIN
0.002 (0.05)
0.018 (0.45)
0.010 (0.25)
0.0315 (0.80)
0.034 (0.875)
0.821 (20.85)
0.829 (21.05)
0.841 (21.35)
MAX
0.010 (0.25)
0.004 (0.10)
0
.
4
0
0

(
1
0
.
1
6
)
0
.
4
7
1

(
1
1
.
9
6
)
0
.
4
5
5

(
1
1
.
5
6
)
0~8
0.030 (0.75)
0.018 (0.45)
TYP
0.010 (0.25)
O
PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(II)