CMOS DRAM
K4F660412C,K4F640412C
This is a family of 16,777,216 x 4 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory
cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption(Normal or Low power)
are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities.
Furthermore, Self-refresh operation is available in L-version. This 16Mx4 Fast Page Mode DRAM family is fabricated using Samsung
s
advanced CMOS process to realize high band-width, low power consumption and high reliability.
Fast Page Mode operation
CAS-before-RAS refresh capability
RAS-only and Hidden refresh capability
Self-refresh capability (L-ver only)
Fast parallel test mode capability
LVTTL(3.3V) compatible inputs and outputs
Early Write or output enable controlled write
JEDEC Standard pinout
Available in Plastic SOJ and TSOP(II) packages
+3.3V
0.3V power supply
Control
Clocks
RAS
CAS
W
Vcc
Vss
A0~A12
(A0~A11)*1
A0~A10
(A0~A11)*1
Memory Array
16,777,216 x 4
Cells
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
16M x 4bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
Note) *1 : 4K Refresh
Refresh Cycles
Part
NO.
Refresh
cycle
Refresh time
Normal
L-ver
K4F660412C*
8K
64ms
128ms
K4F640412C
4K
Performance Range
Speed
t
RAC
t
CAC
t
RC
t
PC
-45
45ns
12ns
80ns
31ns
-50
50ns
13ns
90ns
35ns
-60
60ns
15ns
110ns
40ns
Active Power Dissipation
Speed
8K
4K
-45
324
432
-50
288
396
-60
252
360
Unit : mW
S
e
n
s
e
A
m
p
s
&
I
/
O
Data out
Buffer
DQ0
to
DQ3
Data in
Buffer
* Access mode & RAS only refresh mode
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)
CAS-before-RAS & Hidden refresh mode
: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)
Row Decoder
Column Decoder
VBB Generator
Refresh Timer
Refresh Control
Refresh Counter
Row Address Buffer
Col. Address Buffer
OE
Part Identification
- K4F660412C-JC/L(3.3V, 8K Ref., SOJ)
- K4F640412C-JC/L(3.3V, 4K Ref., SOJ)
- K4F660412C-TC/L(3.3V, 8K Ref., TSOP)
- K4F640412C-TC/L(3.3V, 4K Ref., TSOP)
FEATURES
CMOS DRAM
K4F660412C,K4F640412C
V
CC
DQ0
DQ1
N.C
N.C
N.C
N.C
W
RAS
A0
A1
A2
A3
A4
A5
V
CC
V
SS
DQ3
DQ2
N.C
N.C
N.C
CAS
OE
A12(N.C)*
A11
A10
A9
A8
A7
A6
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PIN CONFIGURATION (Top Views)
* (N.C) : N.C for 4K Refresh product
Pin Name
Pin Function
A0 - A12
Address Inputs(8K Product)
A0 - A11
Address Inputs(4K Product)
DQ0 - 3
Data In/Out
V
SS
Ground
RAS
Row Address Strobe
CAS
Column Address Strobe
W
Read/Write Input
OE
Data Output Enable
V
CC
Power(+3.3V)
N.C
No Connection
V
CC
DQ0
DQ1
N.C
N.C
N.C
N.C
W
RAS
A0
A1
A2
A3
A4
A5
V
CC
V
SS
DQ3
DQ2
N.C
N.C
N.C
CAS
OE
A12(N.C)*
A11
A10
A9
A8
A7
A6
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
(T : 400mil TSOP(II))
(J : 400mil SOJ)
K4F660412C-J
K4F640412C-J
K4F660412C-T
K4F640412C-T
CMOS DRAM
K4F660412C,K4F640412C
ABSOLUTE MAXIMUM RATINGS
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Parameter
Symbol
Rating
Units
Voltage on any pin relative to V
SS
V
IN,
V
OUT
-0.5 to +4.6
V
Voltage on V
CC
supply relative to V
SS
V
CC
-0.5 to +4.6
V
Storage Temperature
Tstg
-55 to +150
C
Power Dissipation
P
D
1
W
Short Circuit Output Current
I
OS
Address
50
mA
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to Vss, T
A
= 0 to 70
C)
*1 : Vcc+1.3V at pulse width
15ns which is measured at V
CC
*2 : -1.3 at pulse width
15ns which is measured at V
SS
Parameter
Symbol
Min
Typ
Max
Units
Supply Voltage
V
CC
3.0
3.3
3.6
V
Ground
V
SS
0
0
0
V
Input High Voltage
V
IH
2.0
-
Vcc+0.3
*1
V
Input Low Voltage
V
IL
-0.3
*2
-
0.8
V
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter
Symbol
Min
Max
Units
Input Leakage Current (Any input 0
V
IN
V
CC
+0.3V,
all other pins not under test=0 Volt)
I
I(L)
-5
5
uA
Output Leakage Current
(Data out is disabled, 0V
V
OUT
V
CC
)
I
O(L)
-5
5
uA
Output High Voltage Level(I
OH
=-2mA)
V
OH
2.4
-
V
Output Low Voltage Level(I
OL
=2mA)
V
OL
-
0.4
V
CMOS DRAM
K4F660412C,K4F640412C
*Note :
I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
, I
CC3
and I
CC6,
address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one fast page mode cycle time,
t
PC
.
DC AND OPERATING CHARACTERISTICS
(Continued)
I
CC1
* : Operating Current (RAS and CAS, Address cycling @
t
RC
=min.)
I
CC2
: Standby Current (RAS=CAS=W=V
IH
)
I
CC3
* : RAS-only Refresh Current (CAS=V
IH
, RAS, Address cycling @
t
RC
=min.)
I
CC4
* : Fast Page Mode Current (RAS=V
IL
, CAS, Address cycling @
t
PC
=min.)
I
CC5
: Standby Current (RAS=CAS=W=V
CC
-0.2V)
I
CC6
* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @
t
RC
=min)
I
CC7
: Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(V
IH
)=V
CC
-0.2V, Input low voltage(V
IL
)=0.2V, CAS=CAS-before-RAS cycling or 0.2V,
W, OE=V
IH
, Address=Don
t care, DQ=Open, T
RC
=31.25us
I
CCS
: Self Refresh Current
RAS=CAS=0.2V, W=OE=A0 ~ A12(A11)=V
CC
-0.2V or 0.2V, DQ0 ~ DQ3=V
CC
-0.2V, 0.2V or Open
Symbol
Power
Speed
Max
Units
K4F660412C
K4F640412C
I
CC1
Don
t care
-45
-50
-60
90
80
70
120
110
100
mA
mA
mA
I
CC2
Normal
L
Don
t care
1
1
1
1
mA
mA
I
CC3
Don
t care
-45
-50
-60
90
80
70
120
110
100
mA
mA
mA
I
CC4
Don
t care
-45
-50
-60
70
60
50
70
60
50
mA
mA
mA
I
CC5
Normal
L
Don
t care
0.5
200
0.5
200
mA
uA
I
CC6
Don
t care
-45
-50
-60
120
110
100
120
110
100
mA
mA
mA
I
CC7
L
Don
t care
350
350
uA
I
CCS
L
Don
t care
350
350
uA
CMOS DRAM
K4F660412C,K4F640412C
CAPACITANCE
(T
A
=25
C, V
CC
=3.3V, f=1MHz)
Parameter
Symbol
Min
Max
Units
Input capacitance [A0 ~ A12]
C
IN1
-
5
pF
Input capacitance [RAS, CAS, W, OE]
C
IN2
-
7
pF
Output capacitance [DQ0 - DQ3]
C
DQ
-
7
pF
Test condition : V
CC
=3.3V
0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V
Parameter
Symbol
-45
-50
-60
Units
Note
Min
Max
Min
Max
Min
Max
Random read or write cycle time
t
RC
80
90
110
ns
Read-modify-write cycle time
t
RWC
115
133
153
ns
Access time from RAS
t
RAC
45
50
60
ns
3,4,10
Access time from CAS
t
CAC
12
13
15
ns
3,4,5
Access time from column address
t
AA
23
25
30
ns
3,10
CAS to output in Low-Z
t
CLZ
0
0
0
ns
3
Output buffer turn-off delay
t
OFF
0
13
0
13
0
13
ns
6
Transition time (rise and fall)
t
T
1
50
1
50
1
50
ns
2
RAS precharge time
t
RP
25
30
40
ns
RAS pulse width
t
RAS
45
10K
50
10K
60
10K
ns
RAS hold time
t
RSH
12
13
15
ns
CAS hold time
t
CSH
45
50
60
ns
CAS pulse width
t
CAS
12
10K
13
10K
15
10K
ns
RAS to CAS delay time
t
RCD
18
33
20
37
20
45
ns
4
RAS to column address delay time
t
RAD
13
22
15
25
15
30
ns
10
CAS to RAS precharge time
t
CRP
5
5
5
ns
Row address set-up time
t
ASR
0
0
0
ns
Row address hold time
t
RAH
8
10
10
ns
Column address set-up time
t
ASC
0
0
0
ns
Column address hold time
t
CAH
8
10
10
ns
Column address to RAS lead time
t
RAL
23
25
30
ns
Read command set-up time
t
RCS
0
0
0
ns
Read command hold time referenced to CAS
t
RCH
0
0
0
ns
8
Read command hold time referenced to RAS
t
RRH
0
0
0
ns
8
Write command hold time
t
WCH
8
10
10
ns
Write command pulse width
t
WP
8
10
10
ns
Write command to RAS lead time
t
RWL
13
15
15
ns
Write command to CAS lead time
t
CWL
12
13
15
ns
Data set-up time
t
DS
0
0
0
ns
9
Data hold time
t
DH
10
10
10
ns
9
AC CHARACTERISTICS
(0
C
T
A
70
C, See note 2)
CMOS DRAM
K4F660412C,K4F640412C
AC CHARACTERISTICS
(Continued)
Parameter
Symbol
-45
-50
-60
Units
Note
Min
Max
Min
Max
Min
Max
Refresh period (Normal)
t
REF
64
64
64
ms
Refresh period (L-ver)
t
REF
128
128
128
ms
Write command set-up time
t
WCS
0
0
0
ns
7
CAS to W delay time
t
CWD
32
36
38
ns
7
RAS to W delay time
t
RWD
67
73
83
ns
7
Column address to W delay time
t
AWD
43
48
53
ns
7
CAS precharge W delay time
t
CPWD
48
53
60
ns
CAS set-up time (CAS -before-RAS refresh)
t
CSR
5
5
5
ns
CAS hold time (CAS -before-RAS refresh)
t
CHR
10
10
10
ns
RAS to CAS precharge time
t
RPC
5
5
5
ns
Access time from CAS precharge
t
CPA
26
30
35
ns
3
Fast Page mode cycle time
t
PC
31
35
40
ns
Fast Page mode read-modify-write cycle time
t
PRWC
70
76
85
ns
CAS precharge time (Fast page cycle)
t
CP
9
10
10
ns
RAS pulse width (Fast page cycle)
t
RASP
45
200K
50
200K
60
200K
ns
RAS hold time from CAS precharge
t
RHCP
28
30
35
ns
OE access time
t
OEA
12
13
15
ns
3
OE to data delay
t
OED
12
13
13
ns
Output buffer turn off delay time from OE
t
OEZ
0
13
0
13
0
13
ns
6
OE command hold time
t
OEH
12
13
15
ns
Write command set-up time (Test mode in)
t
WTS
10
10
10
ns
11
Write command hold time (Test mode in)
t
WTH
15
15
15
ns
11
W to RAS precharge time (C-B-R refresh)
t
WRP
10
10
10
ns
W to RAS hold time (C-B-R refresh)
t
WRH
10
10
10
ns
RAS pulse width (C-B-R self refresh)
t
RASS
100
100
100
us
13,14,15
RAS precharge time (C-B-R self refresh)
t
RPS
80
90
110
ns
13,14,15
CAS hold time (C-B-R self refresh)
t
CHS
-50
-50
-50
ns
13,14,15
CMOS DRAM
K4F660412C,K4F640412C
TEST MODE CYCLE
Parameter
Symbol
-45
-50
-60
Units
Note
Min
Max
Min
Max
Min
Max
Random read or write cycle time
t
RC
85
95
115
ns
Read-modify-write cycle time
t
RWC
120
138
160
ns
Access time from RAS
t
RAC
50
55
65
ns
3,4,10,12
Access time from CAS
t
CAC
17
18
20
ns
3,4,5,12
Access time from column address
t
AA
28
30
35
ns
3,10,12
RAS pulse width
t
RAS
50
10K
55
10K
65
10K
ns
CAS pulse width
t
CAS
17
10K
18
10K
20
10K
ns
RAS hold time
t
RSH
17
18
20
ns
CAS hold time
t
CSH
50
55
65
ns
Column Address to RAS lead time
t
RAL
28
30
35
ns
CAS to W delay time
t
CWD
37
41
43
ns
7
RAS to W delay time
t
RWD
72
78
88
ns
7
Column Address to W delay time
t
AWD
48
53
58
ns
7
Fast Page mode cycle time
t
PC
36
40
45
ns
Fast Page mode read-modify-write cycle time
t
PRWC
75
81
90
ns
RAS pulse width (Fast Page cycle)
t
RASP
50
200K
55
200K
65
200K
ns
Access time from CAS precharge
t
CPA
31
35
40
ns
3
OE access time
t
OEA
17
18
20
ns
3
OE to data delay
t
OED
17
18
18
ns
OE command hold time
t
OEH
17
18
20
ns
( Note 11 )
CMOS DRAM
K4F660412C,K4F640412C
NOTES
An initial pause of 200us is required after power-up followed by any 8 ROR or CBR cycles before proper device operation is
achieved.
V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals. Transition times are measured between
V
IH
(min) and V
IL
(max) and are assumed to be 5ns for all inputs.
Measured with a load equivalent to 1 TTL load and 100pF.
Operation within the
t
RCD
(max) limit insures that
t
RAC
(max) can be met.
t
RCD
(max) is specified as a reference point only.
If
t
RCD
is greater than the specified
t
RCD
(max) limit, then access time is controlled exclusively by
t
CAC
.
Assumes that
t
RCD
t
RCD
(max).
t
OFF
(min)and
t
OEZ
(max) define the time at which the output achieves the open circuit condition and are not referenced V
oh
or V
ol
.
t
WCS
,
t
RWD
,
t
CWD
and
t
AWD
are non restrictive operating parameters. They are included in the data sheet as electric charac-
teristics only. If
t
WCS
t
WCS
(min), the cycles is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If
t
CWD
t
CWD
(min),
t
RWD
t
RWD
(min) and
t
AWD
t
AWD
(min), then the cycle is a read-modify-write cycle
and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the
condition of the data out is indeterminate.
Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
These parameters are referenced to the CAS falling edge in early write cycles and to the W falling edge in read-modify-write
cycles.
Operation within the
t
RAD
(max) limit insures that
t
RAC
(max) can be met.
t
RAD
(max) is specified as a reference point only. If
t
RAD
is greater than the specified
t
RAD
(max) limit, then access time is controlled by
t
AA
.
These specifications are applied in the test mode.
In test mode read cycle, the value of
t
RAC
,
t
AA
,
t
CAC
is delayed by 2ns to 5ns for the specified values. These parameters
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
If
t
RASS
100us, then RAS precharge time must use
t
RPS
instead of
t
RP
.
For RAS-only-Refresh and Burst CAS-before-RAS refresh, 4096 cycles(4K/8K) of burst refresh must be executed within
64ms before and after self refresh, in order to meet refresh specification.
For distributed CAS-before-RAS with 15.6us interval, CBR refresh should be executed with in 15.6us immediately before
and after self refresh in order to meet refresh specification.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
1.
2.
3.
4.
15.
CMOS DRAM
K4F660412C,K4F640412C
t
CRP
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
V
OH
-
V
OL
-
DQ0 ~ DQ3(7)
READ CYCLE
COLUMN
ADDRESS
ROW
ADDRESS
t
RAS
t
RC
t
CRP
t
RP
t
CSH
t
RSH
t
RCD
t
CAS
t
RAL
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
AA
t
OEA
t
CAC
t
CLZ
t
RAC
OPEN
DATA-OUT
t
OEZ
t
RRH
t
RCH
Don
t care
Undefined
t
RCS
t
OFF
CMOS DRAM
K4F660412C,K4F640412C
t
WCS
WRITE CYCLE ( EARLY WRITE )
NOTE : D
OUT
= OPEN
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
V
IH
-
V
IL
-
DQ0 ~ DQ3(7)
COLUMN
ADDRESS
ROW
ADDRESS
t
RAS
t
RC
t
CRP
t
RP
t
CSH
t
RSH
t
RCD
t
CAS
t
RAL
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
CRP
t
WP
t
DS
t
DH
t
WCH
t
CWL
t
RWL
Don
t care
DATA-IN
Undefined
CMOS DRAM
K4F660412C,K4F640412C
t
OED
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
V
IH
-
V
IL
-
DQ0 ~ DQ3(7)
COLUMN
ADDRESS
ROW
ADDRESS
t
RAS
t
RC
t
CRP
t
RP
t
CSH
t
RSH
t
RCD
t
CAS
t
RAL
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
CRP
DATA-IN
t
WP
Don
t care
WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : D
OUT
= OPEN
t
CWL
t
RWL
t
DS
t
DH
t
OEH
Undefined
CMOS DRAM
K4F660412C,K4F640412C
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
V
I/OH
-
V
I/OL
-
DQ0 ~ DQ3(7)
ROW
ADDR
t
RAS
t
RWC
t
RP
t
RSH
t
RCD
t
CAS
t
CSH
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
CRP
VALID
t
WP
Don
t care
READ - MODIFY - WRTIE CYCLE
t
RWL
t
CWL
t
OEZ
t
OEA
t
OED
t
AWD
t
CWD
t
RWD
DATA-OUT
Undefined
VALID
DATA-IN
t
RAC
t
AA
t
CAC
t
CLZ
t
DS
t
DH
COLUMN
ADDRESS
CMOS DRAM
K4F660412C,K4F640412C
t
RCH
t
OEZ
t
CLZ
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
V
OH
-
V
OL
-
DQ0 ~ DQ3(7)
COLUMN
ADDRESS
ROW
ADDR
t
RHCP
t
RASP
t
CAS
t
ASC
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
CRP
VALID
Don
t care
FAST PAGE READ CYCLE
t
OEZ
t
RRH
DATA-OUT
Undefined
VALID
DATA-OUT
COLUMN
ADDRESS
COLUMN
ADDRESS
t
RSH
t
CAS
t
RCD
t
PC
t
CSH
t
CAH
t
ASC
t
CAH
t
RCH
t
RCS
t
RCS
t
RCS
t
OEA
t
CAC
t
OEA
t
CAC
t
OEA
t
CAC
VALID
DATA-OUT
t
CLZ
t
OFF
t
AA
t
OFF
t
AA
t
CLZ
t
OFF
t
OEZ
t
RAC
t
AA
t
CP
t
CAS
t
RP
t
CP
t
RAL
CMOS DRAM
K4F660412C,K4F640412C
t
ASC
t
CAH
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
V
IH
-
V
IL
-
DQ0 ~ DQ3(7)
COLUMN
ADDRESS
ROW
ADDR
t
RHCP
t
RASP
t
CAS
t
RAD
t
ASR
t
RAH
t
ASC
t
CRP
VALID
Don
t care
FAST PAGE WRITE CYCLE ( EARLY WRITE )
DATA-IN
Undefined
VALID
DATA-IN
t
DS
NOTE : D
OUT
= OPEN
COLUMN
ADDRESS
COLUMN
ADDRESS
t
RSH
t
CAS
t
RCD
t
PC
t
CSH
t
CAH
t
CAH
t
WCS
t
WCH
t
WCS
VALID
DATA-IN
t
WP
t
CWL
t
WP
t
WCH
t
WP
t
WCS
t
WCH
t
CWL
t
RWL
t
CWL
t
DH
t
DS
t
DH
t
DS
t
DH
t
RP
t
CP
t
CP
t
CAS
t
PC
t
RAL
t
ASC
CMOS DRAM
K4F660412C,K4F640412C
t
CAC
t
ASC
t
ASC
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
V
I/OH
-
V
I/OL
-
DQ0 ~ DQ3(7)
ROW
ADDR
t
CSH
t
RASP
t
ASR
VALID
Don
t care
FAST PAGE READ - MODIFY - WRITE CYCLE
DATA-OUT
Undefined
t
RCD
t
CP
t
RAD
t
CAH
t
WP
t
DH
COL.
ADDR
COL.
ADDR
t
CAS
t
CAS
t
CRP
t
CAH
t
RAL
t
PRWC
t
RCS
t
CWL
t
CWD
t
AWD
t
RWD
t
WP
t
CWD
t
AWD
t
CWL
t
AA
t
RAC
t
OEA
t
CLZ
t
CAC
t
OEZ
t
CPWD
t
OED
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
t
CLZ
t
DS
t
OEA
t
AA
t
DH
t
DS
t
OEZ
t
OED
t
RWL
t
RP
t
RSH
t
RAH
CMOS DRAM
K4F660412C,K4F640412C
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
ROW
ADDR
t
RAS
t
RC
t
RP
t
ASR
t
RAH
t
CRP
Don
t care
RAS - ONLY REFRESH CYCLE
Undefined
NOTE : W, OE, D
IN
= Don
t care
D
OUT
= OPEN
t
RPC
t
CRP
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE, A = Don
t care
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
t
RAS
t
RC
t
RP
t
WRP
t
RPC
t
RP
t
CP
t
CHR
t
CSR
W
V
IH
-
V
IL
-
t
WRH
t
OFF
t
RPC
V
OH
-
V
OL
-
DQ0 ~ DQ3(7)
OPEN
CMOS DRAM
K4F660412C,K4F640412C
t
WRH
t
OFF
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
V
OH
-
V
OL
-
DQ0 ~ DQ3(7)
HIDDEN REFRESH CYCLE ( READ )
COLUMN
ADDRESS
ROW
ADDRESS
t
RAS
t
RC
t
CHR
t
RCD
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
CRP
t
RCS
t
AA
t
OEA
t
CAC
t
CLZ
t
RAC
OPEN
Don
t care
t
RSH
t
OEZ
Undefined
t
RC
DATA-OUT
t
RP
t
RP
t
RAS
t
RAL
CMOS DRAM
K4F660412C,K4F640412C
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
A
V
IH
-
V
IL
-
W
V
IH
-
V
IL
-
OE
V
IH
-
V
IL
-
V
IH
-
V
IL
-
DQ0 ~ DQ3(7)
HIDDEN REFRESH CYCLE ( WRITE )
COLUMN
ADDRESS
ROW
ADDRESS
t
RAS
t
RC
t
CHR
t
RCD
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
CRP
Don
t care
t
RSH
DATA-IN
t
WRP
t
WRH
Undefined
t
RC
NOTE : D
OUT
= OPEN
t
WCH
t
WP
t
DH
t
RP
t
RP
t
RAS
t
DS
t
WCS
t
RAL
CMOS DRAM
K4F660412C,K4F640412C
Don
t care
Undefined
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE, A = Don
t care
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
t
RASS
t
RPS
t
RPC
t
WRP
t
CHS
t
RP
t
CP
t
CSR
W
V
IH
-
V
IL
-
t
WRH
t
OFF
t
RPC
OPEN
V
OH
-
V
OL
-
DQ0 ~ DQ3(7)
TEST MODE IN CYCLE
NOTE : OE, A = Don
t care
RAS
V
IH
-
V
IL
-
CAS
V
IH
-
V
IL
-
t
RAS
t
RC
t
RP
t
RPC
t
WTS
t
RPC
t
RP
t
CP
t
CHR
t
CSR
W
V
IH
-
V
IL
-
t
WTH
t
OFF
OPEN
V
OH
-
V
OL
-
DQ0 ~ DQ3(7)
CMOS DRAM
K4F660412C,K4F640412C
32 SOJ
400mil
0
.
4
0
0
(
1
0
.
1
6
)
0
.
4
3
5
(
1
1
.
0
6
)
0
.
4
4
5
(
1
1
.
3
0
)
0.830 (21.08)
0.820 (20.84)
MAX
0.841 (21.36)
M
A
X
0
.
1
4
8
(
3
.
7
6
)
0.032 (0.81)
0.026 (0.66)
0.021 (0.53)
0.015 (0.38)
0.027 (0.69)
0.012 (0.30)
0.006 (0.15)
0
.
3
6
0
(
9
.
1
5
)
0
.
3
8
0
(
9
.
6
5
)
MIN
#32
#1
0.0375 (0.95)
0.050 (1.27)
Units : Inches (millimeters)
PACKAGE DIMENSION
32 TSOP(II)
400mil
0
.
4
5
5
(
1
1
.
5
6
)
0
.
4
7
1
(
1
1
.
9
6
)
0.829 (21.05)
0.821 (20.85)
MAX
0.841 (21.35)
0.037 (0.95)
0.050 (1.27)
Units : Inches (millimeters)
0.047 (1.20)
MIN
0.002 (0.05)
0.020 (0.50)
0.012 (0.30)
MAX
0.010 (0.25)
0.004 (0.10)
0
.
4
0
0
(
1
0
.
1
6
)
0~8
0.030 (0.75)
0.018 (0.45)
TYP
0.010 (0.25)
O
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