DRAM MODULE
M372V320(8)0DT1-C
REV. 0.1 Oct. 2000
PERFORMANCE RANGE
Speed
t
RAC
t
CAC
t
RC
t
PC
-C50
50ns
18ns
90ns
35ns
-C60
60ns
20ns
110ns
40ns
M372V320(8)0DT1-C Fast Page Mode
32M x 72 DRAM DIMM with ECC Using 16Mx4, 4K & 8K Refresh, 3.3V
The Samsung M372V320(8)0DT1-C is a 32Mx72bits Dynamic
RAM high density memory module. The Samsung
M372V320(8)0DT1-C consists of thirty-six CMOS 16Mx4bits
DRAMs in TSOP 400mil packages and two 16 bits driver IC in
TSSOP package mounted on a 168-pin glass-epoxy sub-
strate. A 0.1 or 0.22uF decoupling capacitor is mounted on
the printed circuit board for each DRAM. The
M372V320(8)0DT1-C is a Dual In-line Memory Module and is
intended for mounting into 168 pin edge connector sockets.
GENERAL DESCRIPTION
PD Note :PD & ID Terminals must each be pulled up through a register to V
CC
at the next higher
level assembly. PDs will be either open (NC) or driven to V
SS
via on-board buffer circuits.
ID Note : IDs will be either open (NC) or connected directly to V
SS
without a buffer.
Part Identification
Fast Page Mode Operation
CAS-before-RAS Refresh capability
RAS-only and Hidden refresh capability
LVTTL compatible inputs and outputs
Single 3.3V
0.3V power supply
JEDEC standard pinout & Buffered PDpin
Buffered input except RAS and DQ
PCB : Height(2100mil), double sided component
Part number
PKG
Ref.
CBR Ref.
ROR Ref.
M372V3200DT1-C
TSOP
4K
4K/64ms
M372V3280DT1-C
TSOP
8K
4K/64ms
8K/64ms
PIN NAMES
Pins marked
*
are not used in this module.
Pin Names
Function
A0, B0, A1 - A11
Address Input(4K ref)
A0, B0, A1 - A12
Address Input(8K ref)
DQ0 - DQ71
Data In/Out
W0, W2
Read/Write Enable
OE0, OE2
Output Enable
RAS0 - RAS3
Row Address Strobe
CAS0, 1,4,5
Column Address Strobe
V
CC
Power(+3.3V)
V
SS
Ground
NC
No Connection
PDE
Presence Detect Enable
PD1 - 8
Presence Detect
ID0 - 1
ID bit
RSVD
Reserved Use
RFU
Reserved for Future Use
PD & ID Table
PD : 0 for Vol of Drive IC & 1 for N.C
ID : 0 for Vss & 1 for N.C
Pin
50NS
60NS
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
1
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
ID0
ID1
0
0
0
0
PIN CONFIGURATIONS
NOTE : A12 is used for only M372V3280DT1-C (8K Ref.)
Pin
Front
Pin
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V
SS
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
CC
DQ14
DQ15
DQ16
DQ17
V
SS
RSVD
RSVD
V
CC
W0
CAS0
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
*CAS2
RAS0
OE0
V
SS
A0
A2
A4
A6
A8
A10
A12
V
CC
RFU
RFU
V
SS
OE2
RAS2
CAS4
*CAS6
W2
V
CC
RSVD
RSVD
DQ18
DQ19
V
SS
DQ20
DQ21
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
DQ22
DQ23
V
CC
DQ24
RFU
RFU
RFU
RFU
DQ25
DQ26
DQ27
V
SS
DQ28
DQ29
DQ30
DQ31
V
CC
DQ32
DQ33
DQ34
DQ35
V
SS
PD1
PD3
PD5
PD7
ID0
V
CC
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
V
SS
DQ36
DQ37
DQ38
DQ39
V
CC
DQ40
DQ41
DQ42
DQ43
DQ44
V
SS
DQ45
DQ46
DQ47
DQ48
DQ49
V
CC
DQ50
DQ51
DQ52
DQ53
V
SS
RSVD
RSVD
V
CC
RFU
CAS1
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
*CAS3
RAS1
RFU
V
SS
A1
A3
A5
A7
A9
A11
*A13
V
CC
RFU
B0
V
SS
RFU
RAS3
CAS5
*CAS7
PDE
V
CC
RSVD
RSVD
DQ54
DQ55
V
SS
DQ56
DQ57
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
DQ58
DQ59
V
CC
DQ60
RFU
RFU
RFU
RFU
DQ61
DQ62
DQ63
V
SS
DQ64
DQ65
DQ66
DQ67
V
CC
DQ68
DQ69
DQ70
DQ71
V
SS
PD2
PD4
PD6
PD8
ID1
V
CC
FEATURES
DRAM MODULE
M372V320(8)0DT1-C
REV. 0.1 Oct. 2000
FUNCTIONAL BLOCK DIAGRAM
Vcc
Vss
0.1 or 0.22uF Capacitor
under each DRAM
To all DRAMs
RAS0
W0
OE0
A0
DQ0
DQ1
DQ2
DQ3
U0
CAS0
A1-A11(A12)
DQ0
DQ1
DQ2
DQ3
U1
DQ0
DQ1
DQ2
DQ3
U2
DQ0
DQ1
DQ2
DQ3
U3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
U5
NOTE : A12 is used for only M372V3280DT1(8K Ref.)
A0
B0
A1-A11(A12)
W0, OE0
W2, OE2
U0-U8, U18-U26
U9-U17, U27-U35
U0-U35
DQ0
DQ1
DQ2
DQ3
U6
DQ0
DQ1
DQ2
DQ3
U7
U0-U8, U18-U26
U9-U17, U27-U35
DQ0
DQ1
DQ2
DQ3
U8
DQ0
DQ1
DQ2
DQ3
U18
DQ0
DQ1
DQ2
DQ3
U19
DQ0
DQ1
DQ2
DQ3
U20
DQ0
DQ1
DQ2
DQ3
U21
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
U23
DQ0
DQ1
DQ2
DQ3
U24
DQ0
DQ1
DQ2
DQ3
U25
DQ0
DQ1
DQ2
DQ3
U26
RAS1
CAS1
RAS3
W2
OE2
B0
DQ0
DQ1
DQ2
DQ3
U27
CAS5
DQ0
DQ1
DQ2
DQ3
U28
DQ0
DQ1
DQ2
DQ3
U29
DQ0
DQ1
DQ2
DQ3
U30
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
U32
DQ0
DQ1
DQ2
DQ3
U33
DQ0
DQ1
DQ2
DQ3
U34
DQ0
DQ1
DQ2
DQ3
U35
DQ0
DQ1
DQ2
DQ3
U9
DQ0
DQ1
DQ2
DQ3
U10
DQ0
DQ1
DQ2
DQ3
U11
DQ0
DQ1
DQ2
DQ3
U12
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
U14
DQ0
DQ1
DQ2
DQ3
U15
DQ0
DQ1
DQ2
DQ3
U16
DQ0
DQ1
DQ2
DQ3
U17
RAS2
CAS4
A1-A11(A12)
U4
U13
U22
U31
DQ0
-
35
DQ36
-
71
DRAM MODULE
M372V320(8)0DT1-C
REV. 0.1 Oct. 2000
I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
and I
CC3
, address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one Fast page mode cycle time,
t
PC
.
* NOTE :
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
I
CC1
*
I
CC2
I
CC3
*
I
CC4
*
I
CC5
I
CC6
*
I(
IL)
I(
OL)
V
OH
V
OL
Symbol
Speed
M372V3200DT1
M372V3280DT1
Unit
Min
Max
Min
Max
I
CC1
-50
-60
-
-
1998
1818
-
-
1458
1278
mA
mA
I
CC2
Don
t care
-
100
-
100
mA
I
CC3
-50
-60
-
-
1998
1818
-
-
1458
1278
mA
mA
I
CC4
-50
-60
-
-
1098
918
-
-
1098
918
mA
mA
I
CC5
Don
t care
-
30
-
30
mA
I
CC6
-50
-60
-
-
1998
1818
-
-
1998
1818
mA
mA
I
I(L)
I
O(L)
Don
t care
-10
-10
10
10
-10
-10
10
10
uA
uA
V
OH
V
OL
Don
t care
2.4
-
-
0.4
2.4
-
-
0.4
V
V
: Operating Current * (RAS, CAS, Address cycling @
t
RC
=min)
: Standby Current (RAS=CAS=W=V
IH
)
: RAS Only Refresh Current * (CAS=V
IH
, RAS cycling @
t
RC
=min)
: Fast Page Mode Current * (RAS=V
IL
, CAS cycling :
t
PC
=min)
: Standby Current (RAS=CAS=W=Vcc-0.2V)
: CAS-Before-RAS Refresh Current * (RAS and CAS cycling @
t
RC
=min)
: Input Leakage Current (Any input 0
V
IN
Vcc+0.3V, all other pins not under test=0 V)
: Output Leakage Current(Data Out is disabled, 0V
V
OUT
Vcc)
: Output High Voltage Level (I
OH
= -2mA)
: Output Low Voltage Level (I
OL
= 2mA)
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to V
SS
, T
A
= 0 to 70
C)
*1 : V
CC
+1.3V at pulse width
15ns, which is measured at V
CC
.
*2 : -1.3V at pulse width
15ns, which is measured at V
SS
.
Item
Symbol
Min
Typ
Max
Unit
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
V
CC
V
SS
V
IH
V
IL
3.0
0
2.0
-0.3
*2
3.3
0
-
-
3.6
0
V
CC
+0.3
*1
0.8
V
V
V
V
ABSOLUTE MAXIMUM RATINGS *
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.
Item
Symbol
Rating
Unit
Voltage on any pin relative V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Output Current
V
IN
, V
OUT
V
CC
T
stg
P
D
I
OS
-0.5 to +4.6
-0.5 to +4.6
-55 to +125
36
50
V
V
C
W
mA
DRAM MODULE
M372V320(8)0DT1-C
REV. 0.1 Oct. 2000
CAPACITANCE
(T
A
= 25
C, f = 1MHz)
Item
Symbol
Min
Max
Unit
Input capacitance[A0, B0, A1 - A12]
Input capacitance[W0, W2, OE0, OE2]
Input capacitance[RAS0 - RAS3]
Input capacitance[CAS0, 1, 4, 5]
Input/Output capacitance[DQ0 - 71]
C
IN1
C
IN2
C
IN3
C
IN4
C
DQ
-
-
-
-
-
20
20
73
20
24
pF
pF
pF
pF
pF
Test condition : V
ih
/V
il
=2.2/0.7V, V
oh
/V
ol
=2.0/0.8V, output loading CL=100pF
Parameter
Symbol
-50
-60
Unit
Note
Min
Max
Min
Max
Random read or write cycle time
t
RC
90
110
ns
Read-modify-write cycle time
t
RWC
133
155
ns
Access time from RAS
t
RAC
50
60
ns
3,4,10
Access time from CAS
t
CAC
18
20
ns
3,4,5,11
Access time from column address
t
AA
30
35
ns
3,10,11
CAS to output in Low-Z
t
CLZ
5
5
ns
3,11
Output buffer turn-off delay
t
OFF
5
18
5
20
ns
6,11
Transition time(rise and fall)
t
T
1
50
1
50
ns
2
RAS precharge time
t
RP
30
40
ns
RAS pulse width
t
RAS
50
10K
60
10K
ns
RAS hold time
t
RSH
18
20
ns
11
CAS hold time
t
CSH
48
58
ns
11
CAS pulse width
t
CAS
13
10K
15
10K
ns
RAS to CAS delay time
t
RCD
18
32
18
40
ns
4,11
RAS to column address delay time
t
RAD
13
20
13
25
ns
10,11
CAS to RAS precharge time
t
CRP
10
10
ns
11
Row address set-up time
t
ASR
5
5
ns
11
Row address hold time
t
RAH
8
8
ns
11
Column address set-up time
t
ASC
0
0
ns
Column address hold time
t
CAH
10
10
ns
Column address to RAS lead time
t
RAL
30
35
ns
11
Read command set-up time
t
RCS
0
0
ns
Read command hold referencde to CAS
t
RCH
0
0
ns
8
Read command hold referenced to RAS
t
RRH
-2
-2
ns
8,11
Write command hold time
t
WCH
10
10
ns
Write command pulse width
t
WP
10
10
ns
Write command to RAS lead time
t
RWL
20
20
ns
11
Write command to CAS lead time
t
CWL
13
15
ns
Data in set-up time
t
DS
-2
-2
ns
9,11
Data in hold time
t
DH
15
15
ns
9,11
Refresh period(4K & 8K)
t
REF
64
64
ms
Write command set-up time
t
WCS
0
0
ns
7
CAS to W delay time
t
CWD
36
40
ns
7
Column address to W delay time
t
AWD
48
55
ns
7
CAS prechange to W delay time
t
CPWD
53
60
ns
7
RAS ro W delay time
t
RWD
71
83
ns
7,11
AC CHARACTERISTICS
(0
C
T
A
70
C, V
CC
=3.3V
0.3V. See notes 1,2.)
DRAM MODULE
M372V320(8)0DT1-C
REV. 0.1 Oct. 2000
AC CHARACTERISTICS
(0
C
T
A
70
C, V
CC
=3.3V
0.3V. See notes 1,2.)
Parameter
Symbol
-50
-60
Unit
Note
Min
Max
Min
Max
CAS setup time(CAS-before-RAS refresh)
t
CSR
10
10
ns
11
CAS hold time(CAS-before-RAS refresh)
t
CHR
8
8
ns
11
RAS to CAS precharge time
t
RPC
3
3
ns
11
Access time from CAS precharge
t
CPA
35
40
ns
3,11
Fast page mode cycle time
t
PC
35
40
ns
Fast page mode read-modify-write cycle time
t
PRWC
76
85
ns
CAS precharge time(Fast page cycle)
t
CP
10
10
ns
RAS pulse width(Fast page cycle)
t
RASP
50
200K
60
200K
ns
RAS hold time from CAS precharge
t
RHCP
35
40
ns
11
W to RAS precharge time(C-B-R refresh)
t
WRP
15
15
ns
11
W to RAS hold time(C-B-R refresh)
t
WRH
8
8
ns
11
OE access time
t
OEA
18
20
ns
11
OE to data delay
t
OED
18
20
ns
11
Output buffer turn off delay time from OE
t
OEZ
5
18
5
20
ns
11
OE command hold time
t
OEH
13
15
ns
PDE to Valid PD bit
t
PD
10
10
ns
PDE to PD bit Inactive
t
PDOFF
2
7
2
7
ns
Present Detect Read Cycle
NOTES
An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
Input voltage levels are V
ih
/V
il
. V
IH
(min) and V
IL
(max) are ref-
erence levels for measuring timing of input signals. Transi-
tion times are measured between V
IH
(min) and V
IL
(max) and
are assumed to be 5ns for all inputs.
Measured with a load equivalent to 1 TTL loads and 100pF.
Operation within the
t
RCD
(max) limit insures that
t
RAC
(max)
can be met.
t
RCD
(max) is specified as a reference point only.
If
t
RCD
is greater than the specified
t
RCD
(max) limit, then
access time is controlled exclusively by
t
CAC
.
Assumes tha
t
RCD
t
RCD
(max).
This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to V
OH
or
V
OL
.
t
WCS
,
t
RWD
,
t
CWD
,
t
AWD
and
t
CPWD
are not restrictive operat-
ing parameter. They are included in the data sheet as electri-
cal characteristics only. If
t
WCS
t
WCS
(min) the cycle is an
early write cycle and the data out pin will remain high imped-
ance for the duration of the cycle. If
t
RWD
t
RWD
(min),
t
CWD
t
CWD
(min),
t
AWD
t
AWD
(min) and
t
CPWD
t
CPWD
(min).
The cycle is a read-modify-write cycle and the data out will
contain data read from the selected cell. If neither of the
above sets of conditions is satisfied, the condition of data
out(at access time) is indeterminate.
Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
These parameters are referenced to the CAS leading edge in
early write cycles.
Operation within the
t
RAD
(max) limit insures that
t
RAC
(max)
can be met.
t
RAD
(max) is specified as reference point only. If
t
RAD
is greater than the specified
t
RAD
(max) limit, then
access time is controlled by
t
AA
.
The timing skew from the DRAM to the DIMM resulted from
the addition of buffers.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
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