K4G163222A

CMOS SGRAM

The K4G163222A is 16,777,216 bits synchronous high data
rate Dynamic RAM organized as 2 x 262,144 words by 32 bits,
fabricated with SAMSUNG

s high performance CMOS technol-

ogy. Synchronous design allows precise cycle control with the
use of system clock. I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length, and programmable latencies allows the same
device to be useful for a variety of high bandwidth, high perfor-
mance memory system applications.
Write per bit and 8 columns block write improves performance in
graphics systems.

· 3.3V power supply

· LVTTL compatible with multiplexed address

· Dual banks operation

· MRS cycle with address key programs

-. CAS Latency (2, 3)

-. Burst Length (1, 2, 4, 8 & full page)

-. Burst Type (Sequential & Interleave)

· All inputs are sampled at the positive going edge of the

system clock

· Burst Read Single-bit Write operation

· DQM 0-3 for byte masking

· Auto & self refresh

32ms refresh period (2K cycle)

· 100 Pin PQFP, TQFP (14 x 20 mm)

Graphics Features

· SMRS cycle.

-. Load mask register

-. Load color register

· Write Per Bit(Old Mask)

· Block Write(8 Columns)

GENERAL DESCRIPTION

FEATURES

FUNCTIONAL BLOCK DIAGRAM

256K x 32Bit x 2 Banks Synchronous Graphic RAM

I
M

I
N

I
S

CLK

CKE

RAS

CAS

DSF

DQMi

BLOCK

WRITE

CONTROL

LOGIC

DQi

I
N

I
S

256Kx32

CELL

ARRAY

256Kx32

CELL

ARRAY

SERIAL

COUNTER

COLUMN ADDRESS

BUFFER

ROW DECORDER

BANK SELECTION

ADDRESS REGISTER

REFRESH

COUNTER

ROW ADDRESS

BUFFER

I
N

MASK

COLOR

MUX

WRITE

CONTROL

LOGIC

I
F

I
E

COLUMN

MASK

(i=0~31)

DQMi

CLOCK ADDRESS(A

)

DQMi

Samsung Electronics reserves the right to
change products or specification without
notice.

ORDERING INFORMATION

Part NO.

Max Freq.

Interface

Package

K4G163222A-PC/L50

200MHz

LVTTL

100 PQFP

K4G163222A-PC/L55

183MHz

K4G163222A-PC/L60

166MHz

K4G163222A-PC/L70

143MHz

K4G163222A-PC/L80

125MHz

K4G163222A-QC/L50

200MHz

LVTTL

100 TQFP

K4G163222A-QC/L55

183MHz

K4G163222A-QC/L60

166MHz

K4G163222A-QC/L70

143MHz

K4G163222A-QC/L80

125MHz

K4G163222A

CMOS SGRAM

DQ29

SSQ

DQ30
DQ31

N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
V

DQ0
DQ1

SSQ

DQ2

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

PIN CONFIGURATION (TOP VIEW)

(
A

)

N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
V

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31

100 Pin QFP

Forward Type

20 x 14 mm

0.65mm pin Pitch

.
C

/
A

PIN CONFIGURATION DESCRIPTION

Pin

Name

Input Function

CLK

System Clock

Active on the positive going edge to sample all inputs.

Chip Select

Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQMi

CKE

Clock Enable

Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle

prior to new command.

Disable input buffers for power down in standby.

~ A

Address

Row / Column addresses are multiplexed on the same pins.
Row address : RA

~ RA

, Column address : CA

~ CA

BA(A

)

Bank Select Address

Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.

RAS

Row Address Strobe

Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.

CAS

Column Address Strobe

Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.

Write Enable

Enables write operation and Row precharge.
Latches data in starting from CAS, WE active.

DQMi

Data Input/Output Mask

Makes data output Hi-Z, t

SHZ

after the clock and masks the output.

Blocks data input when DQM active.(Byte Masking)

DQi

Data Input/Output

Data inputs/outputs are multiplexed on the same pins.

DSF

Define Special Function

Enables write per bit, block write and special mode register set.

Power Supply /Ground

Power and ground for the input buffers and the core logic.

DDQ

SSQ

Data Output Power /Ground

Isolated power supply and ground for the output buffers to provide improved noise
immunity.

N.C

No Connection

This pin is recommended to be left No Connection on the device.

*PQFP (Height = 3.0mmMAX)
TQFP (Height = 1.2mmMAX)

K4G163222A

CMOS SGRAM

DECOUPLING CAPACITANCE GUIDE LINE

1. V

and V

DDQ

pins are separated each other.

All V

pins are connected in chip. All V

DDQ

pins are connected in chip.

2. V

and V

SSQ

pins are separated each other

All V

pins are connected in chip. All V

SSQ

pins are connected in chip.

Note :

Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Note :

DC OPERATING CONDITIONS

1. V

(max) = 5.6V AC. The overshoot voltage duration is

3ns.

2. V

(min) = -2.0V AC. The undershoot voltage duration is

3ns.

3. Any input 0V

DDQ

Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Dout is disabled, 0V

OUT

DD.

5. The VDD condition of K4G163222A-50/55/60 is 3.135V~3.6V.

Note :

ABSOLUTE MAXIMUM RATINGS

(Voltage referenced to V

)

Parameter

Symbol

Value

Unit

Voltage on any pin relative to Vss

, V

OUT

-1.0

4.6

Voltage on V

supply relative to Vss

, V

DDQ

-1.0

4.6

Storage temperature

STG

-55 ~ +150

Power dissipation

Short circuit current

Recommended operating conditions (Voltage referenced to V

= 0V)

Parameter

Symbol

Min

Typ

Max

Unit

Note

Supply voltage

, V

DDQ

3.0

3.3

3.6

Input high voltage

2.0

3.0

DDQ

+0.3

Input low voltage

-0.3

0.8

Output high voltage

2.4

= -2mA

Output low voltage

0.4

= 2mA

Input leakage current

-10

Output leakage current

-10

Output Loading Condition

see figure 1

CAPACITANCE

DDQ

= 3.3V, T

= 23

C, f = 1MHz)

Pin

Symbol

Min

Max

Unit

Clock

CLK

4.0

RAS, CAS, WE, CS, CKE, DQM

,DSF

4.0

Address

ADD

4.0

OUT

5.0

Recommended decoupling capacitance added to power line at board.

Parameter

Symbol

Value

Unit

Decoupling Capacitance between V

and V

DC1

0.1 + 0.01

Decoupling Capacitance between V

DDQ

and V

SSQ

DC2

0.1 + 0.01

K4G163222A

CMOS SGRAM

DC CHARACTERISTICS

1. Unless otherwise notes, Input level is CMOS(V

DDQ

SSQ

) in LVTTL.

2. Measured with outputs open. Addresses are changed only one time during tcc(min).

3. Refresh period is 32ms. Addresses are changed only one time during tcc(min).

4. K4G163222A-C*

5. K4G163222A-L* : Low Power version

Note :

(Recommended operating condition unless otherwise noted, T

= 0 to 70

C, V

IH(min)

IL(max)

=2.0V/0.8V)

Parameter

Symbol

Test Condition

CAS

Latency

Speed

Unit Note

-50

-55

-60

-70

-80

Operating Current
(One Bank Active)

CC1

Burst Length =1
t

(min), t

(min), I

= 0mA

200

190

180

160

150

Precharge Standby Current
in power-down mode

CC2

CKE

(max), t

= 15ns

CC2

CKE

CLK

(max), t

Precharge Standby Current
in non power-down mode

CC2

CKE

(min), CS

(min), t

= 15ns

Input signals are changed one time during 30ns

CC2

CKE

(min), CLK

(max), t

Input signals are stable

Active Standby Current
in power-down mode

CC3

CKE

(max), t

= 15ns

CC3

CKE

(max), t

Active Standby Current
in non power-down mode
(One Bank Active)

CC3

CKE

(min), CS

(min), t

= 15ns

Input signals are changed one time during 30ns

CC3

CKE

(min), CLK

(max), t

Input signals are stable

Operating Current
(Burst Mode)

CC4

= 0 mA, Page Burst

All bank Activated, t

CCD

= t

CCD

(min)

290

270

260

230

200

160

Refresh Current

CC5

(min)

200

190

180

160

150

Self Refresh Current

CC6

CKE

0.2V

450

Operating Current
(One Bank Block Write)

CC7

(min), I

=0mA, t

BWC

(min)

230

210

200

170

150

K4G163222A

CMOS SGRAM

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then

rounding off to the next higher integer. Refer to the following ns-unit based AC table.

Note :

AC OPERATING TEST CONDITIONS

= 3.3V

0.3V, T

= 0 to 70

Parameter

Value

Unit

Input levels (V

)

2.4 / 0.4

Input timing measurement reference level

1.4

Input rise and fall time

=1 / 1

Output timing measurement reference level

1.4

Output load condition

See Fig. 2

3.3V

1200

870

Output

30pF

(DC) = 2.4V, I

= -2mA

(DC) = 0.4V, I

= 2mA

= 1.4V

Output

30pF

Z0=50

(Fig. 2) AC Output Load Circuit

(Fig. 1) DC Output Load Circuit

1. The VDD condition of K4G163222A-50/55/60 is 3.135V~3.6V.

Note :

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Parameter

Symbol

Version

Unit

Note

-50

-55

-60

-70

-80

CAS Latency

CLK

CLK cycle time

CC(min)

5.5

Row active to row active delay

RRD(min)

CLK

RAS to CAS delay

RCD(min)

CLK

Row precharge time

RP(min)

CLK

Row active time

RAS(min)

CLK

RAS(max)

100

Row cycle time

(

min

)

CLK

Last data in to row precharge

RDL(min)

CLK

2, 5

Last data in to new col.address delay

CDL(min)

CLK

Last data in to burst stop

BDL(min)

CLK

Col. address to col. address delay

CCD(min)

CLK

Block Write data-in to PRE command

BPL(min)

CLK

Block write cycle time

BWC(min)

CLK

Mode Register Set cycle time

MRS(min)

CLK

Number of valid output data

CAS Latency=3

CAS Latency=2

K4G163222A

CMOS SGRAM

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf)=1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]ns should be added to the parameter.

Note :

2. Minimum delay is required to complete write.
3. This parameter means minimum CAS to CAS delay at block write cycle only.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. For -55/60/70/80, tRDL =1CLK product can be supported within restricted amounts and it will be distinguished by bucket code
"NV".

From the next generation, tRDL will be only 2CLK for every clock frequency.

AC CHARACTERISTICS

(AC operating conditions unless otherwise noted)

Parameter

Symbol

-50

-55

-60

-70

-80

Unit Note

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

CLK cycle time

CAS Latency=3

1000

5.5

1000

CAS Latency=2

CLK to valid
output delay

CAS Latency=3

SAC

4.5

5.5

1, 2

CAS Latency=2

Output data hold time

2.5

CLK high pulse width

CAS Latency=3

2.5

CAS Latency=2

CLK low
pulse width

CAS Latency=3

2.5

CAS Latency=2

Input setup time

CAS Latency=3

1.5

1.75

CAS Latency=2

2.5

Input hold time

CLK to output in Low-Z

SLZ

CLK to output
in Hi-Z

CAS latency=3

SHZ

4.5

5.5

CAS latency=2

Parameter

Symbol

Version

Unit

-50

-55

-60

-70

-80

CLK cycle time

CC(min)

5.5

Row active to row active delay

RRD(min)

RAS to CAS delay

RCD(min)

16.5

Row precharge time

RP(min)

16.5

Row active time

RAS(min)

38.5

RAS(max)

100

Row cycle time

(

min

)

K4G163222A

CMOS SGRAM

SIMPLIFIED TRUTH TABLE

(V=Valid, X=Don

t Care, H=Logic High, L=Logic Low)

COMMAND

CKEn-1 CKEn

RAS

CAS

DSF DQM A

~ A

Note

Mode Register Set

OP CODE

1, 2

Special Mode Register Set

1,2,7

Refresh

Auto Refresh

Self
Refresh

Entry

Exit

Bank Active
& Row Addr.

Write Per Bit Disable

Row Address

4, 5

Write Per Bit Enable

4,5,9

Read &
Column Address

Auto Precharge Disable

Column

Address

~ A

)

Auto Precharge Enable

4, 6

Write &
Column Address

Auto Precharge Disable

Column

Address

~ A

)

4, 5

Auto Precharge Enable

4,5,6,9

Block Write &
Column Addr.

Auto Precharge Disable

Column

Address

~ A

)

4, 5

Auto Precharge Enable

4,5,6,9

Burst Stop

Precharge

Bank Selection

Both Banks

Clock Suspend or
Active Power Down

Entry

Exit

Precharge Power Down Mode

Entry

Exit

DQM

No Operation Command

1. OP Code : Operand Code

~ A

: Program keys. (@MRS)

, A

: LMR or LCR select. (@SMRS)

Color register exists only one per DQi which both banks share.

So dose Mask Register.

Color or mask is loaded into chip through DQ pin.

2. MRS can be issued only at both banks precharge state.

SMRS can be issued only if DQ

s are idle.

A new command can be issued at the next clock of MRS/SMRS.

Note :

K4G163222A

CMOS SGRAM

SGRAM vs SDRAM

If DSF is low, SGRAM functionality is identical to SDRAM functionality.

SGRAM can be used as an unified memory by the appropriate DSF control
--> SGRAM=Graphic Memory + Main Memory

Function

MRS

Bank Active

Write

DSF

SGRAM

Function

MRS

SMRS

Bank Active

with

Write per bit

Disable

Bank Active

with

Write per bit

Enable

Normal

Write

Block

Write

3. Auto refresh functions as same as CBR refresh of DRAM.

The automatical precharge without Row precharge command is meant by "Auto".

Auto/Self refresh can be issued only at both precharge state.

4. A

: Bank select address.

If "Low" at read, (block) write, Row active and precharge, bank A is selected.

If "High" at read, (block) write, Row active and precharge, bank B is selected.

If A

is "High" at Row precharge, A

is ignored and both banks are selected.

5. It is determined at Row active cycle.

whether Normal/Block write operates in write per bit mode or not.

For A bank write, at A bank Row active, for B bank write, at B bank Row active.

Terminology : Write per bit =I/O mask

(Block) Write with write per bit mode=Masked(Block) Write

6. During burst read or write with auto precharge, new read/(block) write command cannot be issued.

Another bank read/(block) write command can be issued at

after the end of burst.

7. Burst stop command is valid only at full page burst length.

8. DQM sampled at positive going edge of a CLK.

masks the data-in at the very CLK(Write DQM latency is 0)

but makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)

9. Graphic features added to SDRAM

s original features.

If DSF is tied to low, graphic functions are disabled and chip operates as a 16M SDRAM with 32 DQ

SIMPLIFIED TRUTH TABLE

K4G163222A

CMOS SGRAM

SGRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

1. Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 may be changed.

The device is now ready for normal operation.

Note : 1. RFU(Reserved for Future Use) should stay "0" during MRS cycle.
2. If A

is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.

3. The full column burst(256bit) is available only at Sequential mode of burst type.
4. If LC and LM both high(1), data of mask and color register will be unknown.

Register Programmed with MRS

(Note 1) (Note 2)

Address

Function

RFU

W.B.L

CAS Latency

Burst Length

(Note 3)

Test Mode

CAS Latency

Burst Type

Burst Length

Type

Latency

Type

BT=0

BT=1

Mode Register Set

Reserved

Sequential

Reserved

Vendor

Use

Only

Interleave

Reserved

Write Burst Length

Reserved

Length

Reserved

Burst

Reserved

Single Bit

Reserved

256(Full)

Reserved

Special Mode Register Programmed with SMRS

Address

Function

(Note 4)

Load Color

Load Mask

Function

Disable

Enable

MODE REGISTER FIELD TABLE TO PROGRAM MODES

POWER UP SEQUENCE

K4G163222A

CMOS SGRAM

BURST SEQUENCE (BURST LENGTH = 4)

Initial address

Sequential

Interleave

BURST SEQUENCE (BURST LENGTH = 8)

Initial address

Sequential

Interleave

PIXEL to DQ MAPPING(at BLOCK WRITE)

Column address

3 Byte

2 Byte

1 Byte

0 Byte

I/O

- I/O

I/O

- I/O

I/O

- I/O

I/O

- I/O

K4G163222A

CMOS SGRAM

CLOCK (CLK)

The clock input is used as the reference for all SGRAM opera-
tions. All operations are synchronized to the positive going edge
of the clock. The clock transitions must be monotonic between
V

and V

. During operation with CKE high all inputs are

assumed to be in a valid state (low or high) for the duration of
set-up and hold time around positive edge of the clock for proper
functionality and I

specifications.

CLOCK ENABLE (CKE)

The clock enable(CKE) gates the clock onto SGRAM. If CKE
goes low synchronously with clock (set-up and hold time are the
same as other inputs), the internal clock is suspended from the
next clock cycle and the state of output and burst address is fro-
zen as long as the CKE remains low. All other inputs are ignored
from the next clock cycle after CKE goes low. When both banks
are in the idle state and CKE goes low synchronously with clock,
the SGRAM enters the power down mode from the next clock
cycle. The SGRAM remains in the power down mode ignoring
the other inputs as long as CKE remains low. The power down
exit is synchronous as the internal clock is suspended. When
CKE goes high at least "

+ 1

CLOCK

" before the high going

edge of the clock, then the SGRAM becomes active from the
same clock edge accepting all the input commands.

BANK SELECT (A

)

This SGRAM is organized as two independent banks of 262,144
words x 32 bits memory arrays. The A

inputs is latched at the

time of assertion of RAS and CAS to select the bank to be used
for the operation. When A

is asserted low, bank A is selected.

When A

is asserted high, bank B is selected. The bank select

is latched at bank activate, read, write mode register set and

precharge operations.

ADDRESS INPUT (A

~ A

)

The 18 address bits required to decode the 262,144 word loca-
tions are multiplexed into 10 address input pins(A

). The 10

bit row address is latched along with RAS and A

during bank

activate command. The 8 bit column address is latched along
with CAS, WE and A

during read or write command.

NOP and DEVICE DESELECT

When RAS, CAS and WE are high, the SGRAM performs no

operation (NOP). NOP does not initiate any new operation, but

is needed to complete operations which require more than sin-

gle clock cycle like bank activate, burst read, auto refresh, etc.

The device deselect is also a NOP and is entered by asserting

CS high. CS high disables the command decoder so that RAS,

CAS, WE, DSF and all the address inputs are ignored.

POWER-UP

SGRAMs must be powered up and initialized in a pre-
defined manner to prevent undefined operations.

1. Power must be applied to both CKE and DQM inputs to pull
them high and other pins are NOP condition at the inputs
before or along with V

(and V

DDQ

) supply.

The clock signal must also be asserted at the same time.
2. After V

reaches the desired voltage, a minimum pause of

200 microseconds is required with inputs in NOP condition.
3. Both banks must be precharged now.
4. Perform a minimum of 2 Auto refresh cycles to stabilize the
internal circuitry.
5. Perform a MODE REGISTER SET cycle to program the CAS
latency, burst length and burst type as the default value of
mode register is undefined.
At the end of one clock cycle from the mode register set cycle,
the device is ready for operation.
When the above sequence is used for Power-up, all the outputs
will be in high impedance state. The high impedance of outputs
is not guaranteed in any other power-up sequence.
cf.) Sequence of 4 & 5 may be changed.

MODE REGISTER SET (MRS)

The mode register stores the data for controlling the various

operating modes of SGRAM. It programs the CAS latency,

addressing mode, burst length, test mode and various vendor

specific options to make SGRAM useful for variety of different

applications. The default value of the mode register is not

defined, therefore the mode register must be written after power

up to operate the SGRAM. The mode register is written by

asserting low on CS, RAS, CAS, WE and DSF (The SGRAM

should be in active mode with CKE already high prior to writing

the mode register). The state of address pins A

~ A

and A

the same cycle as CS, RAS, CAS, WE and DSF going low is the

data written in the mode register. One clock cycle is required to

complete the write in the mode register. The mode register con-

tents can be changed using the same command and clock cycle

requirements during operation as long as both banks are in the

idle state. The mode register is divided into various fields

depending on functionality. The burst length field uses A

~ A

burst type uses A

, addressing mode uses A

~ A

, A

~ A

and

are used for vendor specific options or test mode. And the

write burst length is programmed using A

. A

~ A

and A

must

be set to low for normal SGRAM operation. Refer to table for

specific codes for various burst length, addressing modes and

CAS latencies.

DEVICE OPERATIONS

K4G163222A

CMOS SGRAM

BANK ACTIVATE

The bank activate command is used to select a random row in
an idle bank. By asserting low on RAS and CS with desired row
and bank addresses, a row access is initiated. The read or write
operation can occur after a time delay of t

RCD

(min) from the time

of bank activation. t

RCD

(min) is an internal timing parameter of

SGRAM, therefore it is dependent on operating clock frequency.
The minimum number of clock cycles required between bank
activate and read or write command should be calculated by
dividing t

RCD

(min) with cycle time of the clock and then rounding

off the result to the next higher integer. The SGRAM has two
internal banks on the same chip and shares part of the internal
circuitry to reduce chip area, therefore it restricts the activation
of both banks immediately. Also the noise generated during
sensing of each bank of SGRAM is high requiring some time for
power supplies to recover before the other bank can be sensed
reliably. t

RRD

(min) specifies the minimum time required between

activating different banks. The number of clock cycles required
between different bank activation must be calculated similar to
t

RCD

specification. The minimum time required for the bank to be

active to initiate sensing and restoring the complete row of
dynamic cells is determined by t

RAS

(min) specification before a

precharge command to that active bank can be asserted. The
maximum time any bank can be in the active state is determined
by t

RAS

(max). The number of cycles for both t

RAS

(min) and

RAS

(max) can be calculated similar to t

RCD

specification.

BURST READ

The burst read command is used to access burst of data on con-
secutive clock cycles from an active row in an active bank. The
burst read command is issued by asserting low on CS and CAS
with WE being high on the positive edge of the clock. The bank
must be active for at least t

RCD

(min) before the burst read com-

mand is issued. The first output appears CAS latency number of
clock cycles after the issue of burst read command. The burst
length, burst sequence and latency from the burst read com-
mand is determined by the mode register which is already pro-
grammed. The burst read can be initiated on any column
address of the active row. The address wraps around if the initial
address does not start from a boundary such that number of out-
puts from each I/O are equal to the burst length programmed in
the mode register. The output goes into high-impedance at the
end of the burst, unless a new burst read was initiated to keep
the data output gapless. The burst read can be terminated by
issuing another burst read or burst write in the same bank or the
other active bank or a precharge command to the same bank.
The burst stop command is valid only at full page burst length
where the output does not go into high impedance at the end of
burst and the burst is wrapped around..

BURST WRITE

The burst write command is similar to burst read command, and
is used to write data into the SGRAM on consecutive clock

cycles in adjacent addresses depending on burst length and

burst sequence. By asserting low on CS, CAS and WE with valid
column address, a write burst is initiated. The data inputs are
provided for the initial address in the same clock cycle as the
burst write command. The input buffer is deselected at the end
of the burst length, even though the internal writing may not
have been completed yet. The writing can not complete to burst
length. The burst write can be terminated by issuing a burst
read and DQM for blocking data inputs or burst write in the same
or the other active bank. The burst stop command is valid only at
full page burst length where the writing continues at the end of
burst and the burst is wrapped around. The write burst can also
be terminated by using DQM for blocking data and precharging
the bank "t

RDL

" after the last data input to be written into the

active row. See DQM OPERATION also.

DQM OPERATION

The DQM is used to mask input and output operations. It works
similar to OE during read operation and inhibits writing during
write operation. The read latency is two cycles from DQM and
zero cycle for write, which means DQM masking occurs two
cycles later in the read cycle and occurs in the same cycle dur-
ing write cycle. DQM operation is synchronous with the clock,
therefore the masking occurs for a complete cycle. The DQM
signal is important during burst interrupts of write with read or
precharge in the SGRAM. Due to asynchronous nature of the
internal write, the DQM operation is critical to avoid unwanted or
incomplete writes when the complete burst write is not required.
DQM is also used for device selection, byte selection and bus
control in a memory system. DQM0 controls DQ0 to DQ7,
DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23,
DQM3 controls DQ24 to DQ31. DQM masks the DQ

s by a byte

regardless that the corresponding DQ

s are in a state of WPB

masking or Pixel masking. Please refer to DQM timing diagram
also.

PRECHARGE

The precharge operation is performed on an active bank by
asserting low on CS, RAS, WE and A

with valid A

of the bank

to be precharged. The precharge command can be asserted
anytime after t

RAS

(min) is satisfied from the bank activate com-

mand in the desired bank. "t

" is defined as the minimum time

required to precharge a bank. The minimum number of clock
cycles required to complete row precharge is calculated by
dividing "t

" with clock cycle time and rounding up to the next

higher integer. Care should be taken to make sure that burst
write is completed or DQM is used to inhibit writing before pre-
charge command is asserted. The maximum time any bank can
be active is specified by t

RAS

(max). Therefore, each bank has to

be precharged within t

RAS

(max)

from the bank

activate com-

mand. At the end of precharge, the bank enters the idle state
and is ready to be activated again.

DEVICE OPERATIONS

K4G163222A

CMOS SGRAM

Entry to Power Down, Auto refresh, Self refresh and Mode reg-
ister Set etc. is possible only when both banks are in idle state.

AUTO PRECHARGE

The precharge operation can also be performed by using auto

precharge. The SGRAM internally generates the timing to satisfy

RAS

(min) and "t

" for the programmed burst length and CAS

latency. The auto precharge command is issued at the same

time as burst read or burst write by asserting high on A

. If burst

read or burst write command is issued with low on A

, the bank

is left active until a new command is asserted. Once auto pre-

charge command is given, no new commands are possible to

that particular bank until the bank achieves idle state.

BOTH BANKS PRECHARGE

Both banks can be precharged at the same time by using Pre-

charge all command. Asserting low on CS, RAS, and WE with

high on A

after both banks have satisfied t

RAS

(min) require-

ment, performs precharge on both banks. At the end of t

after

performing precharge all, both banks are in idle state.

AUTO REFRESH

The storage cells of SGRAM need to be refreshed every 32ms

to maintain data. An auto refresh cycle accomplishes refresh of

a single row of storage cells. The internal counter increments

automatically on every auto refresh cycle to refresh all the rows.

An auto refresh command is issued by asserting low on CS,RAS

and CAS with high on CKE and WE. The auto refresh command

can only be asserted with both banks being in idle state and the

device is not in power down mode (CKE is high in the previous

cycle). The time required to complete the auto refresh operation

is specified by "t

(min)". The minimum number of clock cycles

required can be calculated by driving "t

" with clock cycle time

and them rounding up to the next higher integer. The auto

refresh command must be followed by NOP

s until the auto

refresh operation

s completed. Both banks will be in the idle

state at the end of auto refresh operation. The auto refresh is the

preferred refresh mode when the SGRAM is being used for nor-

mal data transactions. The auto refresh cycle can be performed

once in 15.6us or a burst of 2048 auto refresh cycles once in

32ms.

SELF REFRESH

The self refresh is another refresh mode available in the
SGRAM. The self refresh is the preferred refresh mode for data
retention and low power operation of SGRAM. In self refresh
mode, the SGRAM disables the internal clock and all the input
buffers except CKE. The refresh addressing and timing are
internally generated to reduce power consumption.
The self refresh mode is entered from all banks idle state by
asserting low on CS, RAS, CAS and CKE with high on WE.
Once the self refresh mode is entered, only CKE state being low
matters, all the other inputs including the clock are ignored in
order to remain in the self refresh mode.
The self refresh is exited by restarting the external clock and
then asserting high on CKE. This must be followed by NOP

for a minimum time of "t

" before the SGRAM reaches idle

state to begin normal operation. If the system uses burst auto
refresh during normal operation, it is recommended to use burst
2048 auto refresh cycles immediately after exiting self refresh.

DEFINE SPECIAL FUNCTION(DSF)

The DSF controls the graphic applications of SGRAM. If DSF is
tied to low, SGRAM functions as 256K x 32 x2 Bank SDRAM.
SGRAM can be used as an unified memory by the appropriate
DSF command. All the graphic function modes can be entered
only by setting DSF high when issuing commands which other-
wise would be normal SDRAM commands. SDRAM functions
such as RAS Active, Write, and WCBR change to SGRAM func-
tions such as RAS Active with WPB, Block Write and SWCBR
respectively. See the section below for the graphic functions that
DSF controls.

SPECIAL MODE REGISTER SET(SMRS)

There are two kinds of special mode registers in SGRAM.One is
color register and the other is mask register. Those usage will be
explained in the "WRITE PER BIT" and "BLOCK WRITE" sec-
tions. When A

and DSF goes high in the same cycle as CS,

RAS, CAS and WE going low, Load Mask Register(LMR) pro-
cess is executed and the mask registers are filled with the
masks for associated DQ

s through DQ pins. And when A

and

DSF goes high in the same cycle as CS, RAS, CAS and WE
going low, Load Color Register(LCR) process is executed and
the color register is filled with color data for associated DQ

through the DQ pins. If both A

and A

are high at SMRS, data

of mask and color cycle are required to complete the write in the
mask register and the color register at LMR and LCR respec-
tively. A new command can be issued in the next clock of LMR
or LCR. SMRS, compared with MRS, can be issued at the active
state under the condition that DQ

s are idle. As in write opera-

tion, SMRS accepts the data needed through DQ pins. There-
fore bus contention must be avoided. The more detailed
materials can be obtained by referring corresponding timing dia-
gram.

DEVICE OPERATIONS (Continued)

K4G163222A

CMOS SGRAM

WRITE PER BIT

Write per bit(i.e. I/O mask mode) for SGRAM is a function that

selectively masks bits of data being written to the devices. The
mask is stored in an internal register and applied to each bit of
data written when the mask is enabled. Bank active command
with DSF=High enables write per bit for associated bank. Bank
active command with DSF=Low disables write per bit for the
associated bank. The mask used for write per bit operations is
stored in the mask register accessed by SWCBR(Special Mode
Register Set Command). When a mask bit=1, the associated
data bit is written when a write command is executed and write
per bit has been enabled for the bank being written. When a
mask bit=0, the associated data bit is unaltered when a write
command is executed and the write per bit has been enabled for
the bank being written. No additional timing conditions are
required for write per bit operations. Write per bit writes can be
either single write, burst writes or block writes. DQM masking is
the same for write per bit and non-WPB write.

BLOCK WRITE

Block write is a feature allowing the simultaneous writing of
consecutive 8 columns of data within a RAM device during a sin-
gle access cycle. During block write the data to be written comes
from an internal "color" register and DQ I/O pins are used for
independent column selection. The block of column to be written
is aligned on 8 column boundaries and is defined by the column
address with the 3 LSB

s ignored. Write command with DSF=1

enables block write for the associated bank. A write command
with DSF=0 enables normal write for the associated bank. The
block width is 8 column where column="n" bits for by "n" part.
The color register is the same width as the data port of the
chip.It is written via a SWCBR where data present on the DQ pin
is to be coupled into the internal color register. The color register
provides the data masked by the DQ column select, WPB
mask(If enabled), and DQM byte mask. Column data mask-
ing(Pixel masking) is provided on an individual column basis for
each byte of data. The column mask is driven on the DQ pins
during a block write command. The DQ column mask function is
segmented on a per bit basis(i.e. DQ[0:7] provides the column
mask for data bits[0:7], DQ[8:15] provides the column mask for
data bits[8:15], DQ0 masks column[0] for data bits[0:7], DQ9
masks column [1] for data bits [8:15], etc). Block writes are
always non-burst, independent of the burst length that has been
programmed into the mode register. Back to back block writes
are allowed provided that the specified block write cycle
time(

BWC

) is satisfied. If write per bit was enabled by the bank

active command with DSF=1, then write per bit masking of the
color register data is enabled.
If write per bit was disabled by a bank active command with
DSF=0, the write per bit masking of the color register data is dis-
abled. DQM masking provides independent data byte masking
during block write exactly the same as it does during normal
write operations, except that the control is extended to the con-
secutive 8 columns of the block write.

1 CLK BW

CLOCK

CKE

RAS

CAS

DSF

HIGH

Timing Diagram to lllustrate

BWC

DEVICE OPERATIONS (Continued)

K4G163222A

CMOS SGRAM

SUMMARY OF 2M Byte SGRAM BASIC FEATURES AND BENEFITS

Features

256K x 32 x 2 SGRAM

Benefits

Interface

Synchronous

Better interaction between memory and system without wait-state of
asynchronous DRAM.
High speed vertical and horizontal drawing.
High operating frequency allows performance gain for SCROLL, FILL,
and BitBLT.

Bank

2 ea

Pseudo-infinite row length by on-chip interleaving operation.
Hidden row activation and precharge.

Page Depth / 1 Row

256 bit

High speed vertical and horizontal drawing.

Total Page Depth

2048 bytes

High speed vertical and horizontal drawing.

Burst Length(Read)

1, 2, 4, 8 Full Page

Programmable burst of 1, 2, ,4, 8 and full page transfer per column
addresses.

Burst Length(Write)

1, 2, 4, 8 Full Page

Programmable burst of 1, 2, ,4, 8 and full page transfer per column
addresses.

BRSW

Switch to burst length of 1 at write without MRS.

Burst Type

Sequential & Interleave

Compatible with Intel and Motorola CPU based system.

CAS Latency

2, 3

Programmable CAS latency.

Block Write

8 Columns

High speed FILL, CLEAR, Text with color registers.
Maximum 32 byte data transfers(e.g. for 8bpp : 32 pixels) with plane and
byte masking functions.

Color Register

1 ea.

A and B bank share.

Mask Register

1 ea.

Write-per-bit capability(bit plane masking). A and B banks share.

Mask function

DQM

0-3

Byte masking(pixel masking for 8bpp system) for data-out/in

Write per bit

Each bit of the mask register directly controls a corresponding bit plane.

Pixel Mask at Block Write

Byte masking(pixel masking for 8bpp system) for color by DQi

K4G163222A

CMOS SGRAM

Note 3
Auto Precharge Starts

*Note : 1. To inhibit invalid write, DQM should be issued.

2. This precharge command and burst write command should be of the same bank, otherwise it is not precharge

interrupt but only another bank precharge of dual banks operation.

3. For -55/60/70/80, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV"
. From the next generation, tRDL will be only 2CLK for every clock frequency.

5. Write Interrupted by Precharge & DQM

CLK

CMD

DQM

Masked by DQM

PRE

Note 2,3

Note 1

*Note :1. t

BPL

: Block write data-in to PRE command delay

2. Number of valid output data after Row Precharge : 1, 2 for CAS Latency =2, 3 respectively.

3. The row active command of the precharge bank can be issued after t

from this point. The new read/write command of other activated

bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.

4. For -55/60/70/80, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV"
. From the next generation, tRDL will be only 2CLK for every clock frequency.

6. Precharge

CLK

CMD

PRE

1) Normal Write (BL=4)

RDL

Note 1,4

3) Read (BL=4)

CLK

CMD

DQ(CL2)

DQ(CL3)

PRE

Note 2

7. Auto Precharge

CLK

CMD

1) Normal Write (BL=4)

Note 3,4
Auto Precharge Starts

3) Read (BL=4)

CLK

CMD

DQ(CL2)

DQ(CL3)

Note 3
Auto Precharge Starts

Pixel

CLK

CMD

PRE

2) Block Write

BPL

Note 1

CLK

CMD

(CL 2, 3)

2) Block Write

Pixel

BPL

K4G163222A

CMOS SGRAM

1. Active power down : one or more bank active state.

2. Precharge power down : both bank precharge state.

3. The auto refresh is the same as CBR refresh of conventional DRAM.

No precharge commands are required after Auto Refresh command.

During tRC from auto refresh command, any other command can not be accepted.

4. Before executing auto/self refresh command, both banks must be idle state.

5. (S)MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.

6. During self refresh mode, refresh interval and refresh operation are perfomed internally.

After self refresh entry, self refresh mode is kept while CKE is LOW.

During self refresh mode, all inputs expect CKE will be don

t cared, and outputs will be in Hi-Z state.

During tRC from self refresh exit command, any other command can not be accepted.

Before/After self refresh mode, burst auto refresh cycle (2K cycles) is recommended.

Note 1

Note 5

Internal

CLK

Note 2

Note 4

10. Clock Suspend Exit & Power Down Exit

1) Clock Suspend (=Active Power Down) Exit

2) Power Down (=Precharge Power Down) Exit

CLK

CKE

CMD

Internal

CLK

CKE

CMD

11. Auto Refresh & Self Refresh

1) Auto Refresh

Note 3

2) Self Refresh

Note 6

CLK

CMD

CKE

CLK

CMD

CKE

*Note :

NOP ACT

CMD

PRE

CMD

PRE

K4G163222A

CMOS SGRAM

12. About Burst Type Control

Basic

MODE

Sequential Counting

At MRS A

= "0". See the BURST SEQUENCE TABLE. (BL=4,8)

BL=1, 2, 4, 8 and full page wrap around.

Interleave Counting

At MRS A

= "1". See the BURST SEQUENCE TABLE. (BL=4,8)

BL=4, 8. At BL=1, 2 Interleave Counting = Sequential Counting

Pseudo-

MODE

Pseudo-

Decrement Sequential

Counting

At MRS A

= "1".(See to Interleave Counting Mode)

Starting Address LSB 3 bits A

0-2

should be "000" or "111".@BL=8.

-- if LSB="000" : Increment Counting.
-- if LSB="111" : Decrement Counting.
For Example,(Assume Addresses except LSB 3 bits are all 0, BL=8)
-- @ write, LSB="000", Accessed Column in order 0-1-2-3-4-5-6-7
-- @ read, LSB="111", Accessed Column in order 7-6-5-4-3-2-1-0
At BL=4, same applications are possible. As above example, at Interleave Counting mode,
by confining starting address to some values, Pseudo-Decrement Counting Mode can be
realized. See the BURST SEQUENCE TABLE carefully.

Pseudo-

Binary Counting

At MRS A

= "0".(See to Sequential Counting Mode)

0-2

= "111".(See to Full Page Mode)

Using Full Page Mode and Burst Stop Command, Binary Counting Mode can be realized.
-- @ Sequential Counting, Accessed Column in order 3-4-5-6-7-1-2-3(BL=8)
-- @ Pseudo-Binary Counting,
Accessed Column in order 3-4-5-6-7-8-9-10(Burst Stop command)
Note. The next column address of 256 is 0.

Random

MODE

Random column Access

CCD

= 1 CLK

Every cycle Read/Write Command with random column address can realize
Random Column Access.
That is similar to Extended Data Out (EDO) Operation of conventional DRAM.

13. About Burst Length Control

Basic

MODE

At MRS A

2,1,0

= "000".

At auto precharge, t

RAS

should not be violated.

At MRS A

2,1,0

= "001".

At auto precharge, t

RAS

should not be violated.

At MRS A

2,1,0

= "010".

At MRS A

2,1,0

= "011".

Full Page

At MRS A

2,1,0

= "111".

Wrap around mode(Infinite burst length)should be stopped by burst stop,
RAS interrupt or CAS interrupt.

Special

MODE

BRSW

At MRS A

= "1".

Read burst =1, 2, 4, 8, full page/write Burst =1
At auto precharge of write, t

RAS

should not be violated.

Block Write

8 Column Block Write. LSB A0-2 are ignored. Burst length=1.
t

BWC

should not be violated.

At auto precharge, t

RAS

should not be violated.

Random

MODE

Burst Stop

BDL

= 1, Valid DQ after burst stop is 1, 2 for CL=2, 3 respectively

Using burst stop command, it is possible only at full page burst length.

Interrupt

MODE

RAS Interrupt

(Interrupted by Precharge)

Before the end of burst, Row precharge command of the same bank
stops read/write burst with Row precharge.
t

RDL

= 2 with DQM, valid DQ after burst stop is 1, 2 for CL= 2, 3 respectively

During read/write burst with auto precharge, RAS interrupt cannot be issued.

CAS Interrupt

Before the end of burst, new read/write stops read/write burst and starts new
read/write burst or block write.
During read/write burst with auto precharge, CAS interrupt can not be issued.

K4G163222A

CMOS SGRAM

I/O(=DQ)

31 24

23 16

15 8

7 0

External Data-in

1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0

DQMi

DQM

Mask Register

0 1 1 1 1 1 1 0

1 0 1 1 1 1 1 1

0 1 1 1 1 1 0 1

0 1 1 1 0 1 1 0

Before Write

0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1

After Write

0 1 1 1 1 1 1 0

1 0 1 1 1 1 1 1

1 0 0 0 0 0 1 0

1 1 1 1 1 1 1 1

14. Mask Functions

1) Normal Write
I/O masking : By Mask at Write Per Bit Mode, the selected bit planes keep the original data.
If bit plane 0, 3, 7, 9, 15, 22, 24, and 31 keep the original value.
i) STEP
- SMRS(LMR) :Load mask[31-0]="0111, 1110, 1011,1111, 0111, 1101, 0111, 0110"
- Row Active with DSF "H" :Write Per Bit Mode Enable
- Perform Normal Write.
i) ILLUSTRATION

I/O(=DQ)

31 24

23 16

15 8

7 0

DQMi

DQM

Color Register

Color3=Blue

Color2=Green

Color1=Yellow

Color0=Red

Before

Block

Write

(Pixel

data)

000

White DQ

001

White DQ

010

White DQ

011

White DQ

100

White DQ

101

White DQ

110

White DQ

111

White DQ

After

Block

Write

000

Blue

Green

Yellow

White

001

Blue

Green

White

010

Blue

White

Yellow

White

011

White

Green

Yellow

White

100

Blue

Green

Yellow

White

101

Blue

Green

White

110

Blue

White

Yellow

White

111

White

Green

Yellow

White

2) Block Write
Pixel masking : By Pixel Data issued through DQ pin, the selected pixels keep the original data.
See PIXEL TO DQ MAPPING TABLE.
If Pixel 0, 4, 9, 13, 18, 22, 27 and 31 keep the original white color.

Assume 8bpp,
White = "0000,0000", Red="1010,0011", Green = "1110,0001", Yellow = "0000,1111", Blue = "1100,0011"
i) STEP
- SMRS(LCR) :Load color(for 8bpp, through x32 DQ color0-3 are loaded into color registers)
Load(color3, color2, color1, color0) = (Blue, Green, Yellow, Red)
= "1100,0011, 1110, 0001, 0000, 1111, 1010, 0011"
- Row Active with DSF "L" : I/O Mask by Write Per Bit Mode Disable
- Block write with DQ[31-0] = "0111, 0111, 1011, 1011, 1101, 1101, 1110, 1110"
i) ILLUSTRATION

1. DQM byte masking.
2. At normal write, ONE column is selected among columns decorded by A

2-0

(000-111).

At block write, instead of ignored address A

2-0

, DQ

0-31

control each pixel.

Note 1

Note 2

*Note :

K4G163222A

CMOS SGRAM

I/O(=DQ)

31 24

23 16

15 8

7 0

Color Register

Blue

1 1 0 0 0 0 1 1

Green

1 1 1 0 0 0 0 1

Yellow

0 0 0 0 1 1 1 1

Red

1 0 1 0 0 0 1 1

DQMi

DQM

Mask Register

1 1 1 1 1 1 1 1

1 1 0 1 1 1 0 1

0 1 0 0 0 0 1 0

0 1 1 1 0 1 1 0

Before Write

Yellow

0 0 0 0 1 1 1 1

Yellow

0 0 0 0 1 1 1 1

Green

1 1 1 0 0 0 0 1

White

0 0 0 0 0 0 0 0

After Write

Blue

1 1 0 0 0 0 1 1

Blue

1 1 0 0 0 0 1 1

Red

1 0 1 0 0 0 1 1

White

0 0 0 0 0 0 0 0

(Continued)

Pixel and I/O masking : By Mask at Write Per Bit Mode, the selected bit planes keep the original data.
By Pixel Data issued through DQ pin, the selected pixels keep the original data.
See PIXEL TO DQ MAPPING TABLE.

Assume 8bpp,
White = "0000,0000", Red="1010,0011", Green ="1110,0001", Yellow ="0000,1111", Blue ="1100,0011"

i) STEP
- SMRS(LCR) : Load color(for 8bpp, through x 32 DQ color0-3 are loaded into color registers)
Load(color3, color2, color1, color0) = (Blue, Green, Yellow, Red)
= "1100,0011,1110,0001,0000,1111,1010,0011"
- SMRS(LMR ): Load mask. Mask[31-0] ="1111,1111,1101,1101, 0100,0010,0111,0110"
--> Byte 3 : No I/O Masking ; Byte 2 : I/O Masking ; Byte 1 : I/O and Pixel Masking ; Byte 0 : DQM Byte Masking
- Row Active with DSF "H" : I/O Mask by Write Per Bit Mode Enable
- Block Write with DQ[31-0] = "0111,0111,1111,1111,0101,0101,1110,1110" (Pixel Mask)

i) ILLUSTRATION

Note 2 Note 1

I/O(=DQ)

31 24

23 16

15 8

7 0

DQMi

DQM

Color Register

Color3=Blue

Color2=Green

Color1=Yellow

Color0=Red

Before

Block

Write

(Pixel

data)

000

Yellow DQ

Green DQ

White DQ

001

Yellow DQ

Green DQ

White DQ

010

Yellow DQ

Green DQ

White DQ

011

Yellow DQ

Green DQ

White DQ

100

Yellow DQ

Green DQ

White DQ

101

Yellow DQ

Green DQ

White DQ

110

Yellow DQ

Green DQ

White DQ

111

Yellow DQ

Green DQ

White DQ

After

Block

Write

000

Blue

Blue

Red

White

001

Blue

Blue

Green

White

010

Blue

Blue

Red

White

011

Yellow

Blue

Green

White

100

Blue

Blue

Red

White

101

Blue

Blue

Green

White

110

Blue

Blue

Red

White

111

Yellow

Blue

Green

White

1. DQM byte masking.
2. At normal write, ONE column is selected among columns decorded by A

2-0

(000-111).

At block write, instead of ignored address A

2-0

, DQ

0-31

control each pixel.

PIXEL MASK

I/O MASK

PIXEL & I/O MASK

BYTE MASK

*Note :

Note 1

K4G163222A

CMOS SGRAM

1. All input can be don't care when CS is high at the CLK high going edge.
2. Bank active & read/write are controlled by A

A10

Active & Read/Write

Bank A

Bank B

A10

Operation

Disable auto precharge, leave bank A active at end of burst.

Disable auto precharge, leave bank B active at end of burst.

Enable auto precharge, precharge bank A at end of burst.

Enable auto precharge, precharge bank B at end of burst.

Precharge

Bank A

Bank B

Both Bank

DSF

Operation

Bank A row active, disable write per bit function for bank A

Bank A row active, enable write per bit function for bank A

Bank B row active, disable write per bit function for bank B

Bank B row active, enable write per bit function for bank B

DSF

Operation

Minimum cycle time

Normal write

CCD

Block write

BWC

3. Enable and disable auto precharge function are controlled by A

in read/write command.

4. A

and A

control bank precharge when precharge command is asserted.

5. Enable and disable Write-per Bit function are controlled by DSF in Row Active command.

6. Block write/normal write is controlled by DSF.

*Note :

K4G163222A

CMOS SGRAM

Read & Write Cycle at Same Bank @Burst Length=4

HIGH

Row Active

(A-Bank)

Precharge

(A-Bank)

Row Active

(A-Bank)

Write

(A-Bank)

Precharge

(A-Bank)

*Note :

1. Minimum row cycle times is required to complete internal DRAM operation.

2. Row precharge can interrupt burst on any cycle. [CAS Latency - 1] valid output data available after Row

enters precharge. Last valid output will be Hi-Z after

SHZ

from the clcok.

3. Access time from Row address.

RCD

+ CAS latency - 1) +

SAC

4. Ouput will be Hi-Z after the end of burst. (1, 2, 4, & 8). At Full page bit burst, burst is wrap-around.

5. For -55/60/70/80, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code
"NV". From the next generation, tRDL will be only 2CLK for every clock frequency.

Read

(A-Bank)

*Note 1

RCD

*Note 2

RDL

SHZ

*Note 4

SHZ

*Note 4

RAC

*Note 3

SAC

RAC

*Note 3

/AP

ADDR

CAS

RAS

CKE

CLOCK

Qa0

Qa1

Qa2

Qa3

Qa0

Qa1

Qa2

Qa3

Db0

Db1

Db2

Db3

Db0

Db1

Db2

Db3

Ca0

Cb0

DQM

DSF

: Don

t care

(CL=2)

(CL=3)

*Note 5

K4G163222A

CMOS SGRAM

Write Interrupted by Precharge Command & Write Burst Stop Cycle (@ Full page Only)

Row Active

(A-Bank)

Write

(A-Bank)

Precharge

(A-Bank)

Write

(A-Bank)

*Note 3

tBDL

1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.

2. Data-in at the cycle of burst stop command cannot be written into the corresponding memory cell.

It is defined by AC parameter of

BDL

(=1CLK).

3. Data-in at the cycle of interrupted by precharge cannot be written into the corresponding memory cell.

It is defined by AC parameter of

RDL

(=2CLK).

DQM at write interrupted by precharge command is needed to ensure

RDL

of 2CLK.

DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.

Input data after Row precharge cycle will be masked internally.

4. Burst stop is valid only at full page burst length.

HIGH

RDL

ADDR

CAS

RAS

CKE

CLOCK

DQM

/AP

DAa0

DAa1

DAa2

DAa3 DAa4

DAb0

DAb1

DAb2

DAb3 DAb4

DAb5

RAa

CAa

CAb

RAa

DSF

*Note 1

*Note 2

Burst Stop

*Note :

: Don

t care

*Note 5

K4G163222A

CMOS SGRAM

FUNCTION TRUTH TABLE(TABLE 1)

Current

State

RAS

CAS

DSF

)

ADDR

ACTION

NOTE

IDLE

NOP

ILLEGAL

Row Active ; Latch Row Address ; Non-IO Mask

Row Active ; Latch Row Address ; IO Mask

NOP

ILLEGAL

Auto Refresh or Self Refresh

ILLEGAL

OP Code

Mode Register Access

OP Code

Special Mode Register Access

Row

Active

NOP

ILLEGAL

CA,AP

Begin Read ; Latch CA ; Determine AP

ILLEGAL

CA,AP

Begin Write ;Latch CA ; Determine AP

CA,AP

Block Write ;Latch CA ; Determine AP

ILLEGAL

Precharge

ILLEGAL

OP Code

Special Mode Register Access

Read

NOP(Continue Burst to End --> Row Active)

Term burst --> Row active

ILLEGAL

CA,AP

Term burst ; Begin Read ; Latch CA ; Determine AP

ILLEGAL

CA,AP

Term burst ; Begin Write ; Latch CA ; Determine AP

CA.AP

Term burst ; Block Write ; Latch CA ; Determine AP

ILLEGAL

Term Burst ; Precharge timing for Reads

ILLEGAL

Write

NOP(Continue Burst to End --> Row Active)

Term burst --> Row active

ILLEGAL

CA,AP

Term burst ; Begin Read ; Latch CA ; Determine AP

ILLEGAL

CA,AP

Term burst ; Begin Write ; Latch CA ; Determine AP

CA,AP

Term burst ; Block Write ; Latch CA ; Determine AP

K4G163222A

CMOS SGRAM

FUNCTION TRUTH TABLE(TABLE 1, Continued)

Current

State

RAS

CAS

DSF

)

ADDR

ACTION

NOTE

Write

ILLEGAL

Term Burst : Precharge timing for Writes

ILLEGAL

Read with

Auto

Precharge

NOP(Continue Burst to End --> Precharge)

ILLEGAL

CA,AP

ILLEGAL

CA,AP

ILLEGAL

RA,PA

ILLEGAL

Write with

Auto

Precharge

NOP(Continue Burst to End --> Precharge)

ILLEGAL

CA,AP

ILLEGAL

CA,AP

ILLEGAL

RA,PA

ILLEGAL

Precharging

NOP --> Idle after

ILLEGAL

CA,AP

ILLEGAL

NOP --> Idle after

ILLEGAL

Block

Write

Recovering

NOP --> Row Active after

BWC

NOP --> Row Active after

BWC

ILLEGAL

CA,AP

ILLEGAL

Term Block Write : Precharge timing for Block Write

ILLEGAL

Row

Activating

NOP --> Row Active after

RCD

NOP --> Row Active after

RCD

ILLEGAL

CA,AP

ILLEGAL

Refreshing

NOP --> Idle after

ILLEGAL

K4G163222A

CMOS SGRAM

1. All entries assume that CKE was active(High) during the preceding clock cycle and the current clock cycle.

2. Illegal to bank in specified state ; Function may be legal in the bank indicated by BA, depending on the state of that bank.

3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.

4. NOP to bank precharging or in idle state. May precharge bank indicated by BA(and PA).

5. Illegal if any banks is not idle.

6. Legal only if all banks are in idle or row active state.

RA = Row Address(A

)

NOP = No Operation Command

BA = Bank Address(A

)

CA = Column Address(A

)

PA = Precharge All(A

)

AP = Auto Precharge(A

)

FUNCTION TRUTH TABLE for CKE(TABLE 2)

Current

State

CKE

n-1

CKE

RAS

CAS

DSF

ADDR

ACTION

NOTE

Self

Refresh

INVALID

Exit Self Refresh --> ABI after

ILLEGAL

NOP(Maintain Self Refresh)

Both

Bank

Precharge

Power

Down

INVALID

Exit Power Down --> ABI

ILLEGAL

NOP(Maintain Power Down Mode)

All

Banks

Idle

Refer to Table 1

Enter Power Down

ILLEGAL

Row (& Bank) Active

Enter Self Refresh

OP Code

Mode Register Access

OP Code

Special Mode Register Access

NOP

Any State

other than

Listed

Above

Refer to Operations in Table 1

Begin Clock Suspend next cycle

Exit Clock Suspend next cycle

Maintain clock Suspend

7. After CKE

s low to high transition to exist self refresh mode. And a time of

(min) has to be elapse after CKE

s low to high

transition to issue a new command.

8. CKE low to high transition is asynchronous as if restarts internal clock.

A minimum setup time "

+ one clock" must be satisfied before any command other than exit.

9. Power-down and self refresh can be entered only from the all banks idle state.

10. Must be a legal command.

FUNCTION TRUTH TABLE (TABLE 1, Continued)

ABBREVIATIONS

*Note :

ABBREVIATIONS : ABI = All Banks Idle

*Note :

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: K4G163222A-PC/L70