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REV. 0.3 Jan.31. 2001
128Mb D-die(x4/8) DDR SDRAM
DDR SDRAM Specification
Version 0.3
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REV. 0.3 Jan.31. 2001
128Mb D-die(x4/8) DDR SDRAM
128Mb D-die(x4/8) Revision History
Version 0 (November, 2001)
- First version for internal review
Version 0.1 (December, 2001)
- Changed spec. from target to preliminry
- updated preliminary IDD value
Version 0.2 (January, 2002)
- updated IDD value.
Version 0.3 (January, 2002)
- Changed final version.
- Added tRAP(Active to read with auto precharge command)
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REV. 0.3 Jan.31. 2001
128Mb D-die(x4/8) DDR SDRAM
Contents
Revision History
General Information
1. Key Features
1.1 Features
1.2 Operating Frequencies
2. Package Pinout & Dimension
2.1 Package Pintout
2.2 Input/Output Function Description
2.3 66 Pin TSOP(II)/MS-024FC Package Physical Dimension
3. Functional Description
3.1 Simplified State Diagram
3.2 Basic Functionality
3.2.1 Power-Up Sequence
3.2.2 Mode Register Definition
3.2.2.1 Mode Register Set(MRS)
3.2.2.2 Extended Mode Register Set(EMRS)
3.2.3 Precharge
3.2.4 No Operation(NOP) & Device Deselect
3.2.5 Row Active
3.2.6 Read Bank
3.2.7 Write Bank
3.3 Essential Functionality for DDR SDRAM
3.3.1 Burst Read Operation
3.3.2 Burst Write Operation
3.3.3 Read Interrupted by a Read
3.3.4 Read Interrupted by a Write & Burst Stop
3.3.5 Read Interrupted by a Precharge
3.3.6 Write Interrupted by a Write
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REV. 0.3 Jan.31. 2001
128Mb D-die(x4/8) DDR SDRAM
3.3.7 Write Interrupted by a Read & DM
3.3.8 Write Interrupted by a Precharge & DM
3.3.9 Burst Stop
3.3.10 DM masking
3.3.11 Read With Auto Precharge
3.3.12 Write With Auto Precharge
3.3.13 Auto Refresh & Self Refresh
3.3.14 Power Down
4. Command Truth Table
5. Functional Truth Table
6. Absolute Maximum Rating
7. DC Operating Conditions & Specifications
7.1 DC Operating Conditions
7.2 DC Specifications
8. AC Operating Conditions & Timming Specification
8.1 AC Operating Conditions
8.2 AC Overshoot/Undershoot specification
8.1.1 Overshoot/Undershoot specification for Address and Control Pins
8.1.2 Overshoot/Undershoot specification for Data Pins
8.3 AC Timming Parameters & Specification(DDR266/200)
8.4 AC Timming Parameters & Specification(DDR333)
9. AC Operating Test Conditions
10. Input/Output Capacitance
11. IBIS: I/V Characteristics for Input and Output Buffers
11.1 Normal strength driver
11.2 Half strength driver
Timing Diagram
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REV. 0.3 Jan.31. 2001
128Mb D-die(x4/8) DDR SDRAM
Table 1 : Operating frequency and DLL jitter
Table 2. : Column address configurtion
Table 3 : Input/Output function description
Table 4 : Burst address ordering for burst length
Table 5 : Bank selection for precharge by bank address bits
Table 6 : Operating description when new command asserted while
read with auto precharge is issued
Table 7 : Operating description when new command asserted while
write with auto precharge is issued
Table 8 : Command truth table
Table 9-1 : Functional truth table
Table 9-2 : Functional truth table (contiued)
Table 9-3 : Functional truth table (contiued)
Table 9-4 : Functional truth table (contiued)
Table 9-5 : Functional truth table (cotinued)
Table 10 : Absolute maximum raings
Table 11 : DC operating condtion
Table 12 : DC specification
Table 13 : AC operating condition
Table 14 : Overshoot/Undershoot specification for Address and Control Pins
Table 15 : Overshoot/Undershoot specification for Data Pins
Table 16 : AC timing parameters and specifications(DDR266/200)
Table 17 : AC operating test conditions
Table 18 : Input/Output capacitance
Table 19 : Pull down and pull up current values(For normal strength driver)
Table 20 : Pull down and pull up current values(For half strength driver)
List of tables
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