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Электронный компонент: K4H510438C-UCB3

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Rev. 1.1 June. 2005
DDR SDRAM
DDR SDRAM 512Mb C-die (x4, x8, x16)
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ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
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512Mb C-die DDR SDRAM Specification
66 TSOP-II with Pb-Free
(RoHS compliant)
Rev. 1.1 June. 2005
DDR SDRAM
DDR SDRAM 512Mb C-die (x4, x8, x16)
Table of Contents
1.0 Key Features .............................................................................................................................. 4
2.0 Ordering Information ................................................................................................................ 4
3.0 Operating Frequencies............................................................................................................... 4
4.0 Pin Description .......................................................................................................................... 5
5.0 Package Physical Dimension ................................................................................................... 6
6.0 Block Diagram (64Mbit x4 / 32Mbit x8 I/O x4 Banks) ............................................................... 7
7.0 Input/Output Function Description ........................................................................................... 8
8.0 Command Truth Table ............................................................................................................... 9
9.0 General Description...................................................................................................................10
10.0 Absolute Maximum Rating .....................................................................................................10
11.0 DC Operating Conditions ........................................................................................................10
12.0 DDR SDRAM Spec Items & Test Conditions .........................................................................11
13.0 Input/Output Capacitance ......................................................................................................11
14.0 Detailed test condition for DDR SDRAM IDD1 & IDD7A ......................................................12
15.0 DDR SDRAM IDD spec table ..................................................................................................13
16.0 AC Operating Conditions .......................................................................................................14
17.0 AC Overshoot/Undershoot specification for Address and Control Pins ...........................14
18.0 Overshoot/Undershoot specification for Data, Strobe and Mask Pins...............................15
19.0 AC Timming Parameters & Specifications ...........................................................................16
20.0 System Characteristics for DDR SDRAM ............................................................................. 17
21.0 Component Notes ................................................................................................................... 18
22.0 System Notes ..........................................................................................................................20
23.0 IBIS : I/V Characteristics for Input and Output Buffers ........................................................21
Rev. 1.1 June. 2005
DDR SDRAM
DDR SDRAM 512Mb C-die (x4, x8, x16)
Revision History
Revision
Month
Year
History
0.0
April
2004
- First version for internal review
0.1
August
2004
- Preliminary spec release
0.2
October
2004
- Changed IDD current
1.0
January
2005
- Release the Rev. 1.0 spec
1.1
June
2005
- Changed master format.
Rev. 1.1 June. 2005
DDR SDRAM
DDR SDRAM 512Mb C-die (x4, x8, x16)
VDD : 2.5V 0.2V, VDDQ : 2.5V 0.2V for DDR266, 333
VDD : 2.6V 0.1V, VDDQ : 2.6V 0.1V for DDR400
Double-data-rate architecture; two data transfers per clock cycle
Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16)
Four banks operation
Differential clock inputs(CK and CK)
DLL aligns DQ and DQS transition with CK transition
MRS cycle with address key programs
-. Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
Data I/O transactions on both edges of data strobe
Edge aligned data output, center aligned data input
LDM,UDM for write masking only (x16)
DM for write masking only (x4, x8)
Auto & Self refresh
7.8us refresh interval(8K/64ms refresh)
Maximum burst refresh cycle : 8
66pin TSOP II
Pb-Free
package
RoHS compliant
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2.0)
B0(DDR266@CL=2.5)
Speed @CL2
-
133MHz
133MHz
100MHz
Speed @CL2.5
166MHz
166MHz
133MHz
133MHz
Speed @CL3
200MHz
-
-
-
CL-tRCD-tRP
3-3-3
2.5-3-3
2-3-3
2.5-3-3
Part No.
Org.
Max Freq.
Interface
Package
K4H510438C-UC/LB3
128M x 4
B3(DDR333@CL=2.5)
SSTL2
66pin TSOP II
K4H510438C-UC/LA2
A2(DDR266@CL=2)
K4H510438C-UC/LB0
B0(DDR266@CL=2.5)
K4H510838C-UC/LCC
64M x 8
CC(DDR400@CL=3)
SSTL2
66pin TSOP II
K4H510838C-UC/LB3
B3(DDR333@CL=2.5)
K4H510838C-UC/LA2
A2(DDR266@CL=2)
K4H510838C-UC/LB0
B0(DDR266@CL=2.5)
K4H511638C-UC/LCC
32M x 16
CC(DDR400@CL=3)
SSTL2
66pin TSOP II
K4H511638C-UC/LB3
B3(DDR333@CL=2.5)
K4H511638C-UC/LA2
A2(DDR266@CL=2)
K4H511638C-UC/LB0
B0(DDR266@CL=2.5)
1.0 Key Features
2.0 Ordering Information
3.0 Operating Frequencies
Rev. 1.1 June. 2005
DDR SDRAM
DDR SDRAM 512Mb C-die (x4, x8, x16)
DM is internally loaded to match DQ and DQS identically.
Row & Column address configuration
Organization
Row Address
Column Address
128Mx4
A0~A12
A0-A9, A11, A12
64Mx8
A0~A12
A0-A9, A11
32Mx16
A0~A12
A0-A9
4.0 Pin Description
512Mb TSOP-II Package Pinout
V
DD
1
66Pin TSOPII
(400mil x 875mil)
DQ
0
2
V
DDQ
3
NC
4
DQ
1
5
V
SSQ
6
NC
7
DQ
2
8
V
DDQ
9
NC
10
DQ
3
11
V
SSQ
12
BA
0
20
CS
19
RAS
18
CAS
17
WE
16
NC
15
V
DDQ
14
NC
13
V
DD
27
A
3
26
A
2
25
A
1
24
A
0
23
AP/A
10
22
BA
1
21
V
SS
54
DQ
7
53
V
SSQ
52
NC
51
DQ
6
50
V
DDQ
49
NC
48
DQ
5
47
V
SSQ
46
NC
45
DQ
4
44
V
DDQ
43
A
11
35
36
CKE
37
CK
38
DM
39
V
REF
40
V
SSQ
41
NC
42
V
SS
55
A
4
56
A
5
57
A
6
58
A
7
59
A
8
60
A
9
34
(0.65mm Pin Pitch)
33
32
31
30
29
28
61
62
63
64
65
66
NC
NC
NC
NC
NC
V
DD
NC
DQS
NC
V
SS
CK
NC
A
12
V
SS
NC
V
SSQ
NC
DQ
3
V
DDQ
NC
NC
V
SSQ
NC
DQ
2
V
DDQ
A
11
CKE
CK
DM
V
REF
V
SSQ
NC
V
SS
A
4
A
5
A
6
A
7
A
8
A
9
NC
DQS
NC
V
SS
CK
NC
A
12
V
DD
NC
V
DDQ
NC
DQ
0
V
SSQ
NC
NC
V
DDQ
NC
DQ
1
V
SSQ
BA
0
CS
RAS
CAS
WE
NC
V
DDQ
NC
V
DD
A
3
A
2
A
1
A
0
AP/A
10
BA
1
NC
NC
NC
NC
NC
V
DD
Bank Address
BA0~BA1
Auto Precharge
A10
128Mb x 4
64Mb x 8
V
DD
DQ
0
V
DDQ
DQ
1
DQ
2
V
SSQ
DQ
3
DQ
4
V
DDQ
DQ
5
DQ
6
V
SSQ
BA
0
CS
RAS
CAS
WE
LDM
V
DDQ
DQ
7
V
DD
A
3
A
2
A
1
A
0
AP/A
10
BA
1
NC
LDQS
NC
NC
NC
V
DD
V
SS
DQ
15
V
SSQ
DQ
14
DQ
13
V
DDQ
DQ
12
DQ
11
V
SSQ
DQ
10
DQ
9
V
DDQ
A
11
CKE
CK
UDM
V
REF
V
SSQ
DQ
8
V
SS
A
4
A
5
A
6
A
7
A
8
A
9
NC
UDQS
NC
V
SS
CK
NC
A
12
32Mb x 16