DDR SDRAM

DDR SDRAM 256Mb E-die (x4, x8)

Rev. 1.1 September. 2003

· 200MHz Clock, 400Mbps data rate.
· VDD= +2.6V + 0.10V, VDDQ= +2.6V + 0.10V
· Double-data-rate architecture; two data transfers per clock cycle
· Bidirectional data strobe [DQ] (x4,x8)
· Four banks operation
· Differential clock inputs(CK and CK)
· DLL aligns DQ and DQS transition with CK transition
· MRS cycle with address key programs

-. Read latency 3 (clock) for DDR400 , 2.5 (clock) for DDR333
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)

· All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
· Data I/O transactions on both edges of data strobe
· Edge aligned data output, center aligned data input
· DM for write masking only (x4, x8)
· Auto & Self refresh
· 7.8us refresh interval(8K/64ms refresh)
· Maximum burst refresh cycle : 8
· 60Ball FBGA package

Key Features

Ordering Information

Part No.

Org.

Max Freq.

Interface

Package

K4H560438E-GCCC

64M x 4

CC(DDR400@CL=3)

SSTL2

60 FBGA

K4H560438E-GCC4

C4(DDR400@CL=3)

K4H560838E-GCCC

32M x 8

CC(DDR400@CL=3)

SSTL2

60 FBGA

K4H560838E-GCC4

C4(DDR400@CL=3)

*CL : CAS Latency

Operating Frequencies

- CC(DDR400@CL=3)

- C4(DDR400@CL=3)

Speed @CL3

200MHz

CL-tRCD-tRP

3 - 3 - 3

3 - 4 - 4

DDR SDRAM

DDR SDRAM 256Mb E-die (x4, x8)

Rev. 1.1 September. 2003

Ball Description

DM is internally loaded to match DQ and DQS identically.

Row & Column address configuration

Organization

Row Address

Column Address

64Mx4

A0~A12

A0-A9, A11

32Mx8

A0~A12

A0-A9

VSSQ

VREF

VDDQ

VSSQ

VDDQ

VSSQ

VSS

A12

A11

VSS

DQ3

DQ2

DQS

CKE

VSS

VDD

DQ0

DQ1

RAS

BA1

VDD

VSSQ

VDDQ

VSSQ

VDDQ

VDD

CAS

BA0

A10/AP

VDDQ

VSSQ

VREF

DQ7

VDDQ

VSSQ

VDDQ

VSSQ

VSS

A12

A11

VSS

DQ6

DQ5

DQ4

DQS

CKE

VSS

VDD

DQ1

DQ2

DQ3

RAS

BA1

VDD

DQ0

VSSQ

VDDQ

VSSQ

VDDQ

VDD

CAS

BA0

A10/AP

VDDQ

32M x 8bit

64M x 4bit

(

Bottom View

)

DDR SDRAM

DDR SDRAM 256Mb E-die (x4, x8)

Rev. 1.1 September. 2003

SYMBOL

TYPE

DESCRIPTION

CK, CK

Input

Clock : CK and CK are differential clock inputs. All address and control input signals are sam-
pled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to
both edges of CK. Internal clock signals are derived from CK/CK.

CKE

Input

Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN
(row ACTIVE in any bank). CKE is synchronous for all functions except for disabling outputs,
which is achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled dur-
ing power-down and self refresh modes, providing low standby power. CKE will recognize an
LVCMOS LOW level prior to VREF being stable on power-up.

Input

Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command
decoder. All commands are masked when CS is registered HIGH. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the command code.

RAS, CAS, WE

Input

Command Inputs : RAS, CAS and WE (along with CS) define the command being entered.

Input

Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH along with that input data during a WRITE access. DM is sampled on both
edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS
loading. DM may be driven high, low, or floating during READs.

BA0, BA1

Input

Bank Addres Inputs : BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-
CHARGE command is being applied.

A [0 : 12]

Input

Address Inputs : Provide the row address for ACTIVE commands, and the column address and
AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the mem-
ory array in the respective bank. A10 is sampled during a PRECHARGE command to deter-
mine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If
only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also
provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which
mode register is loaded during the MODE REGISTER SET command (MRS or EMRS).

I/O

Data Input/Output : Data bus

DQS

I/O

Data Strobe : Output with read data, input with write data. Edge-aligned with read data, cen-
tered in write data. Used to capture write data.

No Connect : No internal electrical connection is present.

VDDQ

Supply

DQ Power Supply : +2.6V

0.1V.

VSSQ

Supply

DQ Ground.

VDD

Supply

Power Supply : +2.6V

0.1V (device specific).

VSS

Supply

Ground.

VREF

Input

SSTL_2 reference voltage.

Input/Output Function Description

DDR SDRAM

DDR SDRAM 256Mb E-die (x4, x8)

Rev. 1.1 September. 2003

Command Truth Table

(V=Valid, X=Don

t Care, H=Logic High, L=Logic Low)

COMMAND

CKEn-1 CKEn

RAS

CAS

BA0,1 A10/AP

A0 ~ A9,

A11,A12

Note

Extended MRS

OP CODE

1, 2

Mode Register Set

OP CODE

1, 2

Refresh

Auto Refresh

Self
Refresh

Entry

Exit

Bank Active & Row Addr.

Row Address

Read &
Column Address

Auto Precharge Disable

Column

Address

Auto Precharge Enable

Write &
Column Address

Auto Precharge Disable

Column

Address

Auto Precharge Enable

4, 6

Burst Stop

Precharge

Bank Selection

All Banks

Active Power Down

Entry

Exit

Precharge Power Down Mode

Entry

Exit

DM(UDM/LDM for x16 only)

No operation (NOP) : Not defined

1. OP Code : Operand Code. A

~ A

& BA

~ BA

: Program keys. (@EMRS/MRS)

2. EMRS/MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA

~ BA

: Bank select addresses.

If both BA

and BA

are "Low" at read, write, row active and precharge, bank A is selected.

If BA

is "High" and BA

is "Low" at read, write, row active and precharge, bank B is selected.

If BA

is "Low" and BA

is "High" at read, write, row active and precharge, bank C is selected.

If both BA

and BA

are "High" at read, write, row active and precharge, bank D is selected.

5. If A

/AP is "High" at row precharge, BA

and BA

are ignored and all banks are selected.

6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t

after the end of burst.

7. Burst stop command is valid at every burst length.
8. DM(x4/8) sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges
(Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.

Note :

DDR SDRAM

DDR SDRAM 256Mb E-die (x4, x8)

Rev. 1.1 September. 2003

16M x 4Bit x 4 Banks / 8M x 8Bit x 4 Banks Banks Double Data Rate SDRAM

The K4H560438E / K4H560838E / is 268,435,456 bits of double data rate synchronous DRAM organized as 4x 16,785,216 / 4x
8,388,608 words by 4/ 8bits, fabricated with SAMSUNG

s high performance CMOS technology. Synchronous features with Data Strobe

allow extremely high performance up to 333Mb/s per pin. I/O transactions are possible on both edges of DQS. Range of operating fre-
quencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance mem-
ory system applications.

General Description

Absolute Maximum Rating

Parameter

Symbol

Value

Unit

Voltage on any pin relative to V

, V

OUT

-0.5 ~ 3.6

Voltage on V

& V

DDQ

supply relative to V

, V

DDQ

-1.0 ~ 3.6

Storage temperature

STG

-55 ~ +150

Power dissipation

1.5

Short circuit current

Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC Operating Conditions

Recommended operating conditions(Voltage referenced to V

=0V, T

=0 to 70

Parameter

Symbol

Min

Max

Unit

Note

Supply voltage(for device with a nominal V

of 2.5V)

2.5

2.7

I/O Supply voltage

DDQ

2.5

2.7

I/O Reference voltage

REF

0.49*VDDQ

0.51*VDDQ

I/O Termination voltage(system)

REF

-0.04

REF

+0.04

Input logic high voltage

(DC)

REF

+0.15

DDQ

+0.3

Input logic low voltage

(DC)

-0.3

REF

-0.15

Input Voltage Level, CK and CK inputs

(DC)

-0.3

DDQ

+0.3

Input Differential Voltage, CK and CK inputs

(DC)

0.36

DDQ

+0.6

V-I Matching: Pullup to Pulldown Current Ratio

VI(Ratio)

0.71

1.4

Input leakage current

-2

Output leakage current

-5

Output High Current(Normal strengh driver) ;V

OUT

= V

+ 0.84V

-16.8

Output High Current(Normal strengh driver) ;V

OUT

= V

- 0.84V

16.8

Output High Current(Half strengh driver) ;V

OUT

= V

+ 0.45V

-9

Output High Current(Half strengh driver) ;V

OUT

= V

- 0.45V

1.VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same.
Peak-to peak noise on VREF may not exceed +/-2% of the dc value.
2. V

is not applied directly to the device. V

is a system supply for signal termination resistors, is expected to be set equal to

REF

, and must track variations in the DC level of V

REF

3. V

is the magnitude of the difference between the input level on CK and the input level on CK.

4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire
temperature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the
maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the
maximum to minimum pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to 1.0.

Note :

DDR SDRAM

DDR SDRAM 256Mb E-die (x4, x8)

Rev. 1.1 September. 2003

Input/Output Capacitance

=2.6, V

DDQ

=2.6V, T

= 25

C, f=1MHz)

Parameter

Symbol

Min

Max

Delta

Unit

Note

Input capacitance
(A0 ~ A12, BA0 ~ BA1, CKE, CS, RAS,CAS, WE)

CIN1

1.5

2.5

0.5

Input capacitance( CK, CK )

CIN2

1.5

2.5

0.25

Data & DQS input/output capacitance

COUT

3.5

4.5

0.5

1,2,3,4

Input capacitance (DM)

CIN3

3.5

4.5

1,2,3,4

Note : 1.These values are guaranteed by design and are tested on a sample basis only.

2. Although DM is an input -only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins.
This is required to match signal propagation times of DQ, DQS, and DM in the system.
3. Unused pins are tied to ground.
4. This parameteer is sampled. VDDQ = +2.6V +0.1V, VDD = +2.6V +0.1V, f=100MHz, tA=25

C, Vout(dc) =

VDDQ/2, Vout(peak to peak) = 0.2V. DM inputs are grouped with I/O pins - reflecting the fact that they are matched in loading
(to facilitate trace matching at the board level).

DDR SDRAM Spec Items & Test Conditions

Conditions

Symbol

Operating current - One bank Active-Precharge;
tRC=tRCmin; tCK=5ns for DDR400; DQ,DM and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles; CS = high between valid commands.

IDD0

Operating current - One bank operation ; One bank open, BL=4, Reads
- Refer to the following page for detailed test condition; CS = high between valid commands.

IDD1

Percharge power-down standby current; All banks idle; power - down mode; CKE = <VIL(max); tCK=5ns for
DDR400; Vin = Vref for DQ,DQS and DM.

IDD2P

Precharge Floating standby current; CS# > =VIH(min);All banks idle; CKE > = VIH(min); tCK=5ns for DDR400;
Address and other control inputs changing once per clock cycle; Vin = Vref for DQ,DQS and DM

IDD2F

Precharge Quiet standby current; CS# > = VIH(min); All banks idle;
CKE > = VIH(min); tCK=5ns for DDR400; Address and other control inputs stable at >= VIH(min) or =<VIL(max);
Vin = Vref for DQ ,DQS and DM

IDD2Q

Active power - down standby current ; one bank active; power-down mode; CKE=< VIL (max); tCK=5ns
DDR400; Vin = Vref for DQ,DQS and DM

IDD3P

Active standby current; CS# >= VIH(min); CKE>=VIH(min);
one bank active; active - precharge; tRC=tRASmax; tCK=5ns for DDR400; DQ, DQS and DM inputs changing twice
per clock cycle; address and other control inputs changing once per clock cycle

IDD3N

Operating current - burst read; Burst length = 2; reads; continguous burst; One bank active; address and control
inputs changing once per clock cycle; CL=3 at 5ns for DDR400; 50% of data changing on every transfer; lout = 0 m
A

IDD4R

Operating current - burst write; Burst length = 2; writes; continuous burst;
One bank active address and control inputs changing once per clock cycle; CL=3 at tCK=5ns for DDR400; DQ, DM
and DQS inputs changing twice per clock cycle, 50% of input data changing at every transfer

IDD4W

Auto refresh current; tRC = tRFC(min) - 14*tCK for DDR400 at tCK=5ns;

IDD5

Self refresh current; CKE =< 0.2V; External clock on; tCK = 5ns for DDR400.

IDD6

DDR SDRAM

DDR SDRAM 256Mb E-die (x4, x8)

Rev. 1.1 September. 2003

DDR SDRAM I

spec table

=2.7V, T = 10

Symbol

64Mx4 (K4H560438E), 32Mx8 (K4H560838E)

Unit

Notes

CC(DDR400@CL=3)

C4(DDR400@CL=3)

IDD0

105

100

IDD1

130

IDD2P

IDD2F

IDD2Q

IDD3P

IDD3N

IDD4R

185

IDD4W

190

IDD5

180

IDD6

Normal

Low power

1.5

Optional

IDD7A

310

290

< Detailed test conditions for DDR SDRAM IDD1 & IDD7A >

IDD1 : Operating current: One bank operation
1. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs change logic state once per Deselect cycle.
Iout = 0mA
2. Timing patterns

- CC/C4(200Mhz,CL=3) : tCK=5ns, CL=3, BL=4, tRCD=3*tCK(CC) 4*tCK(C4), tRC=11*tCK(CC) 12*tCK(C4), tRAS=8*tCK
Setup : A0 N N R0 N N N N P0 N N

Read : A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing

*50% of data changing at every transfer

IDD7A : Operating current: Four bank operation
1. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on Deselet edge are not changing.
Iout = 1mA
2. Timing patterns

- CC/C4(200Mhz,CL=3) : tCK=5ns, CL=3, BL=4, tRCD=3*tCK(CC) 4*tCK(C4), tRC=11*tCK(CC) 12*tCK(C4), tRAS=8*tCK
Setup : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N N

Read : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N N - repeat the same timing with random address changing

*50% of data changing at every transfer

Legend : A = Activate, R=Read, W=Write, P=Precharge, N=NOP

DDR SDRAM

DDR SDRAM 256Mb E-die (x4, x8)

Rev. 1.1 September. 2003

AC Operating Conditions

Parameter/Condition

Symbol

Min

Max-10

Unit

Note

Input High (Logic 1) Voltage, DQ, DQS and DM signals

VIH(AC)

VREF + 0.31

Input Low (Logic 0) Voltage, DQ, DQS and DM signals.

VIL(AC)

VREF - 0.31

Input Differential Voltage, CK and /CK inputs

VID(AC)

0.7

VDDQ+0.6

Input Crossing Point Voltage, CK and /CK inputs

VIX(AC)

0.5*VDDQ-0.2

0.5*VDDQ+0.2

-1

-2

-3

-4

-5

0.5

0.6875

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.3125

6.5

7.0

VDD

Overshoot

Maximum Amplitude = 1.5V

Area = 4.5V-ns

Maximum Amplitude = 1.5V

undershoot

GND

l
t
s
(

)

Tims(ns)

AC overshoot/Undershoot Definition

Notes :
1. VID is the magnitude of the difference between the input level on CK and the input level on /CK.
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.

AC Overshoot/Undershoot specification for Address and Control Pins

Parameter

Specification

DDR400

Maximum peak amplitude allowed for overshoot

1.5V

Maximum peak amplitude allowed for undershoot

1.5V

The area between the overshoot signal and VDD must be less than or equal to

4.5V-ns

The area between the undershoot signal and GND must be less than or equal to

4.5V-ns

DDR SDRAM

DDR SDRAM 256Mb E-die (x4, x8)

Rev. 1.1 September. 2003

-1

-2

-3

-4

-5

0 0.5 1.0 1.42 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.68 6.0 6.5 7.0

VDDQ

Overshoot

Maximum Amplitude = 1.2V

Area = 2.4V-ns

Maximum Amplitude = 1.2V

undershoot

GND

l
t
s
(

)

Tims(ns)

DQ/DM/DQS AC overshoot/Undershoot Definition

Overshoot/Undershoot specification for Data, Strobe, and Mask Pins

Parameter

Specification

DDR400

Maximum peak amplitude allowed for overshoot

1.2V

Maximum peak amplitude allowed for undershoot

1.2V

The area between the overshoot signal and VDD must be less than or equal to

2.5V-ns

The area between the undershoot signal and GND must be less than or equal to

2.5V-ns

DDR SDRAM

DDR SDRAM 256Mb E-die (x4, x8)

Rev. 1.1 September. 2003

AC Timing Parameters and Specifications

Parameter

Symbol

- CC(DDR400@CL=3)

- C4(DDR400@CL=3)

Unit

Note

Min

Max

Min

Max

Row cycle time

tRC

Refresh row cycle time

tRFC

Row active time

tRAS

70K

RAS to CAS delay

tRCD

Row precharge time

tRP

Row active to Row active delay

tRRD

Write recovery time

tWR

Internal write to read command delay

tWTR

tCK

Clock cycle time

CL=3.0

tCK

CL=2.5

Clock high level width

tCH

0.45

0.55

0.45

0.55

tCK

Clock low level width

tCL

0.45

0.55

0.45

0.55

tCK

DQS-out access time from CK/CK

tDQSCK

-0.55

+0.55

-0.55

+0.55

Output data access time from CK/CK

tAC

-0.65

+0.65

-0.65

+0.65

Data strobe edge to ouput data edge

tDQSQ

0.4

Read Preamble

tRPRE

0.9

1.1

0.9

1.1

tCK

Read Postamble

tRPST

0.4

0.6

0.4

0.6

tCK

CK to valid DQS-in

tDQSS

0.72

1.28

0.72

1.28

tCK

Write preamble setup time

tWPRES

Write preamble

tWPRE

0.25

tCK

Write postamble

tWPST

0.4

0.6

0.4

0.6

tCK

DQS falling edge to CK rising-setup time

tDSS

0.2

tCK

DQS falling edge from CK rising-hold time

tDSH

0.2

tCK

DQS-in high level width

tDQSH

0.35

tCK

DQS-in low level width

tDQSL

0.35

tCK

Address and Control Input setup time

tIS

0.6

h,7~10

Address and Control Input hold time

tIH

0.6

h,7~10

Data-out high impedence time from CK/CK

tHZ

tAC max

Data-out low impedence time from CK/CK

tLZ

tAC min

tAC max

tAC min

tAC max

Mode register set cycle time

tMRD

tCK

DQ & DM setup time to DQS, slew rate 0.5V/ns

tDS

0.4

i, j

DQ & DM hold time to DQS, slew rate 0.5V/ns

tDH

0.4

i, j

DQ & DM input pulse width

tDIPW

1.75

Control & Address input pulse width for each input

tIPW

2.2

Refresh interval time

Up to 128Mb

tREFI

15.6

256Mb, 512Mb, 1Gb

7.8

Output DQS valid window

tQH

tHP

-tQHS

tHP

-tQHS

Clock half period

tHP

min

tCH/tCL

min

tCH/tCL

11, 12

DDR SDRAM

DDR SDRAM 256Mb E-die (x4, x8)

Rev. 1.1 September. 2003

Component Notes

1.V

is the magnitude of the difference between the input level on CK and the input level on CK.

2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.

3. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a
specific voltage level but specify when the device output in no longer driving (HZ), or begins driving (LZ).

4. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but sys
tem performance (bus turnaround) will degrade accordingly.

5. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A
valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previ
ously in progress on the bus, DQS will be tran sitioning from High- Z to logic LOW. If a previous write was in progress, DQS could
be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.

6. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.

7. For command/address input slew rate

0.5 V/ns

8. For CK & CK slew rate

0.5 V/ns

9. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by
device design or tester correlation.

10. Slew Rate is measured between VOH(ac) and VOL(ac).

11. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the
period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into
the clock traces.

12. tQH = tHP - tQHS, where:
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The
pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst
case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-
channel to n-channel variation of the output drivers.

13. tDQSQ
Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given
cycle.

14. tDAL = (tWR/tCK) + (tRP/tCK)
For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR400(CC) at CL=3 and
tCK=5ns tDAL = (15 ns / 5 ns) + (15 ns/ 5ns) = {(3) + (3)}CLK
tDAL = 6 clocks

15. In all circumstances, tXSNR can be satisfied using tXSNR=tRFCmin+1*tCK

16. The only time that the clock frequency is allowed to change is during self-refresh mode.

Parameter

Symbol

- CC(DDR400@CL=3)

- C4(DDR400@CL=3)

Unit

Note

Min

Max

Min

Max

Data hold skew factor

tQHS

0.5

Auto Precharge write recovery + precharge time

tDAL

Exit self refresh to non-READ command

tXSNR

Exit self refresh to READ command

tXSRD

200

tCK

DDR SDRAM

DDR SDRAM 256Mb E-die (x4, x8)

Rev. 1.1 September. 2003

Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate

Table 5 : Output Slew Rate Characteristice (X8 Devices only)

Table 6 : Output Slew Rate Characteristice (X16 Devices only)

Table 7 : Output Slew Rate Matching Ratio Characteristics

Delta Slew Rate

tDS

tDH

Units

Notes

+/- 0.0 V/ns

+/- 0.25 V/ns

+50

+/- 0.5 V/ns

+100

Slew Rate Characteristic

Typical Range

(V/ns)

Minimum

(V/ns)

Maximum

(V/ns)

Notes

Pullup Slew Rate

1.2 ~ 2.5

1.0

4.5

a,c,d,f,g

Pulldown slew

1.2 ~ 2.5

1.0

4.5

b,c,d,f,g

Slew Rate Characteristic

Typical Range

(V/ns)

Minimum

(V/ns)

Maximum

(V/ns)

Notes

Pullup Slew Rate

1.2 ~ 2.5

0.7

5.0

a,c,d,f,g

Pulldown slew

1.2 ~ 2.5

0.7

5.0

b,c,d,f,g

AC CHARACTERISTICS

DDR400

PARAMETER

MIN

MAX

Notes

Output Slew Rate Matching Ratio (Pullup to Pulldown)

e,k

System Characteristics for DDR SDRAM

The following specification parameters are required in systems using DDR400 devices to ensure proper system perfor-
mance. these characteristics are for system simulation purposes and are guaranteed by design.

Table 1 : Input Slew Rate for DQ, DQS, and DM

Table 2 : Input Setup & Hold Time Derating for Slew Rate

Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate

AC CHARACTERISTICS

DDR400

PARAMETER

SYMBOL

MIN

MAX

Units

Notes

DQ/DM/DQS input slew rate measured between
VIH(DC), VIL(DC) and VIL(DC), VIH(DC)

DCSLEW

0.5

4.0

V/ns

a, k

Input Slew Rate

tIS

tIH

Units

Notes

0.5 V/ns

0.4 V/ns

+50

0.3 V/ns

+100

Input Slew Rate

tDS

tDH

Units

Notes

0.5 V/ns

0.4 V/ns

+75

0.3 V/ns

+150

DDR SDRAM

DDR SDRAM 256Mb E-die (x4, x8)

Rev. 1.1 September. 2003

System Notes :
a. Pullup slew rate is characteristized under the test conditions as shown in Figure 1.

Output

Test point

VSSQ

Figure 1 : Pullup slew rate test load

b. Pulldown slew rate is measured under the test conditions shown in Figure 2.

Output

Test point

VDDQ

Figure 2 : Pulldown slew rate test load

c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV)
Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV)
Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output
switching.
Example : For typical slew rate, DQ0 is switching

For minmum slew rate, all DQ bits are switching from either high to low, or low to high.

For Maximum slew rate, only one DQ is switching from either high to low, or low to high.

The remaining DQ bits remain the same as for previous state.

d. Evaluation conditions
Typical : 25

C (T Ambient), VDDQ = 2.6V, typical process

Minimum : 70

C (T Ambient), VDDQ = 2.5V, slow - slow process

Maximum : 0

C (T Ambient), VDDQ = 2.7V, fast - fast process

e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and
voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation.

f. Verified under typical conditions for qualification purposes.

g. TSOPII package divices only.

h. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns
as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or
VIH(DC) to VIL(DC), similarly for rising transitions.

i. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4.
Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the
slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.
The delta rise/fall rate is calculated as:
{1/(Slew Rate1)} - {1/(Slew Rate2)}

For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this
would result in the need for an increase in tDS and tDH of 100 ps.

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