DDR SDRAM
DDR SDRAM 256Mb E-die (x4, x8)
Rev. 1.3 April, 2005
256Mb E-die DDR SDRAM Specification
54pin sTSOP(II)
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DDR SDRAM
DDR SDRAM 256Mb E-die (x4, x8)
Rev. 1.3 April, 2005
256Mb E-die Revision History
Revision0.0 (February, 2003)
- First version for internal review
Revision1.0 (July, 2003)
- Finalized datasheet
Revision1.1 (August, 2003)
- Corrected typo in package phyisical dimension and deleted speed AA.
Revision1.2 (October, 2004)
- Corrected typo.
Revision1.3 (April, 2005)
- Added notice and corrected typo.
DDR SDRAM
DDR SDRAM 256Mb E-die (x4, x8)
Rev. 1.3 April, 2005
Double-data-rate architecture; two data transfers per clock cycle
Bidirectional data strobe(DQS)
Four banks operation
Differential clock inputs(CK and CK)
DLL aligns DQ and DQS transition with CK transition
MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
Data I/O transactions on both edges of data strobe
Edge aligned data output, center aligned data input
DM for write masking only (x4, x8)
Auto & Self refresh
7.8us refresh interval(8K/64ms refresh)
Maximum burst refresh cycle : 8
54pin sTSOP(II)-300 package
*CL : CAS Latency
Operating Frequencies
B3(DDR333@CL=2.5)
AA(DDR266@CL=2.0)
A2(DDR266@CL=2.0)
B0(DDR266@CL=2.5)
Speed @CL2
133MHz
133MHz
133MHz
100MHz
Speed @CL2.5
166MHz
133MHz
133MHz
133MHz
Ordering Information
Part No.
Org.
Max Freq.
Interface
Package
K4H560438E-NC/LB3
64M x 4
B3(DDR333@CL=2.5)
SSTL2
54pin sTSOP(II)-300
K4H560438E-NC/LA2
A2(DDR266@CL=2)
K4H560438E-NC/LB0
B0(DDR266@CL=2.5)
K4H560838E-NC/LB3
32M x 8
B3(DDR333@CL=2.5)
SSTL2
54pin sTSOP(II)-300
K4H560838E-NC/LA2
A2(DDR266@CL=2)
K4H560838E-NC/LB0
B0(DDR266@CL=2.5)
Key Features
DDR SDRAM
DDR SDRAM 256Mb E-die (x4, x8)
Rev. 1.3 April, 2005
Pin Description
DM is internally loaded to match DQ and DQS identically.
Row & Column address configuration
Organization
Row Address
Column Address
64Mx4
A0~A12
A0-A9, A11
32Mx8
A0~A12
A0-A9
54pin sTSOP(II)-300
VDD
1
54 PinsTSOP(II)
300mil x 551mil
NC
2
VDDQ
3
DQ0
4
VSSQ
5
NC
6
VDDQ
7
DQ1
8
VSSQ
9
NC
10
VDDQ
11
NC
12
A3
20
A1
19
A0
18
AP/A10
17
BA1
16
BA0
15
WE
14
NC
13
CS
27
26
25
24
23
22
VDD
21
VSS
42
NC
41
VSSQ
40
DQ3
39
VDDQ
38
NC
37
VSSQ
36
DQ2
35
VDDQ
34
NC
33
VSSQ
32
DQS
31
A4
A7
A9
A11
CKE
28
DM
29
VREF
30
43
44
45
46
47
48
VSS
(0.5 mm Pin Pitch)
49
50
51
52
53
54
VDD
CAS
RAS
NC
A2
VSS
CK
CK
A12
A8
A6
A5
64Mb x 4
32Mb x 8
VSS
DQ7
VSSQ
DQ6
VDDQ
DQ5
VSSQ
DQ4
VDDQ
NC
VSSQ
DQS
A4
A7
A9
A11
CKE
DM
VREF
VSS
VSS
CK
CK
A12
A8
A6
A5
VDD
DQ0
VDDQ
DQ1
VSSQ
DQ2
VDDQ
DQ3
VSSQ
NC
VDDQ
NC
A3
A1
A0
AP/A10
BA1
BA0
WE
NC
CS
VDD
VDD
CAS
RAS
NC
A2
Bank Address
BA0-BA1
Row Address
A0-A12
Auto Precharge
A10
(7.62mm x 14.00mm)
DDR SDRAM
DDR SDRAM 256Mb E-die (x4, x8)
Rev. 1.3 April, 2005
Package Physical Dimension
Units : Millimeters
0.20
0.50TYP
(0.50)
14.40MAX
0.125
(0.8
0)
7.
6
0
~8
#1
#27
#54
#28
(
1
.00)
0.50
0.05
1.2
0
MAX
(0
.50)
(0.50
)
(8.22
)
9.2
2
0.20
(14
)
+0.075
-0.035
(0
.80)
0.10 MAX
0
.
05 MIN
(14
)
(14
)
(2-R
0.15
)
0.
210
0.0
5
0.
665
0.0
5
(2
-R
0.
30)
(1
4
)
(R
0.
25
)
(R
0.
25)
0.40
~0.6
0
0.25TYP
NOTE
1. ( ) IS REFERENCE
2. [ ] IS ASS
'
Y OUT QUALITY
(1.00)
(
2.00 Dp0~0.05 BTM)
(2-R 0.15)
(2-R 0.30)
+0.075
-0.035
0.07 MAX
[
]
(1.10
)
1.
0
0
0.0
5
(14.20)
14.00
0.10
54pin sTSOP(II)-300
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