DDR SDRAM
DDR SDRAM 256Mb F-die (x8, x16)
Rev. 1.1 August. 2003
256Mb F-die DDR SDRAM Specification
Revision 1.1
DDR SDRAM
DDR SDRAM 256Mb F-die (x8, x16)
Rev. 1.1 August. 2003
256Mb F-die Revision History
Revision 1.0 (June, 2003)
- First version for internal review
Revision 1.1 (Agust, 2003)
- Added x8 org (K4H560838F) and speed AA
DDR SDRAM
DDR SDRAM 256Mb F-die (x8, x16)
Rev. 1.1 August. 2003
Double-data-rate architecture; two data transfers per clock cycle
Bidirectional data strobe
L(U)DQS
Four banks operation
Differential clock inputs(CK and CK)
DLL aligns DQ and DQS transition with CK transition
MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
Data I/O transactions on both edges of data strobe
Edge aligned data output, center aligned data input
LDM,UDM for write masking only (x16)
Auto & Self refresh
7.8us refresh interval(8K/64ms refresh)
Maximum burst refresh cycle : 8
66pin TSOP II package
Ordering Information
Part No.
Org.
Max Freq.
Interface
Package
K4H561638F-TC/LB3
16M x 16
B3(DDR333@CL=2.5)
SSTL2
66pin TSOP II
K4H561638F-TC/LAA
AA(DDR266@CL=2)
K4H561638F-TC/LA2
A2(DDR266@CL=2)
K4H561638F-TC/LB0
B0(DDR266@CL=2.5)
K4H560838F-TC/LB3
32M x 8
B3(DDR333@CL=2.5)
SSTL2
66pin TSOP II
K4H560838F-TC/LAA
AA(DDR266@CL=2)
K4H560838F-TC/LA2
A2(DDR266@CL=2)
K4H560838F-TC/LB0
B0(DDR266@CL=2.5)
Key Features
*CL : CAS Latency
Operating Frequencies
B3(DDR333@CL=2.5)
AA(DDR266@CL=2.0)
A2(DDR266@CL=2.0)
B0(DDR266@CL=2.5)
Speed @CL2
133MHz
133MHz
133MHz
100MHz
Speed @CL2.5
166MHz
133MHz
133MHz
133MHz
DDR SDRAM
DDR SDRAM 256Mb F-die (x8, x16)
Rev. 1.1 August. 2003
Pin Description
DM is internally loaded to match DQ and DQS identically.
256Mb TSOP-II Package Pinout
Row & Column address configuration
1
66Pin TSOPII
(400mil x 875mil)
2
3
4
5
6
7
8
9
10
11
12
20
19
18
17
16
15
14
13
27
26
25
24
23
22
21
54
53
52
51
50
49
48
47
46
45
44
43
35
36
37
38
39
40
41
42
55
56
57
58
59
60
34
(0.65mm Pin Pitch)
33
32
31
30
29
28
61
62
63
64
65
66
Bank Address
BA0~BA1
Auto Precharge
A10
Organization
Row Address
Column Address
32Mx8
A0~A12
A0-A9
16Mx16
A0~A12
A0-A8
V
DD
DQ
0
V
DDQ
DQ
1
DQ
2
V
SSQ
DQ
3
DQ
4
V
DDQ
DQ
5
DQ
6
V
SSQ
BA
0
CS
RAS
CAS
WE
LDM
V
DDQ
DQ
7
V
DD
A
3
A
2
A
1
A
0
AP/A
10
BA
1
NC
LDQS
NC
NC
NC
V
DD
V
SS
DQ
15
V
SSQ
DQ
14
DQ
13
V
DDQ
DQ
12
DQ
11
V
SSQ
DQ
10
DQ
9
V
DDQ
A
11
CKE
CK
UDM
V
REF
V
SSQ
DQ
8
V
SS
A
4
A
5
A
6
A
7
A
8
A
9
NC
UDQS
NC
V
SS
CK
NC
A
12
16Mb x 16
32Mb x 8
V
DD
DQ
0
V
DDQ
NC
DQ
1
V
SSQ
NC
DQ
2
V
DDQ
NC
DQ
3
V
SSQ
BA
0
CS
RAS
CAS
WE
NC
V
DDQ
NC
V
DD
A
3
A
2
A
1
A
0
AP/A
10
BA
1
NC
NC
NC
NC
NC
V
DD
V
SS
DQ
7
V
SSQ
NC
DQ
6
V
DDQ
NC
DQ
5
V
SSQ
NC
DQ
4
V
DDQ
A
11
CKE
CK
DM
V
REF
V
SSQ
NC
V
SS
A
4
A
5
A
6
A
7
A
8
A
9
NC
DQS
NC
V
SS
CK
NC
A
12
DDR SDRAM
DDR SDRAM 256Mb F-die (x8, x16)
Rev. 1.1 August. 2003
Units : Millimeters
0.30
0.08
0.65TYP
(0.71)
22.22
0.10
0.125
(0.80
)
10
.16
0.1
0
0
~8
#1
#33
#66
#34
(1.50)
(1.50
)
0.65
0.08
1.0
0
0.
1
0
1.2
0
MAX
(0
.50)
(0.
50)
(10.1
6
)
11
.
7
6
0.2
0
(10
)
(10
)
+0.075
-0.035
(0.8
0)
0.10 MAX
0.075 MAX
[
]
0
.
05 MIN
(10
)
(10
)
(R0.1
5)
0.
210
0.0
5
0.
665
0.0
5
(R
0.
15)
(4
)
(R
0.
25
)
(R
0.
25)
0.45
~0.7
5
0.25TYP
NOTE
1. ( ) IS REFERENCE
2. [ ] IS ASS
'
Y OUT QUALITY
66pin TSOPII / Package dimension
Package Physical Dimension
PDF 
ZIP