K4M563233D-M(E)E/N/I/P
Rev. 1.1 Dec. 2002
CMOS SDRAM
GENERAL DESCRIPTION
FEATURES
2M x 32Bit x 4 Banks SDRAM in 90FBGA
FUNCTIONAL BLOCK DIAGRAM
ORDERING INFORMATION
- M(E)E/N ; Normal/Low Power, Temp : -25
C ~ 85
C.
- M(E)I/P ; Noraml/Low Power, Temp : -40
C ~ 85
C.
Note : 1. In case of 40MHz Frequency, CL1 can be supported.
Part No.
Max Freq.
Interface Package
K4M563233D-M(E)E/N/I/P80
125MHz(CL=3)
105MHz(CL=2)
LVCMOS
90 FBGA
Pb
(Pb Free)
K4M563233D-M(E)E/N/I/P1H 105MHz(CL=2)
K4M563233D-M(E)E/N/I/P1L 105MHz(CL=3)
*1
3.0V & 3.3V power supply
LVCMOS compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
-. CAS latency (1, 2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system
clock
Burst read single-bit write operation
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle).
Extended Temperature Operation (-25
C ~ 85
C).
Inderstrial Temperature Operation (-40
C ~ 85
C).
90Balls DDP FBGA(-MXXX -Pb, -EXXX -Pb Free).
Bank Select
Data Input Register
2M x 32
2M x 32
S
e
n
s
e
A
M
P
O
u
t
p
u
t
B
u
f
f
e
r
I
/
O
C
o
n
t
r
o
l
Column Decoder
Latency & Burst Length
Programming Register
A
d
d
r
e
s
s
R
e
g
i
s
t
e
r
R
o
w
B
u
f
f
e
r
R
e
f
r
e
s
h
C
o
u
n
t
e
r
R
o
w
D
e
c
o
d
e
r
C
o
l
.
B
u
f
f
e
r
L
R
A
S
L
C
B
R
LCKE
LRAS
LCBR
LWE
LDQM
CLK
CKE
CS
RAS
CAS
WE
DQM
LWE
LDQM
DQi
CLK
ADD
LCAS
LWCBR
2M x 32
2M x 32
Timing Register
* Samsung Electronics reserves the right to change products or specification without notice.
The K4M283233D is 268,435,456 bits synchronous high data
rate Dynamic RAM organized as 4 x 2,097,152 words by 32
bits, fabricated with SAMSUNG
s high performance CMOS
technology. Synchronous design allows precise cycle control
with the use of system clock and I/O transactions are possible
on every clock cycle. Range of operating frequencies, program-
mable burst lengths and programmable latencies allow the
same device to be useful for a variety of high bandwidth and
high performance memory system applications.
K4M563233D-M(E)E/N/I/P
Rev. 1.1 Dec. 2002
CMOS SDRAM
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= -25
C to 85
C for Extended, -40
C to 85
C for Industrial)
Notes
:
1. V
IH
(max) = 5.3V AC. The overshoot voltage duration is
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
3ns.
3. Any input 0V
V
IN
V
DDQ
.
Input leakage currents include HI-Z output leakage for all bi-directional buffers with tri-state outputs.
4. Dout is disabled, 0V
V
OUT
V
DDQ.
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply voltage
V
D D
2.7
3.0
3.6
V
V
DDQ
2.7
3.0
3.6
V
Input logic high voltage
V
I H
2.2
3.0
V
DDQ
+0.3
V
1
Input logic low voltage
V
IL
-0.3
0
0.5
V
2
Output logic high voltage
V
O H
2.4
-
-
V
I
O H
= -2mA
Output logic low voltage
V
OL
-
-
0.4
V
I
OL
= 2mA
Input leakage current
I
LI
-10
-
10
uA
3
CAPACITANCE
(V
DD
= 3.0V & 3.3V, T
A
= 23
C, f = 1MHz, V
REF
=0.9V
50
mV)
Pin
Symbol
Min
Max
Unit
Note
Clock
C
CLK
3.0
9.0
pF
RAS, CAS, WE, CS, CKE
C
IN
3.0
9.0
pF
DQM
C
IN
1.5
4.5
pF
Address
C
ADD
3.0
9.0
pF
D Q
0
~ DQ
31
C
OUT
3.0
6.5
pF
ABSOLUTE MAXIMUM RATINGS
Notes
:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
V
I N
, V
O U T
-1.0 ~ 4.6
V
Voltage on V
D D
supply relative to Vss
V
DD
, V
DDQ
-1.0 ~ 4.6
V
Storage temperature
T
STG
-55 ~ +150
C
Power dissipation
P
D
1
W
Short circuit current
I
OS
50
mA
K4M563233D-M(E)E/N/I/P
Rev. 1.1 Dec. 2002
CMOS SDRAM
DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= -25
C to 85
C for Extended, -40
C to 85
C for Industrial)
Parameter
Symbol
Test Condition
Version
Unit
Note
-80
-1H
-1L
Operating Current
(One Bank Active)
I
CC1
Burst length = 1
t
RC
t
R C
(min)
I
O
= 0 mA
150
150
140
mA
1
Precharge Standby Current
in power-down mode
I
CC2
P
CKE
V
IL
(max), t
CC
= 10ns
1.2
mA
I
C C 2
PS CKE & CLK
V
IL
(max), t
CC
=
1.2
Precharge Standby Current
in non power-down mode
I
CC2
N
CKE
V
IH
(min), CS
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
20
mA
I
CC2
NS
CKE
V
IH
(min), CLK
V
IL
(max), t
CC
=
Input signals are stable
10
Active Standby Current
in power-down mode
I
CC3
P
CKE
V
IL
(max), t
CC
= 10ns
8
mA
I
C C 3
PS CKE & CLK
V
IL
(max), t
CC
=
8
Active Standby Current
in non power-down mode
(One Bank Active)
I
CC3
N
CKE
V
IH
(min), CS
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
45
mA
I
CC3
NS
CKE
V
IH
(min), CLK
V
IL
(max), t
CC
=
Input signals are stable
40
mA
Operating Current
(Burst Mode)
I
CC4
I
O
= 0 mA
Page burst
4Banks Activated
t
C C D
= 2CLKs
190
160
160
mA
1
Refresh Current
I
CC5
t
RC
t
R C
(min)
320
300
290
mA
2
Self Refresh Current
I
CC6
CKE
0.2V
-M(E)E/I
3
mA
3
-M(E)N/P
1000
uA
4
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4M563233D-M(E)E/I**
4. K4M563233D-M(E)N/P**
5. Unless otherwise noted, input swing IeveI is CMOS(V
IH
/V
IL
=V
DDQ
/V
SSQ)
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