Page 1

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

Overview

The Rambus Direct RDRAMTM is a general purpose high-
performance memory device suitable for use in a broad
range of applications including computer memory, graphics,
video, and any other application where high bandwidth and
low latency are required.

The 288Mbit Direct Rambus DRAMs (RDRAM

) are

extremely high-speed CMOS DRAMs organized as 16M
words by 18 bits. The use of Rambus Signaling Level (RSL)
technology permits 600MHz to 800MHz transfer rates while
using conventional system and board design technologies.
Direct RDRAM devices are capable of sustained data trans-
fers at 1.25 ns per two bytes (10ns per sixteen bytes).

The architecture of the Direct RDRAMs allows the highest
sustained bandwidth for multiple, simultaneous randomly
addressed memory transactions. The separate control and
data buses with independent row and column control yield
over 95% bus efficiency. The Direct RDRAM's 32 banks
support up to four simultaneous transactions.

System oriented features for mobile, graphics and large
memory systems include power management, byte masking,
and x18 organization. The two data bits in the x18 organiza-
tion are general and can be used for additional storage/band-
width or for error correction.

Features

Highest sustained bandwidth per DRAM device

- 1.6GB/s sustained data transfer rate
- Separate control/data buses for maximum efficiency
- Separate row and column control buses for easy
scheduling and highest performance
- 32 banks: four transactions can take place simul-

taneously at full bandwidth data rates

Low latency features

- Write buffer to reduce read latency
- 3 precharge mechanisms for controller flexibility
- Interleaved transactions

Advanced power management:

- Multiple low power states allows flexibility in power
consumption versus time to active state
- Power-down self-refresh

Organization: 2Kbyte pages and 32 banks, x 18

- x18 organization allows ECC configurations or

increased storage and bandwidth

Used Rambus Signaling Level (RSL) for up to 800MHz oper-

ation

The 288Mbit Direct RDRAMs are offered in a CSP hori-
zontal package suitable for desktop as well as low-profile
add-in card and mobile applications.

Key Timing Parameters/Part Numbers

a.The

32s

designation indicates that this RDRAM core is composed of 32

banks which use a

split

bank architecture.

b.The

designator indicates the normal package

c.The

designator indicates that this RDRAM core uses Normal Power

Self Refresh.

Figure 1: Direct RDRAM CSP Package

Organization

Speed

Part Number

Bin

I/O

Freq.

MHz

RAC

(Row

Access

Time) ns

512Kx18x32s

-CG6

600

53.3

K4R881869M-N

-CK7

711

K4R881869M-NCK7

-CK8

800

K4R881869M-NCK8

K4R88

69A-

xxx

SAMSUNG 001

Page 2

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

The pin #1(ROW 1, COL A) is located at the
A1 position on the top side and the A1 position
is marked by the marker

Pinouts and Definitions

Center-Bonded Devices - Preliminary

These tables shows the pin assignments of the center-bonded
RDRAM package. The mechanical dimensions of this

package are shown in a later section. Refer to Section

Center-Bonded uBGA Package

on page 58. Note - pin #1

is at the A1 position. .

Table 1: Center-Bonded Device (top view)

GND

CMD

GND

GNDa

GND

CMOS

GND

DQA8

DQA7

DQA5

DQA3

DQA1

CTMN

CTM

RQ7

RQ5

RQ3

RQ1

DQB1

DQB3

DQB5

DQB7

DQB8

GND

DQA6

DQA4

DQA2

DQA0

CFM

CFMN

RQ6

RQ4

RQ2

RQ0

DQB0

DQB2

DQB4

DQB6

GND

SCK

CMOS

GND

DDa

REF

GND

SIO0

SIO1

GND

COL

ROW

Chip

Top View

K4R88

69A-

xxx

SAMSUNG 001

Page 3

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

Table 2: Pin Description

Signal

I/O

Type

# Pins

Description

SIO1,SIO0

I/O

CMOS

Serial input/output. Pins for reading from and writing to the control
registers using a serial access protocol. Also used for power man-
agement.

CMD

CMOS

Command input. Pins used in conjunction with SIO0 and SIO1 for
reading from and writing to the control registers. Also used for
power management.

SCK

CMOS

Serial clock input. Clock source used for reading from and writing to
the control registers

Supply voltage for the RDRAM core and interface logic.

DDa

Supply voltage for the RDRAM analog circuitry.

CMOS

Supply voltage for CMOS input/output pins.

GND

Ground reference for RDRAM core and interface.

GNDa

Ground reference for RDRAM analog circuitry.

DQA8..DQA0

I/O

RSL

Data byte A. Nine pins which carry a byte of read or write data
between the Channel and the RDRAM.

CFM

RSL

Clock from master. Interface clock used for receiving RSL signals
from the Channel. Positive polarity.

CFMN

RSL

Clock from master. Interface clock used for receiving RSL signals
from the Channel. Negative polarity

REF

Logic threshold reference voltage for RSL signals

CTMN

RSL

Clock to master. Interface clock used for transmitting RSL signals
to the Channel. Negative polarity.

CTM

RSL

Clock to master. Interface clock used for transmitting RSL signals
to the Channel. Positive polarity.

RQ7..RQ5 or
ROW2..ROW0

RSL

Row access control. Three pins containing control and address
information for row accesses.

RQ4..RQ0 or
COL4..COL0

RSL

Column access control. Five pins containing control and address
information for column accesses.

DQB8..
DQB0

I/O

RSL

Data byte B. Nine pins which carry a byte of read or write data
between the Channel and the RDRAM.

Total pin count per package

a. All CMOS signals are high-true; a high voltage is a logic one and a low voltage is logic zero.
b. All RSL signals are low-true; a low voltage is a logic one and a high voltage is logic zero.

Page 4

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

Figure 2: 288 Mbit Direct RDRAM Block Diagram

Bank 31

DQA8..DQA0

:
8

:
1

r
i
t
e

f
f
e

:
8

W
r
i
t
e

f
f
e

:
1

Bank 30

Bank 29

Bank 18

Bank 17

Bank 16

Bank 15

Bank 14

Bank 13

Bank 1

Bank 0

/
2

DQB8..DQB0

1:8 Demux

Packet Decode

ROW2..ROW0

COL4..COL0

CTM CTMN

CFM CFMN

SCK,CMD

RCLK

TCLK

Control Registers

COP

XOP

ROP

Write

Buffer

Match

Mux

Match

DEVID

512x128x144

Internal DQB Data Path

Column Decode & Mask

REFR

Row Decode

Mux

ACT

RD, WR

Power Modes

DRAM Core

Mux

XOP Decode

PREX

PREC

PRER

COLX

COLC

COLM

SIO0,SIO1

Sense Amp

Internal DQA Data Path

Packet Decode

ROWA

ROWR

RCLK

RQ7..RQ5 or

RQ4..RQ0 or

/
1

/
3

64x72

/
2

/
1

/
3

64x72

Bank 2

·
·
·

Page 5

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

General Description

Figure 2 is a block diagram of the 288Mbit Direct RDRAM.
It consists of two major blocks: a

core

block built from

banks and sense amps similar to those found in other types
of DRAM, and a Direct Rambus interface block which
permits an external controller to access this core at up to
1.6GB/s.

Control Registers:

The CMD, SCK, SIO0, and SIO1

pins appear in the upper center of Figure 2. They are used to
write and read a block of control registers. These registers
supply the RDRAM configuration information to a
controller and they select the operating modes of the device.
The nine bit REFR value is used for tracking the last
refreshed row. Most importantly, the five bit DEVID speci-
fies the device address of the RDRAM on the Channel.

Clocking:

The CTM and CTMN pins (Clock-To-Master)

generate TCLK (Transmit Clock), the internal clock used to
transmit read data. The CFM and CFMN pins (Clock-From-
Master) generate RCLK (Receive Clock), the internal clock
signal used to receive write data and to receive the ROW and
COL pins.

DQA,DQB Pins:

These 18 pins carry read (Q) and write

(D) data across the Channel. They are multiplexed/de-multi-
plexed from/to two 72-bit data paths (running at one-eighth
the data frequency) inside the RDRAM.

Banks:

The 32Mbyte core of the RDRAM is divided into

32 one-Mbyte banks, each organized as 512 rows, with each
row containing 128 dualocts (2 Kbytes), and each dualoct
containing 16 bytes. A dualoct is the smallest unit of data
that can be addressed.

Sense Amps:

The RDRAM contains 34 sense amps. Each

sense amp consists of 1024 bytes of fast storage (512 for
DQA and 512 for DQB) and can hold one-half of one row of
one bank of the RDRAM. The sense amp may hold any of
the 512 half-rows of an associated bank. However, each
sense amp is shared between two adjacent banks of the
RDRAM (except for numbers 0, 15, 30, and 31). This intro-
duces the restriction that adjacent banks may not be simulta-
neously accessed.

RQ Pins:

These pins carry control and address informa-

tion. They are broken into two groups. RQ7..RQ5 are also
called ROW2..ROW0, and are used primarily for controlling
row accesses. RQ4..RQ0 are also called COL4..COL0, and
are used primarily for controlling column accesses.

ROW Pins:

The principle use of these three pins is to

manage the transfer of data between the banks and the sense
amps of the RDRAM. These pins are de-multiplexed into a

24-bit ROWA (row-activate) or ROWR (row-operation)
packet.

COL Pins:

The principle use of these five pins is to

manage the transfer of data between the DQA/DQB pins and
the sense amps of the RDRAM. These pins are de-multi-
plexed into a 23-bit COLC (column-operation) packet and
either a 17-bit COLM (mask) packet or a 17-bit COLX
(extended-operation) packet.

ACT Command:

An ACT (activate) command from an

ROWA packet causes one of the 512 rows of the selected
bank to be loaded to its associated sense amps (two 512 byte
sense amps for DQA and two for DQB).

PRER Command:

A PRER (precharge) command from

an ROWR packet causes the selected bank to release its two
associated sense amps, permitting a different row in that
bank to be activated, or permitting adjacent banks to be acti-
vated.

RD Command:

The RD (read) command causes one of

the 128 dualocts of one of the sense amps to be transmitted
on the DQA/DQB pins of the Channel.

WR Command:

The WR (write) command causes a

dualoct received from the DQA/DQB data pins of the
Channel to be loaded into the write buffer. There is also
space in the write buffer for the BC bank address and C
column address information. The data in the write buffer is
automatically retired (written with optional bytemask) to one
of the 128 dualocts of one of the sense amps during a subse-
quent COP command. A retire can take place during a RD,
WR, or NOCOP to another device, or during a WR or
NOCOP to the same device. The write buffer will not retire
during a RD to the same device. The write buffer reduces the
delay needed for the internal DQA/DQB data path turn-
around.

PREC Precharge:

The PREC, RDA and WRA

commands are similar to NOCOP, RD and WR, except that
a precharge operation is performed at the end of the column
operation. These commands provide a second mechanism
for performing precharge.

PREX Precharge:

After a RD command, or after a WR

command with no byte masking (M=0), a COLX packet may
be used to specify an extended operation (XOP). The most
important XOP command is PREX. This command provides
a third mechanism for performing precharge.

Page 6

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

Packet Format

Figure 3 shows the formats of the ROWA and ROWR
packets on the ROW pins. Table 4 describes the fields which
comprise these packets. DR4T and DR4F bits are encoded to
contain both the DR4 device address bit and a framing bit
which allows the ROWA or ROWR packet to be recognized
by the RDRAM.

The AV (ROWA/ROWR packet selection) bit distinguishes
between the two packet types. Both the ROWA and ROWR
packet provide a five bit device address and a five bit bank
address. An ROWA packet uses the remaining bits to
specify a nine bit row address, and the ROWR packet uses
the remaining bits for an eleven bit opcode field. Note the
use of the

RsvX

notation to reserve bits for future address

field extension.

Figure 3 also shows the formats of the COLC, COLM, and
COLX packets on the COL pins. Table 5 describes the fields
which comprise these packets.

The COLC packet uses the S (Start) bit for framing. A
COLM or COLX packet is aligned with this COLC packet,
and is also framed by the S bit.

The 23 bit COLC packet has a five bit device address, a five
bit bank address, a seven bit column address, and a four bit
opcode. The COLC packet specifies a read or write
command, as well as some power management commands.

The remaining 17 bits are interpreted as a COLM (M=1) or
COLX (M=0) packet. A COLM packet is used for a COLC
write command which needs bytemask control. The COLM
packet is associated with the COLC packet from a time t

RTR

earlier. An COLX packet may be used to specify an indepen-
dent precharge command. It contains a five bit device
address, a five bit bank address, and a five bit opcode. The
COLX packet may also be used to specify some house-
keeping and power management commands. The COLX
packet is framed within a COLC packet but is not otherwise
associated with any other packet.

Table 4: Field Description for ROWA Packet and ROWR Packet

Field

Description

DR4T,DR4F

Bits for framing (recognizing) a ROWA or ROWR packet. Also encodes highest device address bit.

DR3..DR0

Device address for ROWA or ROWR packet.

BR4..BR0

Bank address for ROWA or ROWR packet. RsvB denotes bits ignored by the RDRAM.

Selects between ROWA packet (AV=1) and ROWR packet (AV=0).

R8..R0

Row address for ROWA packet. RsvR denotes bits ignored by the RDRAM.

ROP10..ROP0

Opcode field for ROWR packet. Specifies precharge, refresh, and power management functions.

Table 5: Field Description for COLC Packet, COLM Packet, and COLX Packet

Field

Description

Bit for framing (recognizing) a COLC packet, and indirectly for framing COLM and COLX packets.

DC4..DC0

Device address for COLC packet.

BC4..BC0

Bank address for COLC packet. RsvB denotes bits reserved for future extension (controller drives 0's).

C6..C0

Column address for COLC packet.

COP3..COP0

Opcode field for COLC packet. Specifies read, write, precharge, and power management functions.

Selects between COLM packet (M=1) and COLX packet (M=0).

MA7..MA0

Bytemask write control bits. 1=write, 0=no-write. MA0 controls the earliest byte on DQA8..0.

MB7..MB0

Bytemask write control bits. 1=write, 0=no-write. MB0 controls the earliest byte on DQB8..0.

DX4..DX0

Device address for COLX packet.

BX4..BX0

Bank address for COLX packet. RsvB denotes bits reserved for future extension (controller drives 0's).

XOP4..XOP0

Opcode field for COLX packet. Specifies precharge, I

control, and power management functions.

Page 7

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

Figure 3: Packet Formats

CTM/CFM

COL4

COL3

COL2

COL1

COL0

S=1

MA7 MA5 MA3 MA1

M=1 MA6 MA4 MA2 MA0

MB7 MB4 MB1

MB6 MB3 MB0

MB5 MB2

CTM/CFM

ROW2

DR4T DR2 BR0

BR3 RsvR

ROW1

DR4F DR1 BR1

BR4 RsvR

ROW0

DR3

DR0 BR2 RsvB AV=1

ACT a0

PREX d0

MSK (b1)

PRER c0

WR b1

CTM/CFM

COL4

DC4

S=1

COL3

DC3

COL2

DC2 COP1

RsvB BC2

DC1 COP0

BC4

BC1

DC0 COP2

COP3 BC3

BC0

COL1

COL0

CTM/CFM

ROW2

ROW1

ROW0

CTM/CFM

COL4

COL3

COL2

COL1

COL0

ROP2

DR4T DR2 BR0

BR3

ROP10

ROP8 ROP5

DR4F DR1 BR1 4RsvB ROP9 ROP7 ROP4 ROP1

DR3

DR0 BR2 RsvB AV=0 ROP6 ROP3 ROP0

S=1

DX4 XOP4 RsvB BX1

M=0 DX3 XOP3 BX4

BX0

DX2 XOP2 BX3

DX1 XOP1 BX2

DX0 XOP0

ROWA Packet

COLM Packet

COLC Packet

COLX Packet

ROWR Packet

CTM/CFM

DQA8..0
DQB8..0

COL4

..COL0

ROW2

..ROW0

PACKET

The COLM is associated with a

previous COLC, and is aligned
with the present COLC, indicated
by the Start bit (S=1) position.

The COLX is aligned

with the present COLC,
indicated by the Start
bit (S=1) position.

Page 8

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

Field Encoding Summary

Table 6 shows how the six device address bits are decoded
for the ROWA and ROWR packets. The DR4T and DR4F
encoding merges a fifth device bit with a framing bit. When
neither bit is asserted, the device is not selected. Note that a

broadcast operation is indicated when both bits are set.
Broadcast operation would typically be used for refresh and
power management commands. If the device is selected, the
DM (DeviceMatch) signal is asserted and an ACT or ROP
command is performed.

Table 7 shows the encodings of the remaining fields of the
ROWA and ROWR packets. An ROWA packet is specified
by asserting the AV bit. This causes the specified row of the
specified bank of this device to be loaded into the associated
sense amps.

An ROWR packet is specified when AV is not asserted. An
11 bit opcode field encodes a command for one of the banks
of this device. The PRER command causes a bank and its
two associated sense amps to precharge, so another row or
an adjacent bank may be activated. The REFA (refresh-acti-
vate) command is similar to the ACT command, except the

row address comes from an internal register REFR, and
REFR is incremented at the largest bank address. The REFP
(refresh-precharge) command is identical to a PRER
command.

The NAPR, NAPRC, PDNR, ATTN, and RLXR commands
are used for managing the power dissipation of the RDRAM
and are described in more detail in

Power State Manage-

ment

on page 38. The TCEN and TCAL commands are

used to adjust the output driver slew rate and they are
described in more detail in

Current and Temperature

Control

on page 43.

Table 6: Device Field Encodings for ROWA Packet and ROWR Packet

DR4T

DR4F

Device Selection

Device Match signal (DM)

All devices (broadcast)

DM is set to 1

One device selected

DM is set to 1 if {DEVID4..DEVID0} == {0,DR3..DR0} else DM is set to 0

One device selected

DM is set to 1 if {DEVID4..DEVID0} == {1,DR3..DR0} else DM is set to 0

No packet present

DM is set to 0

Table 7: ROWA Packet and ROWR Packet Field Encodings

ROP10..ROP0 Field

Name

Command Description

2:0

---

No operation.

Row address

ACT

Activate row R8..R0 of bank BR4..BR0 of device and move device to ATTN

000

PRER

Precharge bank BR4..BR0 of this device.

000

REFA

Refresh (activate) row REFR8..REFR0 of bank BR3..BR0 of device.
Increment REFR if BR4..BR0 = 1111 (see Figure 50).

000

REFP

Precharge bank BR4..BR0 of this device after REFA (see Figure 50).

000

PDNR

Move this device into the powerdown (PDN) power state (see Figure 47).

000

NAPR

Move this device into the nap (NAP) power state (see Figure 47).

000

NAPRC

Move this device into the nap (NAP) power state conditionally

000

ATTN

Move this device into the attention (ATTN) power state (see Figure 45).

000

RLXR

Move this device into the standby (STBY) power state (see Figure 46).

001

TCAL

Temperature calibrate this device (see Figure 52).

010

TCEN

Temperature calibrate/enable this device (see Figure 52).

000

NOROP

No operation.

a. The DM (Device Match signal) value is determined by the DR4T,DR4F, DR3..DR0 field of the ROWA and ROWR packets. See Table 6.
b. The ATTN command does not cause a RLX-to-ATTN transition for a broadcast operation (DR4T/DR4F=1/1).
c. An

entry indicates which commands may be combined. For instance, the three commands PRER/NAPRC/RLXR may be specified in one ROP value (011000111000).

Page 9

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

Table 8 shows the COP field encoding. The device must be
in the ATTN power state in order to receive COLC packets.
The COLC packet is used primarily to specify RD (read) and
WR (write) commands. Retire operations (moving data from
the write buffer to a sense amp) happen automatically. See
Figure 17 for a more detailed description.

The COLC packet can also specify a PREC command,
which precharges a bank and its associated sense amps. The
RDA/WRA commands are equivalent to combining RD/WR
with a PREC. RLXC (relax) performs a power mode transi-
tion. See

Power State Management

on page 38.

Table 9 shows the COLM and COLX field encodings. The
M bit is asserted to specify a COLM packet with two 8 bit
bytemask fields MA and MB. If the M bit is not asserted, an
COLX is specified. It has device and bank address fields,
and an opcode field. The primary use of the COLX packet is
to permit an independent PREX (precharge) command to be

specified without consuming control bandwidth on the ROW
pins. It is also used for the CAL(calibrate) and SAM
(sample) current control commands (see

Current and

Temperature Control

on page 43, and for the RLXX power

mode command (see

Power State Management

on page

38).

Table 8: COLC Packet Field Encodings

DC4.. DC0
(select device)

COP3..0 Name

Command Description

----

-----

No operation.

/= (DEVID4 ..0)

-----

Retire write buffer of this device.

== (DEVID4 ..0)

x000

NOCOP

Retire write buffer of this device.

== (DEVID4 ..0)

x001

Retire write buffer of this device, then write column C6..C0 of bank BC4..BC0 to write buffer.

== (DEVID4 ..0)

x010

RSRV

Reserved, no operation.

== (DEVID4 ..0)

x011

Read column C6..C0 of bank BC4..BC0 of this device.

== (DEVID4 ..0)

x100

PREC

Retire write buffer of this device, then precharge bank BC4..BC0 (see Figure 14).

== (DEVID4 ..0)

x101

WRA

Same as WR, but precharge bank BC4..BC0 after write buffer (with new data) is retired.

== (DEVID4 ..0)

x110

RSRV

Reserved, no operation.

== (DEVID4 ..0)

x111

RDA

Same as RD, but precharge bank BC4..BC0 afterward.

== (DEVID4 ..0)

1xxx

RLXC

Move this device into the standby (STBY) power state (see Figure 46).

means not equal,

means equal.

b. An

entry indicates which commands may be combined. For instance, the two commands WR/RLXC may be specified in one COP value (1001).

Table 9: COLM Packet and COLX Packet Field Encodings

DX4 .. DX0
(selects device)

XOP4..0

Name

Command Description

----

MSK

MB/MA bytemasks used by WR/WRA.

/= (DEVID4 ..0)

No operation.

== (DEVID4 ..0)

00000

NOXOP

No operation.

== (DEVID4 ..0)

1xxx0

PREX

Precharge bank BX4..BX0 of this device (see Figure 14).

== (DEVID4 ..0)

x10x0

CAL

Calibrate (drive) I

current for this device (see Figure 51).

== (DEVID4 ..0)

x11x0

CAL/SAM

Calibrate (drive) and Sample ( update) I

current for this device (see Figure 51).

== (DEVID4 ..0)

xxx10

RLXX

Move this device into the standby (STBY) power state (see Figure 46).

== (DEVID4 ..0)

xxxx1

RSRV

Reserved, no operation.

a. An

entry indicates which commands may be combined. For instance, the two commands PREX/RLXX may be specified in one XOP value (10010)

Page 10

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

DQ Packet Timing

Figure 4 shows the timing relationship of COLC packets
with D and Q data packets. This document uses a specific
convention for measuring time intervals between packets: all
packets on the ROW and COL pins (ROWA, ROWR,
COLC, COLM, COLX) use the trailing edge of the packet as
a reference point, and all packets on the DQA/DQB pins (D
and Q) use the leading edge of the packet as a reference
point.

An RD or RDA command will transmit a dualoct of read
data Q a time t

CAC

later. This time includes one to five

cycles of round-trip propagation delay on the Channel. The
t

CAC

parameter may be programmed to a one of a range of

values ( 8, 9, 10, 11, or 12 t

CYCLE

). The value chosen

depends upon the number of RDRAM devices on the
Channel and the RDRAM timing bin. See Figure 39 for
more information.

A WR or WRA command will receive a dualoct of write
data D a time t

CWD

later. This time does not need to include

the round-trip propagation time of the Channel since the
COLC and D packets are traveling in the same direction.

When a Q packet follows a D packet (shown in the left half
of the figure), a gap (t

CAC

-t

CWD

) will automatically appear

between them because the t

CWD

value is always less than the

CAC

value. There will be no gap between the two COLC

packets with the WR and RD commands which schedule the
D and Q packets.

When a D packet follows a Q packet (shown in the right half
of the figure), no gap is needed between them because the
t

CWD

value is less than the t

CAC

value. However, , a gap of

CAC

-t

CWD

or greater must be inserted between the COLC

packets with the RD WR commands by the controller so the
Q and D packets do not overlap.

COLM Packet to D Packet Mapping

Figure 5 shows a write operation initiated by a WR
command in a COLC packet. If a subset of the 16 bytes of
write data are to be written, then a COLM packet is trans-
mitted on the COL pins a time t

RTR

after the COLC packet

containing the WR command. The M bit of the COLM
packet is set to indicate that it contains the MA and MB
mask fields. Note that this COLM packet is aligned with the
COLC packet which causes the write buffer to be retired.
See Figure 17 for more details.

If all 16 bytes of the D data packet are to be written, then no
further control information is required. The packet slot that
would have been used by the COLM packet (t

RTR

after the

COLC packet) is available to be used as an COLX packet.
This could be used for a PREX precharge command or for a

housekeeping command (this case is not shown). The M bit
is not asserted in an COLX packet and causes all 16 bytes of
the previous WR to be written unconditionally. Note that a
RD command will never need a COLM packet, and will
always be able to use the COLX packet option (a read opera-
tion has no need for the byte-write-enable control bits).

Figure 5 also shows the mapping between the MA and MB
fields of the COLM packet and bytes of the D packet on the
DQA and DQB pins. Each mask bit controls whether a byte
of data is written (=1) or not written (=0).

Figure 4: Read (Q) and Write (D) Data Packet - Timing for t

CAC

= 8, 9, 10, 11, or 12 t

CYCLE

CTM/CFM

DQA8..0
DQB8..0

COL4

..COL0

ROW2

..ROW0

RD b1

Q (a1)

WR a1

D (a1)

CWD

RD c1

Q (a1)

CAC

-t

CWD

This gap on the DQA/DQB pins appears automatically

This gap on the COL pins must be inserted by the controller

CAC

WR d1

D (d1)

CAC

-t

CWD

WR d1

Q (c1)

· · ·

WR d1

· · ·

D (d1)

Q (c1)

D (d1)

Q (c1)

· · ·

Q (a1)

Q (b1)

WR d1

D (d1)

Q (c1)

Page 11

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

Figure 5: Mapping Between COLM Packet and D Packet for WR Command

CTM/CFM

COL4

COL3

COL2

COL1

COL0

MA7 MA5 MA3 MA1

M=1 MA6 MA4 MA2 MA0

MB7 MB4 MB1

MB6 MB3 MB0

MB5 MB2

CTM/CFM

DQA8..0
DQB8..0

COL4

..COL0

ROW2

..ROW0

MSK (a1)

retire (a1)

WR a1

D (a1)

ACT b0

ACT a0

Transaction a: WR

a0 = {Da,Ba,Ra}

a1 = {Da,Ba,Ca1}

a3 = {Da,Ba}

RTR

CTM/CFM

DQB8

DQB7

DQB1

DQB0

DB71

DB8

DB17 DB26 DB35 DB45 DB53 DB62

DB7

DB16 DB25 DB34 DB44 DB52 DB61 DB70

DB1

DB10 DB19 DB28 DB37 DB46 DB55 DB64

DB0

DB9

DB18 DB27 DB36 DB45 DB54 DB63

COLM Packet

PRER a2

DQA8

DQA7

·
·
·

DQA1

DQA0

D Packet

MB0

DA71

DA8

DA17 DA26 DA35 DA45 DA53 DA62

DA7

DA16 DA25 DA34 DA44 DA52 DA61 DA70

DA1

DA10 DA19 DA28 DA37 DA46 DA55 DA64

DA0

DA9

DA18 DA27 DA36 DA45 DA54 DA63

MA0

MB1

MA1

MB2

MA2

MB3

MA3

MB4

MA4

MB5

MA5

MB6

MA6

MB7

MA7

·
·
·

CWD

Each bit of the MB7..MB0 field

controls writing (=1) or no writing
(=0) of the indicated DB bits when

the M bit of the COLM packet is one.

Each bit of the MA7..MA0 field

controls writing (=1) or no writing
(=0) of the indicated DA bits when

the M bit of the COLM packet is one.

When M=1, the MA and MB

fields control writing of

individual data bytes.

When M=0, all data bytes are

written unconditionally.

Page 12

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

ROW-to-ROW Packet Interaction

Figure 6 shows two packets on the ROW pins separated by
an interval t

RRDELAY

which depends upon the packet

contents. No other ROW packets are sent to banks
{Ba,Ba+1,Ba-1} between packet

and packet

unless

noted otherwise. Table 10 summarizes the t

RRDELAY

values

for all possible cases.

Cases RR1 through RR4 show two successive ACT
commands. In case RR1, there is no restriction since the
ACT commands are to different devices. In case RR2, the
t

restriction applies to the same device with non-adjacent

banks. Cases RR3 and RR4 are illegal (as shown) since bank
Ba needs to be precharged. If a PRER to Ba, Ba+1, or Ba-1
is inserted, t

RRDELAY

is t

RAS

to the PRER command,

and t

to the next ACT).

Cases RR5 through RR8 show an ACT command followed
by a PRER command. In cases RR5 and RR6, there are no
restrictions since the commands are to different devices or to
non-adjacent banks of the same device. In cases RR7 and
RR8, the t

RAS

restriction means the activated bank must wait

before it can be precharged.

Cases RR9 through RR12 show a PRER command followed
by an ACT command. In cases RR9 and RR10, there are
essentially no restrictions since the commands are to
different devices or to non-adjacent banks of the same
device. RR10a and RR10b depend upon whether a bracketed
bank (Ba

1) is precharged or activated. In cases RR11 and

RR12, the same and adjacent banks must all wait t

for the

sense amp and bank to precharge before being activated.

Figure 6: ROW-to-ROW Packet Interaction- Timing

CTM/CFM

DQA8..0
DQB8..0

COL4

..COL0

ROW2

..ROW0

Transaction a: ROPa

Transaction b: ROPb

a0 = {Da,Ba,Ra}
b0= {Db,Bb,Rb}

RRDELAY

ROPa a0

ROPb b0

Table 10: ROW-to-ROW Packet Interaction - Rules

Case #

ROPa

ROPb

RRDELAY

Example

RR1

ACT

/= Da

xxxx

x..x

PACKET

Figure 11

RR2

ACT

== Da

/= {Ba,Ba+1,Ba-1}

x..x

Figure 11

RR3

ACT

== Da

== {Ba+1,Ba-1}

x..x

- illegal unless PRER to Ba/Ba+1/Ba-1

Figure 10

RR4

ACT

== Da

== {Ba}

x..x

- illegal unless PRER to Ba/Ba+1/Ba-1

Figure 10

RR5

ACT

PRER

/= Da

xxxx

x..x

PACKET

Figure 11

RR6

ACT

PRER

== Da

/= {Ba,Ba+1,Ba-1}

x..x

PACKET

Figure 11

RR7

ACT

PRER

== Da

== { Ba+1,Ba-1}

x..x

RAS

Figure 10

RR8

ACT

PRER

== Da

== {Ba}

x..x

RAS

Figure 15

RR9

PRER

ACT

/= Da

xxxx

x..x

PACKET

Figure 12

RR10

PRER

ACT

== Da

/= {Ba,Ba

1,Ba

x..x

PACKET

Figure 12

RR10a

PRER

ACT

== Da

== {Ba+2}

x..x

PACKET

if Ba+1 is precharged/activated.

RR10b

PRER

ACT

== Da

== {Ba-2}

x..x

PACKET

if Ba-1 is precharged/activated.

RR11

PRER

ACT

== Da

== {Ba+1,Ba-1}

x..x

Figure 10

RR12

PRER

ACT

== Da

== {Ba}

x..x

Figure 10

RR13

PRER

/= Da

xxxx

x..x

PACKET

Figure 12

RR14

PRER

== Da

/= {Ba,Ba+1,Ba-1}

x..x

Figure 12

RR15

PRER

== Da

== {Ba+1,Ba-1}

x..x

Figure 12

RR16

PRER

== Da

== Ba

x..x

Figure 12

Page 13

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

ROW-to-ROW Interaction - contin-
ued

Cases RR13 through RR16 summarize the combinations of
two successive PRER commands. In case RR13 there is no
restriction since two devices are addressed. In RR14, t

applies, since the same device is addressed. In RR15 and
RR16, the same bank or an adjacent bank may be given
repeated PRER commands with only the t

restriction.

Two adjacent banks can

t be activate simultaneously. A

precharge command to one bank will thus affect the state of
the adjacent banks (and sense amps). If bank Ba is activate
and a PRER is directed to Ba, then bank Ba will be
precharged along with sense amps Ba-1/Ba and Ba/Ba+1. If
bank Ba+1 is activate and a PRER is directed to Ba, then
bank Ba+1 will be precharged along with sense amps
Ba/Ba+1 and Ba+1/Ba+2. If bank Ba-1 is activate and a
PRER is directed to Ba, then bank Ba-1 will be precharged
along with sense amps Ba/Ba-1 and Ba-1/Ba-2.

A ROW packet may contain commands other than ACT or
PRER. The REFA and REFP commands are equivalent to
ACT and PRER for interaction analysis purposes. The inter-
action rules of the NAPR, NAPRC, PDNR, RLXR, ATTN,
TCAL, and TCEN commands are discussed in later sections
(see Table 7 for cross-ref).

ROW-to-COL Packet Interaction

Figure 7 shows two packets on the ROW and COL pins.
They must be separated by an interval t

RCDELAY

which

depends upon the packet contents. Table 11 summarizes the
t

RCDELAY

values for all possible cases. Note that if the COL

packet is earlier than the ROW packet, it is considered a
COL-to-ROW packet interaction.

Cases RC1 through RC5 summarize the rules when the
ROW packet has an ACT command. Figure 15 and
Figure 16 show examples of RC5 - an activation followed by
a read or write. RC4 is an illegal situation, since a read or
write of a precharged banks is being attempted (remember
that for a bank to be activated, adjacent banks must be
precharged). In cases RC1, RC2, and RC3, there is no inter-
action of the ROW and COL packets.

Cases RC6 through RC8 summarize the rules when the
ROW packet has a PRER command. There is either no inter-
action (RC6 through RC9) or an illegal situation with a read
or write of a precharged bank (RC9).

The COL pins can also schedule a precharge operation with
a RDA, WRA, or PREC command in a COLC packet or a
PREX command in a COLX packet. The constraints of these
precharge operations may be converted to equivalent PRER
command constraints using the rules summarized in
Figure 14.

Figure 7: ROW-to-COL Packet Interaction- Timing

CTM/CFM

DQA8..0
DQB8..0

COL4

..COL0

ROW2

..ROW0

Transaction a: ROPa
Transaction b: COPb

a0 = {Da,Ba,Ra}

b1= {Db,Bb,Cb1}

RCDELAY

ROPa a0

COPb b1

Table 11: ROW-to-COL Packet Interaction - Rules

Case #

ROPa

COPb

Cb1

RCDELAY

Example

RC1

ACT

NOCOP,RD,retire

/= Da

xxxx

x..x

RC2

ACT

NOCOP

== Da

xxxx

x..x

RC3

ACT

RD,retire

== Da

/= {Ba,Ba+1,Ba-1}

x..x

RC4

ACT

RD,retire

== Da

== {Ba+1,Ba-1}

x..x

Illegal

RC5

ACT

RD,retire

== Da

== Ba

x..x

RCD

Figure 15

RC6

PRER

NOCOP,RD,retire

/= Da

xxxx

x..x

RC7

PRER

NOCOP

== Da

xxxx

x..x

RC8

PRER

RD,retire

== Da

/= {Ba,Ba+1,Ba-1}

x..x

RC9

PRER

RD,retire

== Da

== {Ba+1,Ba-1}

x..x

Illegal

Page 14

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

COL-to-COL Packet Interaction

Figure 8 shows three arbitrary packets on the COL pins.
Packets

and

must be separated by an interval

CCDELAY

which depends upon the command and address

values in all three packets. Table 12 summarizes the
t

CCDELAY

values for all possible cases.

Cases CC1 through CC5 summarize the rules for every situ-
ation other than the case when COPb is a WR command and
COPc is a RD command. In CC3, when a RD command is
followed by a WR command, a gap of t

CAC

-t

CWD

must be

inserted between the two COL packets. See Figure 4 for
more explanation of why this gap is needed. For cases CC1,

CC2, CC4, and CC5, there is no restriction (t

CCDELAY

In cases CC6 through CC10, COPb is a WR command and
COPc is a RD command. The t

CCDELAY

value needed

between these two packets depends upon the command and
address in the packet with COPa. In particular, in case CC6
when there is WR-WR-RD command sequence directed to
the same device, a gap will be needed between the packets
with COPb and COPc. The gap will need a COLC packet
with a NOCOP command directed to any device in order to
force an automatic retire to take place. Figure 18 (right)
provides a more detailed explanation of this case.

In case CC10, there is a RD-WR-RD sequence directed to
the same device. If a prior write to the same device is unre-
tired when COPa is issued, then a gap will be needed
between the packets with COPb and COPc as in case CC6.
The gap will need a COLC packet with a NOCOP command
directed to any device in order to force an automatic retire to
take place.

Cases CC7, CC8, and CC9 have no restriction (t

CCDELAY

For the purposes of analyzing COL-to-ROW interactions,
the PREC, WRA, and RDA commands of the COLC packet
are equivalent to the NOCOP, WR, and RD commands.
These commands also cause a precharge operation PREC to
take place. This precharge may be converted to an equiva-
lent PRER command on the ROW pins using the rules
summarized in Figure 14.

Figure 8: COL-to-COL Packet Interaction- Timing

CTM/CFM

DQA8..0
DQB8..0

COL4

..COL0

ROW2

..ROW0

COPa a1

Transaction a: COPa

COPc c1

Transaction b: COPb

Transaction c: COPc

a1 = {Da,Ba,Ca1}

b1 = {Db,Bb,Cb1}

c1 = {Dc,Bc,Cc1}

CCDELAY

COPb b1

Table 12: COL-to-COL Packet Interaction - Rules

Case #

COPa

Ca1

COPb

Cb1

COPc

Cc1

CCDELAY

Example

CC1

xxxx

xxxxx

x..x

NOCOP

Cb1

xxxx

xxxxx

x..x

CC2

xxxx

xxxxx

x..x

RD,WR

Cb1

NOCOP

xxxxx

x..x

CC3

xxxx

xxxxx

x..x

Cb1

xxxxx

x..x

CAC

-t

CWD

Figure 4

CC4

xxxx

xxxxx

x..x

Cb1

xxxxx

x..x

Figure 15

CC5

xxxx

xxxxx

x..x

Cb1

xxxxx

x..x

Figure 16

CC6

== Db

x..x

Cb1

== Db

x..x

RTR

Figure 18

CC7

== Db

x..x

Cb1

/= Db

x..x

CC8

/= Db

x..x

Cb1

== Db

x..x

CC9

NOCOP

== Db

x..x

Cb1

== Db

x..x

CC10

== Db

x..x

Cb1

== Db

x..x

Page 15

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

COL-to-ROW Packet Interaction

Figure 9 shows arbitrary packets on the COL and ROW pins.
They must be separated by an interval t

CRDELAY

which

depends upon the command and address values in the
packets. Table 13 summarizes the t

CRDELAY

value for all

possible cases.

Cases CR1, CR2, CR3, and CR9 show no interaction
between the COL and ROW packets, either because one of
the commands is a NOP or because the packets are directed
to different devices or to non-adjacent banks.

Case CR4 is illegal because an already-activated bank is to
be re-activated without being precharged Case CR5 is illegal
because an adjacent bank can't be activated or precharged
until bank Ba is precharged first.

In case CR6, the COLC packet contains a RD command, and
the ROW packet contains a PRER command for the same
bank. The t

RDP

parameter specifies the required spacing.

Likewise, in case CR7, the COLC packet causes an auto-
matic retire to take place, and the ROW packet contains a
PRER command for the same bank. The t

RTP

parameter

specifies the required spacing.

Case CR8 is labeled

Hazardous

because a WR command

should always be followed by an automatic retire before a
precharge is scheduled. Figure 19 shows an example of what
can happen when the retire is not able to happen before the
precharge.

For the purposes of analyzing COL-to-ROW interactions,
the PREC, WRA, and RDA commands of the COLC packet
are equivalent to the NOCOP, WR, and RD commands.
These commands also cause a precharge operation to take
place. This precharge may converted to an equivalent PRER
command on the ROW pins using the rules summarized in
Figure 14.

A ROW packet may contain commands other than ACT or
PRER. The REFA and REFP commands are equivalent to
ACT and PRER for interaction analysis purposes. The inter-
action rules of the NAPR, PDNR, and RLXR commands are
discussed in a later section.

Figure 9: COL-to-ROW Packet Interaction- Timing

CTM/CFM

DQA8..0
DQB8..0

COL4

..COL0

ROW2

..ROW0

Transaction a: COPa

Transaction b: ROPb

a1= {Da,Ba,Ca1}

b0= {Db,Bb,Rb}

CRDELAY

ROPb b0

COPa a1

Table 13: COL-to-ROW Packet Interaction - Rules

Case #

COPa

Ca1

ROPb

CRDELAY

Example

CR1

NOCOP

Ca1

x..x

xxxxx

xxxx

x..x

CR2

RD/WR

Ca1

x..x

/= Da

xxxx

x..x

CR3

RD/WR

Ca1

x..x

== Da

/= {Ba,Ba+1,Ba-1}

x..x

CR4

RD/WR

Ca1

ACT

== Da

== {Ba}

x..x

Illegal

CR5

RD/WR

Ca1

ACT

== Da

== {Ba+1,Ba-1}

x..x

Illegal

CR6

Ca1

PRER

== Da

== {Ba,Ba+1,Ba-1}

x..x

RDP

Figure 15

CR7

retire

Ca1

PRER

== Da

== {Ba,Ba+1,Ba-1}

x..x

RTP

Figure 16

CR8

Ca1

PRER

== Da

== {Ba,Ba+1,Ba-1}

x..x

Figure 19

CR9

xxxx

Ca1

NOROP

xxxxx

xxxx

x..x

a. This is any command which permits the write buffer of device Da to retire (see Table 8).

is the bank address in the write buffer.

b. This situation is hazardous because the write buffer will be left unretired while the targeted bank is precharged. See Figure 19.

Page 16

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

ROW-to-ROW Examples

Figure 10 shows examples of some of the the ROW-to-
ROW packet spacings from Table 10. A complete sequence
of activate and precharge commands is directed to a bank.
The RR8 and RR12 rules apply to this sequence. In addition
to satisfying the t

RAS

and t

timing parameters, the separa-

tion between ACT commands to the same bank must also
satisfy the t

timing parameter (RR4).

When a bank is activated, it is necessary for adjacent banks
to remain precharged. As a result, the adjacent banks will
also satisfy parallel timing constraints; in the example, the
RR11 and RR3 rules are analogous to the RR12 and RR4
rules.

Figure 11 shows examples of the ACT-to-ACT (RR1, RR2)
and ACT-to-PRER (RR5, RR6) command spacings from
Table 10. In general, the commands in ROW packets may be
spaced an interval t

PACKET

apart unless they are directed to

the same or adjacent banks or unless they are a similar
command type (both PRER or both ACT) directed to the
same device.

Figure 10: Row Packet Example

CTM/CFM

DQA8..0
DQB8..0

COL4

..COL0

ROW2

..ROW0

ACT a0

PRER a1

RAS

a0 = {Da,Ba,Ra}

a1 = {Da,Ba+1}

b0 = {Da,Ba+1,Rb}

Same Device

Adjacent Bank

RR7

Same Device

Adjacent Bank

RR11

ACT b0

b0 = {Da,Ba,Rb}

Same Device

Same Bank

RR12

b0 = {Da,Ba+1,Rb}

Same Device

Adjacent Bank

RR3

b0 = {Da,Ba,Rb}

Same Device

Same Bank

RR4

Figure 11: Row Packet Example

CTM/CFM

DQA8..0
DQB8..0

COL4

..COL0

ROW2

..ROW0

ACT a0

PRER b0

PACKET

ACT c0

a0 = {Da,Ba,Ra}

b0 = {Db,Bb,Rb}

c0 = {Da,Bc,Rc}

Different Device

Any Bank

Same Device

Non-adjacent Bank

RR1
RR2

ACT a0

ACT b0

PRER c0

b0 = {Db,Bb,Rb}

c0 = {Da,Bc,Rc}

Different Device

Any Bank

Same Device

Non-adjacent Bank

RR5
RR6

ACT a0

PACKET

Page 17

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

Figure 12 shows examples of the PRER-to-PRER (RR13,
RR14) and PRER-to-ACT (RR9, RR10) command spacings
from Table 10. The RR15 and RR16 cases (PRER-to-PRER
to same or adjacent banks) are not shown, but are similar to
RR14. In general, the commands in ROW packets may be

spaced an interval t

PACKET

apart unless they are directed to

the same or adjacent banks or unless they are a similar
command type (both PRER or both ACT) directed to the
same device.

Row and Column Cycle Description

Activate: A row cycle begins with the activate (ACT) opera-
tion. The activation process is destructive; the act of sensing
the value of a bit in a bank's storage cell transfers the bit to
the sense amp, but leaves the original bit in the storage cell
with an incorrect value.

Restore: Because the activation process is destructive, a
hidden operation called restore is automatically performed.
The restore operation rewrites the bits in the sense amp back
into the storage cells of the activated row of the bank.

Read/Write: While the restore operation takes place, the
sense amp may be read (RD) and written (WR) using
column operations. If new data is written into the sense amp,
it is automatically forwarded to the storage cells of the bank
so the data in the activated row and the data in the sense amp
remain identical.

Precharge: When both the restore operation and the column
operations are completed, the sense amp and bank are
precharged (PRE). This leaves them in the proper state to
begin another activate operation.

Intervals: The activate operation requires the interval
t

RCD,MIN

to complete. The hidden restore operation requires

the interval t

RAS,MIN

- t

RCD,MIN

to complete. Column read

and write operations are also performed during the t

RAS,MIN

- t

RCD,MIN

interval (if more than about four column opera-

tions are performed, this interval must be increased). The
precharge operation requires the interval t

RP,MIN

complete.

Adjacent Banks: An RDRAM with a

designation

(512Kx32sx18) indicates it contains

split banks

. This

means the sense amps are shared between two adjacent
banks. The only exception is that sense amp 0, 15, 30, and
31 are not shared. When a row in a bank is activated, the two
adjacent sense amps are connected to (associated with) that
bank and are not available for use by the two adjacent banks.
These two adjacent banks must remain precharged while the
selected bank goes through its activate, restore, read/write,
and precharge operations.

For example (referring to the block diagram of Figure 2), if
bank 5 is accessed, sense amp 4/5 and sense amp 5/6 will
both be loaded with one of the 512 rows (with 1024 bytes
loaded into each sense amp from the 2Kbyte row - 512 bytes
to the DQA side and 512 bytes to the DQB side). While this
row from bank 5 is being accessed, no rows may be accessed
in banks 4 or 6 because of the sense amp sharing.

Figure 12: Row Packet Examples

CTM/CFM

DQA8..0

DQB8..0

COL4

..COL0

ROW2

..ROW0

PRER a0

ACT b0

PACKET

PRER c0

a0 = {Da,Ba,Ra}

b0 = {Db,Bb,Rb}

c0 = {Da,Bc,Rc}

Different Device

Any Bank

Same Device

Non-adjacent Bank

RR13
RR14

PRER a0

PRER b0

ACT c0

b0 = {Db,Bb,Rb}

c0 = {Da,Bc,Rc}

Different Device

Any Bank

Same Device

Non-adjacent Bank

RR9

RR10

PRER a0

c0 = {Da,Ba+1Rc}

Same Device

Same Bank

RR16

c0 = {Da,Ba,Rc}

Same Device

Adjacent Bank

RR15

PACKET

Page 18

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

Precharge Mechanisms

Figure 13 shows an example of precharge with the ROWR
packet mechanism. The PRER command must occur a time

RAS

after the ACT command, and a time t

before the next

ACT command. This timing will serve as a baseline aginst
which the other precharge mechanisms can be compared.

Figure 14 (top) shows an example of precharge with a RDA
command. A bank is activated with an ROWA packet on the
ROW pins. Then, a series of four dualocts are read with RD
commands in COLC packets on the COL pins. The fourth of
these commands is a RDA, which causes the bank to auto-
matically precharge when the final read has finished. The
timing of this automatic precharge is equivalent to a PRER
command in an ROWR packet on the ROW pins that is
offset a time t

OFFP

from the COLC packet with the RDA

command. The RDA command should be treated as a RD
command in a COLC packet as well as a simultaneous (but
offset) PRER command in an ROWR packet when analyzing
interactions with other packets.

Figure 14 (middle) shows an example of precharge with a
WRA command. As in the RDA example, a bank is acti-
vated with an ROWA packet on the ROW pins. Then, two
dualocts are written with WR commands in COLC packets
on the COL pins. The second of these commands is a WRA,
which causes the bank to automatically precharge when the
final write has been retired. The timing of this automatic
precharge is equivalent to a PRER command in an ROWR
packet on the ROW pins that is offset a time t

OFFP

from the

COLC packet that causes the automatic retire. The WRA
command should be treated as a WR command in a COLC
packet as well as a simultaneous (but offset) PRER
command in an ROWR packet when analyzing interactions
with other packets. Note that the automatic retire is triggered
by a COLC packet a time t

RTR

after the COLC packet with

the WR command unless the second COLC contains a RD
command to the same device. This is described in more
detail in Figure 17.

Figure 14 (bottom) shows an example of precharge with a
PREX command in an COLX packet. A bank is activated
with an ROWA packet on the ROW pins. Then, a series of
four dualocts are read with RD commands in COLC packets
on the COL pins. The fourth of these COLC packets
includes an COLX packet with a PREX command. This
causes the bank to precharge with timing equivalent to a
PRER command in an ROWR packet on the ROW pins that
is offset a time t

OFFP

from the COLX packet with the PREX

command.

Figure 13: Precharge via PRER Command in ROWR Packet

CTM/CFM

DQA8..0

DQB8..0

COL4

..COL0

ROW2

..ROW0

ACT a0

PRER a5

RAS

a0 = {Da,Ba,Ra}

a5 = {Da,Ba}

b0 = {Da,Ba,Rb}

ACT b0

Page 19

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

Figure 14: Offsets for Alternate Precharge Mechanisms

CTM/CFM

DQA8..0

DQB8..0

COL4

..COL0

ROW2

..ROW0

CTM/CFM

DQA8..0

DQB8..0

COL4

..COL0

ROW2

..ROW0

CTM/CFM

DQA8..0

DQB8..0

COL4

..COL0

ROW2

..ROW0

RD a1

ACT a0

RD a2

Q (a2)

Q (a1)

ACT b0

MSK (a2)

MSK (a1)

retire (a1)

OFFP

WR a1

D (a2)

D (a1)

ACT b0

ACT a0

Transaction a: RD

a0 = {Da,Ba,Ra}

a5 = {Da,Ba}

COLC Packet: RDA Precharge Offset

COLC Packet: WDA Precharge Offset

Transaction a: WR

a0 = {Da,Ba,Ra}

a1 = {Da,Ba,Ca1}

a2 = {Da,Ba,Ca2}

a5 = {Da,Ba}

COLX Packet: PREX Precharge Offset

RD a3

Q (a4)

Q (a3)

RDA a4

PRER a5

The RDA precharge is equivalent to a PRER command here

OFFP

PRER a5

The WRA precharge (triggered by the automatic retire) is equivalent to a PRER command here

WRA a2

retire (a2)

RTR

a3 = {Da,Ba,Ca3}

a4 = {Da,Ba,Ca4}

a1 = {Da,Ba,Ca1}

a2 = {Da,Ba,Ca2}

RD a1

ACT a0

RD a2

Q (a2)

Q (a1)

ACT b0

OFFP

Transaction a: RD

a0 = {Da,Ba,Ra}

a5 = {Da,Ba}

RD a3

Q (a4)

Q (a3)

PRER a5

The PREX precharge command is equivalent to a PRER command here

a3 = {Da,Ba,Ca3}

a4 = {Da,Ba,Ca4}

a1 = {Da,Ba,Ca1}

a2 = {Da,Ba,Ca2}

RD a4

PREX a5

Page 20

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

Read Transaction - Example

Figure 15 shows an example of a read transaction. It begins
by activating a bank with an ACT a0 command in an ROWA
packet. A time t

RCD

later a RD a1 command is issued in a

COLC packet. Note that the ACT command includes the
device, bank, and row address (abbreviated as a0) while the
RD command includes device, bank, and column address
(abbreviated as a1). A time t

CAC

after the RD command the

read data dualoct Q(a1) is returned by the device. Note that
the packets on the ROW and COL pins use the end of the
packet as a timing reference point, while the packets on the
DQA/DQB pins use the beginning of the packet as a timing
reference point.

A time t

after the first COLC packet on the COL pins a

second is issued. It contains a RD a2 command. The a2
address has the same device and bank address as the a1
address (and a0 address), but a different column address. A
time t

CAC

after the second RD command a second read data

dualoct Q(a2) is returned by the device.

includes the same device and bank address as the a0, a1, and
a2 addresses. The PRER command must occur a time t

RAS

or more after the original ACT command (the activation
operation in any DRAM is destructive, and the contents of
the selected row must be restored from the two associated
sense amps of the bank during the t

RAS

interval). The PRER

command must also occur a time t

RDP

or more after the last

RD command. Note that the t

RDP

value shown is greater

than the t

RDP,MIN

specification in Table 22. This transaction

example reads two dualocts, but there is actually enough
time to read three dualocts before t

RDP

becomes the limiting

parameter rather than t

RAS

. If four dualocts were read, the

packet with PRER would need to shift right (be delayed) by
one t

CYCLE

(note - this case is not shown).

Finally, an ACT b0 command is issued in an ROWR packet
on the ROW pins. The second ACT command must occur a
time t

or more after the first ACT command and a time t

or more after the PRER command. This ensures that the
bank and its associated sense amps are precharged. This
example assumes that the second transaction has the same
device and bank address as the first transaction, but a
different row address. Transaction b may not be started until
transaction a has finished. However, transactions to other
banks or other devices may be issued during transaction a.

Figure 15: Read Transaction Example

CTM/CFM

DQA8..0

DQB8..0

COL4

..COL0

ROW2

..ROW0

RD a1

ACT a0

PRER a3

RD a2

Q (a2)

RCD

CAC

Q (a1)

ACT b0

RAS

Transaction a: RD

a0 = {Da,Ba,Ra}

a1 = {Da,Ba,Ca1}

a2 = {Da,Ba,Ca2}

a3 = {Da,Ba}

CAC

RDP

Transaction b: xx

b0 = {Da,Ba,Rb}

Page 21

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

Write Transaction - Example

Figure 16 shows an example of a write transaction. It begins
by activating a bank with an ACT a0 command in an ROWA
packet. A time t

RCD

-t

RTR

later a WR a1 command is issued

in a COLC packet (note that the t

RCD

interval is measured to

the end of the COLC packet with the first retire command).
Note that the ACT command includes the device, bank, and
row address (abbreviated as a0) while the WR command
includes device, bank, and column address (abbreviated as
a1). A time t

CWD

after the WR command the write data

dualoct D(a1) is issued. Note that the packets on the ROW
and COL pins use the end of the packet as a timing reference
point, while the packets on the DQA/DQB pins use the
beginning of the packet as a timing reference point.

A time t

after the first COLC packet on the COL pins a

second COLC packet is issued. It contains a WR a2
command. The a2 address has the same device and bank
address as the a1 address (and a0 address), but a different
column address. A time t

CWD

after the second WR

command a second write data dualoct D(a2) is issued.

A time t

RTR

after each WR command an optional COLM

packet MSK (a1) is issued, and at the same time a COLC
packet is issued causing the write buffer to automatically
retire. See Figure 17 for more detail on the write/retire
mechanism. If a COLM packet is not used, all data bytes are
unconditionally written. If the COLC packet which causes

the write buffer to retire is delayed, then the COLM packet
(if used) must also be delayed.

Next, a PRER a3 command is issued in an ROWR packet on
the ROW pins. This causes the bank to precharge so that a
different row may be activated in a subsequent transaction or
so that an adjacent bank may be activated. The a3 address
includes the same device and bank address as the a0, a1, and
a2 addresses. The PRER command must occur a time t

RAS

interval).

A PRER a3 command is issued in an ROWR packet on the
ROW pins. The PRER command must occur a time t

RTP

more after the last COLC which causes an automatic retire.

Finally, an ACT b0 command is issued in an ROWR packet
on the ROW pins. The second ACT command must occur a
time t

or more after the first ACT command and a time t

Figure 16: Write Transaction Example

CTM/CFM

DQA8..0

DQB8..0

COL4

..COL0

ROW2

..ROW0

MSK (a2)

retire (a2)

MSK (a1)

retire (a1)

WR a1

PRER a3

WR a2

D (a2)

RCD

D (a1)

ACT b0

ACT a0

CWD

Transaction a: WR

a0 = {Da,Ba,Ra}

a1 = {Da,Ba,Ca1}

a2 = {Da,Ba,Ca2}

a3 = {Da,Ba}

CWD

RTR

RAS

RTR

RTP

Transaction b: xx

b0 = {Da,Ba,Rb}

Page 22

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

Write/Retire - Examples

The process of writing a dualoct into a sense amp of an
RDRAM bank occurs in two steps. The first step consists of
transporting the write command, write address, and write
data into the write buffer. The second step happens when the
RDRAM automatically retires the write buffer (with an
optional bytemask) into the sense amp. This two-step write
process reduces the natural turn-around delay due to the
internal bidirectional data pins.

Figure 17 (left) shows an example of this two step process.
The first COLC packet contains the WR command and an
address specifying device, bank and column. The write data
dualoct follows a time t

CWD

later. This information is loaded

into the write buffer of the specified device. The COLC

packet which follows a time t

RTR

later will retire the write

buffer. The retire will happen automatically unless (1) a
COLC packet is not framed (no COLC packet is present and
the S bit is zero), or (2) the COLC packet contains a RD
command to the same device. If the retire does not take place
at time t

RTR

after the original WR command, then the device

continues to frame COLC packets, looking for the first that
is not a RD directed to itself. A bytemask MSK(a1) may be
supplied in a COLM packet aligned with the COLC that
retires the write buffer at time t

RTR

after the WR command.

The memory controller must be aware of this two-step
write/retire process. Controller performance can be
improved, but only if the controller design accounts for
several side effects.

Figure 17 (right) shows the first of these side effects. The
first COLC packet has a WR command which loads the
address and data into the write buffer. The third COLC
causes an automatic retire of the write buffer to the sense
amp. The second and fourth COLC packets (which bracket
the retire packet) contain RD commands with the same
device, bank and column address as the original WR
command. In other words, the same dualoct address that is
written is read both before and after it is actually retired. The
first RD returns the old dualoct value from the sense amp
before it is overwritten. The second RD returns the new
dualoct value that was just written.

Figure 18 (left) shows the result of performing a RD
command to the same device in the same COLC packet slot
that would normally be used for the retire operation. The
read may be to any bank and column address; all that matters
is that it is to the same device as the WR command. The

retire operation and MSK(a1) will be delayed by a time
t

PACKET

as a result. If the RD command used the same bank

and column address as the WR command, the old data from
the sense amp would be returned. If many RD commands to
the same device were issued instead of the single one that is
shown, then the retire operation would be held off an arbi-
trarily long time. However, once a RD to another device or a
WR or NOCOP to any device is issued, the retire will take
place. Figure 18 (right) illustrates a situation in which the
controller wants to issue a WR-WR-RD COLC packet
sequence, with all commands addressed to the same device,
but addressed to any combination of banks and columns.

Figure 17: Normal Retire (left) and Retire/Read Ordering (right)

CTM/CFM

DQA8..0

DQB8..0

COL4

..COL0

ROW2

..ROW0

Transaction a: WR

a1= {Da,Ba,Ca1}

D (a1)

WR a1

CTM/CFM

DQA8..0

DQB8..0

COL4

..COL0

ROW2

..ROW0

Transaction a: WR
Transaction b: RD

a1= {Da,Ba,Ca1}

b1= {Da,Ba,Ca1}

retire (a1)
MSK (a1)

RTR

CWD

D (a1)

WR a1

retire (a1)
MSK (a1)

RTR

RD b1

RD c1

Q (b1)

CWD

Transaction c: RD

c1= {Da,Ba,Ca1}

CAC

This RD gets the old data

This RD gets the new data

Retire is automatic here unless:

CAC

(1) No COLC packet (S=0) or

(2) COLC packet is RD to device Da

Q (c1)

Page 23

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

Write/Retire Examples - continued

The RD will prevent a retire of the first WR from automati-
cally happening. But the first dualoct D(a1) in the write
buffer will be overwritten by the second WR dualoct D(b1)
if the RD command is issued in the third COLC packet.

Therefore, it is required in this situation that the controller
issue a NOCOP command in the third COLC packet,
delaying the RD command by a time of t

PACKET

. This situa-

tion is explicitly shown in Table 12 for the cases in which
t

CCDELAY

is equal to t

RTR

Figure 19 shows a possible result when a retire is held off for
a long time (an extended version of Figure 18-left). After a
WR command, a series of six RD commands are issued to
the same device (but to any combination of bank and column
addresses). In the meantime, the bank Ba to which the WR
command was originally directed is precharged, and a
different row Rc is activated. When the retire is automati-
cally performed, it is made to this new row, since the write

buffer only contains the bank and column address, not the
row address. The controller can insure that this doesn't
happen by never precharging a bank with an unretired write
buffer. Note that in a system with more than one RDRAM,
there will never be more than two RDRAMs with unretired
write buffers. This is because a WR command issued to one
device automatically retires the write buffers of all other
devices written a time t

RTR

before or earlier.

Figure 18: Retire Held Off by Read (left) and Controller Forces WWR Gap (right)

CTM/CFM

DQA8..0

DQB8..0

COL4

..COL0

ROW2

..ROW0

Transaction a: WR
Transaction b: RD

a1= {Da,Ba,Ca1}

b1= {Da,Bb,Cb1}

Transaction a: WR

Transaction b: WR

a1= {Da,Ba,Ca1}

b1= {Da,Bb,Cb1}

D (a1)

WR a1

retire (a1)
MSK (a1)

RD b1

Q (b1)

CWD

CAC

CTM/CFM

DQA8..0

DQB8..0

COL4

..COL0

ROW2

..ROW0

D (a1)

WR a1

RD c1

RTR

retire (a1)
MSK (a1)

CWD

CAC

WR b1

D (b1)

Transaction c: RD

c1= {Da,Bc,Cc1}

The controller must insert a NOCOP to retire (a1)

to make room for the data (b1) in the write buffer

The retire operation for a write can be

held off by a read to the same device

RTR

+ t

PACKET

Figure 19: Retire Held Off by Reads to Same Device, Write Buffer Retired to New Row

CTM/CFM

DQA8..0

DQB8..0

COL4

..COL0

ROW2

..ROW0

MSK (a1)

retire (a1)

RD b1

WR a1

PRER a2

RCD

ACT c0

RAS

ACT a0

CWD

RTR

Transaction a: WR

a0 = {Da,Ba,Ra}

a1 = {Da,Ba,Ca1}

a2 = {Da,Ba}

RD b2

RD b3

RD b4

RD b5

RD b6

Transaction b: RD

b1 = {Da,Bb,Cb1}

b2 = {Da,Bb,Cb2}

b3= {Da,Bb,Cb3}

b4 = {Da,Bb,Cb4}

b5 = {Da,Bb,Cb5}

b6 = {Da,Bb,Cb6}

Q (b1)

CAC

Q (b2)

Q (b3)

Q (b4)

Q (b5)

Transaction c: WR

c0 = {Da,Ba,Rc}

D (a1)

The retire operation puts the

write data in the new row

WARNING

This sequence is hazardous

and must be used with caution

Page 24

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

Interleaved Write - Example

Figure 20 shows an example of an interleaved write transac-
tion. Transactions similar to the one presented in Figure 16
are directed to non-adjacent banks of a single RDRAM. This
allows a new transaction to be issued once every t

interval

rather than once every t

interval (four times more often).

The DQ data pin efficiency is 100% with this sequence.

With two dualocts of data written per transaction, the COL,
DQA, and DQB pins are fully utilized. Banks are precharged

using the WRA autoprecharge option rather than the PRER
command in an ROWR packet on the ROW pins.

In this example, the first transaction is directed to device Da
and bank Ba. The next three transactions are directed to the
same device Da, but need to use different, non-adjacent
banks Bb, Bc, Bd so there is no bank conflict. The fifth
transaction could be redirected back to bank Ba without
interference, since the first transaction would have
completed by then (t

has elapsed). Each transaction may

use any value of row address (Ra, Rb, ..) and column address
(Ca1, Ca2, Cb1, Cb2, ...).

Interleaved Read - Example

Figure 21 shows an example of interleaved read transac-
tions. Transactions similar to the one presented in Figure 15
are directed to non-adjacent banks of a single RDRAM. The
address sequence is identical to the one used in the previous
write example. The DQ data pins efficiency is also 100%.
The only difference with the write example (aside from the
use of the RD command rather than the WR command) is
the use of the PREX command in a COLX packet to
precharge the banks rather than the RDA command. This is
done because the PREX is available for a readtransaction but
is not available for a masked write transaction.

Interleaved RRWW - Example

Figure 22 shows a steady-state sequence of 2-dualoct
RD/RD/WR/WR.. transactions directed to non-adjacent
banks of a single RDRAM. This is similar to the interleaved
write and read examples in Figure 20 and Figure 21 except

that bubble cycles need to be inserted by the controller at
read/write boundaries. The DQ data pin efficiency for the
example in Figure 22 is 32/42 or 76%. If there were more
RDRAMs on the Channel, the DQ pin efficiency would
approach 32/34 or 94% for the two-dualoct RRWW
sequence (this case is not shown).

In Figure 22, the first bubble type t

CBUB1

is inserted by the

controller between a RD and WR command on the COL
pins. This bubble accounts for the round-trip propagation
delay that is seen by read data, and is explained in detail in
Figure 4. This bubble appears on the DQA and DQB pins as
t

DBUB1

between a write data dualoct D and read data dualoct

Q. This bubble also appears on the ROW pins as t

RBUB1

Figure 20: Interleaved Write Transaction with Two Dualoct Data Length

CTM/CFM

DQA8..0

DQB8..0

COL4

..COL0

ROW2

..ROW0

ACT a0

MSK (b2)

WRA c2

MSK (b1)

WR c1

WR b1

MSK (a1)

WRA b2

MSK (a2)

D (b2)

D (b1)

ACT b0

ACT c0

ACT d0

ACT e0

D (a2)

D (a1)

WR d1

MSK (c1)

D(c1)

ACT f0

WR d2

MSK (c2)

WR e1

MSK (d1)

D (c2)

D (d1)

WR e2

MSK (d2)

D (z2)

D (z1)

D (x2)

D (y1)

D (y2)

MSK (z2)

WRA a2

MSK (z1)

WR a1

WR z1

MSK (y1)

WRA z2

MSK (y2)

Q (d1)

RCD

CWD

Transaction e can use the

same bank as transaction a

f3 = {Da,Ba+2}

Transaction f: WR

f0 = {Da,Ba+2,Rf}

f1 = {Da,Ba+2,Cf1}

f2= {Da,Ba+2,Cf2}

e3 = {Da,Ba}

Transaction e: WR

e0 = {Da,Ba,Re}

e1 = {Da,Ba,Ce1}

e2= {Da,Ba,Ce2}

d3 = {Da,Ba+6}

Transaction d: WR

d0 = {Da,Ba+6,Rd}

d1 = {Da,Ba+6,Cd1}

d2= {Da,Ba+6,Cd2}

c3 = {Da,Ba+4}

Transaction c: WR

c0 = {Da,Ba+4,Rc}

c1 = {Da,Ba+4,Cc1}

c2= {Da,Ba+4,Cc2}

b3 = {Da,Ba+2}

Transaction b: WR

b0 = {Da,Ba+2,Rb}

b1 = {Da,Ba+2,Cb1}

b2= {Da,Ba+2,Cb2}

a3 = {Da,Ba}

Transaction a: WR

a0 = {Da,Ba,Ra}

a1 = {Da,Ba,Ca1}

a2= {Da,Ba,Ca2}

z3 = {Da,Ba+6}

Transaction z: WR

z0 = {Da,Ba+6,Rz}

z1 = {Da,Ba+6,Cz1}

z2= {Da,Ba+6,Cz2}

y3 = {Da,Ba+4}

Transaction y: WR

y0 = {Da,Ba+4,Ry}

y1 = {Da,Ba+4,Cy1}

y2= {Da,Ba+4,Cy2}

Page 25

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

The second bubble type t

CBUB2

is inserted (as a NOCOP

command) by the controller between a WR and RD
command on the COL pins when there is a WR-WR-RD
sequence to the same device. This bubble enables write data
to be retired from the write buffer without being lost, and is

explained in detail in Figure 18. There would be no bubble if
address c0 and address d0 were directed to different devices.
This bubble appears on the DQA and DQB pins as t

DBUB2

between a write data dualoct D and read data dualoct Q. This
bubble also appears on the ROW pins as t

RBUB2

Control Register Transactions

The RDRAM has two CMOS input pins SCK and CMD and
two CMOS input/output pins SIO0 and SIO1. These provide

serial access to a set of control registers in the RDRAM.
These control registers provide configuration information to
the controller during the initialization process. They also

Figure 21: Interleaved Read Transaction with Two Dualoct Data Length

CTM/CFM

DQA8..0

DQB8..0

COL4

..COL0

ROW2

..ROW0

ACT a0

PREX b3

RD c2

RD c1

RD b1

RD b2

PREX a3

ACT b0

ACT c0

ACT d0

ACT e0

RD a1

RD a2

PREX z3

RD d1

ACT f0

RDd2

PREX c3

RD e1

RD e2

PREX d3

RD z1

RD z2

PREX y3

Q (b2)

Q (b1)

Q (a2)

Q (a1)

Q (c1)

Q (c2)

Q (d1)

Q (z2)

Q (z1)

Q (x2)

Q (y1)

Q (y2)

RCD

CAC

Transaction e can use the

same bank as transaction a

f3 = {Da,Ba+2}

Transaction f: RD

f0 = {Da,Ba+2,Rf}

f1 = {Da,Ba+2,Cf1}

f2= {Da,Ba+2,Cf2}

e3 = {Da,Ba}

Transaction e: RD

e0 = {Da,Ba,Re}

e1 = {Da,Ba,Ce1}

e2= {Da,Ba,Ce2}

d3 = {Da,Ba+6}

Transaction d: RD

d0 = {Da,Ba+6,Rd}

d1 = {Da,Ba+6,Cd1}

d2= {Da,Ba+6,Cd2}

c3 = {Da,Ba+4}

Transaction c: RD

c0 = {Da,Ba+4,Rc}

c1 = {Da,Ba+4,Cc1}

c2= {Da,Ba+4,Cc2}

b3 = {Da,Ba+2}

Transaction b: RD

b0 = {Da,Ba+2,Rb}

b1 = {Da,Ba+2,Cb1}

b2= {Da,Ba+2,Cb2}

a3 = {Da,Ba}

Transaction a: RD

a0 = {Da,Ba,Ra}

a1 = {Da,Ba,Ca1}

a2= {Da,Ba,Ca2}

z3 = {Da,Ba+6}

Transaction z: RD

z0 = {Da,Ba+6,Rz}

z1 = {Da,Ba+6,Cz1}

z2= {Da,Ba+6,Cz2}

y3 = {Da,Ba+4}

Transaction y: RD

y0 = {Da,Ba+4,Ry}

y1 = {Da,Ba+4,Cy1}

y2= {Da,Ba+4,Cy2}

Figure 22: Interleaved RRWW Sequence with Two Dualoct Data Length

CTM/CFM

DQA8..0

DQB8..0

COL4

..COL0

ROW2

..ROW0

ACT a0

MSK (b2)

WRA c2

MSK (b1)

WR c1

WR b1

MSK (y2)

WRA b2
PREX a3

D (b2)

D (b1)

ACT b0

ACT c0

ACT d0

ACT e0

RD a1

RD a2

PREX z3

Q (a2)

Q (a1)

MSK (c1)

D (c1)

NOCOP

MSK (c2)

RDd0

D (c2)

RBUB1

RDf1

Q (z2)

Q (z1)

D (y2)

RD z1

RD z2

CBUB1

DBUB1

DBUB2

CBUB2

RBUB2

CBUB2

NOCOP

Transaction e can use the

same bank as transaction a

f3 = {Da,Ba+2}

Transaction f: WR

f0 = {Da,Ba+2,Rf}

f1 = {Da,Ba+2,Cf1}

f2= {Da,Ba+2,Cf2}

e3 = {Da,Ba}

Transaction e: RD

e0 = {Da,Ba,Re}

e1 = {Da,Ba,Ce1}

e2= {Da,Ba,Ce2}

d3 = {Da,Ba+6}

Transaction d: RD

d0 = {Da,Ba+6,Rd}

d1 = {Da,Ba+6,Cd1}

d2= {Da,Ba+6,Cd2}

c3 = {Da,Ba+4}

Transaction c: WR

c0 = {Da,Ba+4,Rc}

c1 = {Da,Ba+4,Cc1}

c2= {Da,Ba+4,Cc2}

b3 = {Da,Ba+2}

Transaction b: WR

b0 = {Da,Ba+2,Rb}

b1 = {Da,Ba+2,Cb1}

b2= {Da,Ba+2,Cb2}

a3 = {Da,Ba}

Transaction a: RD

a0 = {Da,Ba,Ra}

a1 = {Da,Ba,Ca1}

a2= {Da,Ba,Ca2}

z3 = {Da,Ba+6}

Transaction z: RD

z0 = {Da,Ba+6,Rz}

z1 = {Da,Ba+6,Cz1}

z2= {Da,Ba+6,Cz2}

y3 = {Da,Ba+4}

Transaction y: WR

y0 = {Da,Ba+4,Ry}

y1 = {Da,Ba+4,Cy1}

y2= {Da,Ba+4,Cy2}

Page 26

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

allow an application to select the appropriate operating mode
of the RDRAM.

SCK (serial clock) and CMD (command) are driven by the
controller to all RDRAMs in parallel. SIO0 and SIO1 are
connected (in a daisy chain fashion) from one RDRAM to

the next. In normal operation, the data on SIO0 is repeated
on SIO1, which connects to SIO0 of the next RDRAM (the
data is repeated from SIO1 to SIO0 for a read data packet).
The controller connects to SIO0 of the first RDRAM.

Write and read transactions are each composed of four
packets, as shown in Figure 23 and Figure 24. Each packet
consists of 16 bits, as summarized in Table 14 and Table 15.
The packet bits are sampled on the falling edge of SCK. A
transaction begins with a SRQ (Serial Request) packet. This
packet is framed with a 11110000 pattern on the CMD input
(note that the CMD bits are sampled on both the falling edge
and the rising edge of SCK). The SRQ packet contains the
SOP3..SOP0 (Serial Opcode) field, which selects the trans-
action type. The SDEV5..SDEV0 (Serial Device address)
selects one of the 32 RDRAMs. If SBC (Serial Broadcast) is
set, then all RDRAMs are selected. The SA (Serial Address)

packet contains a 12 bit address for selecting a control
register.

A write transaction has a SD (Serial Data) packet next. This
contains 16 bits of data that is written into the selected
control register. A SINT (Serial Interval) packet is last,
providing some delay for any side-effects to take place. A
read transaction has a SINT packet, then a SD packet. This
provides delay for the selected RDRAM to access the
control register. The SD read data packet travels in the oppo-
site direction (towards the controller) from the other packet
types. The SCK cycle time will accomodate the total delay.

Figure 23: Serial Write (SWR) Transaction to Control Register

SRQ - SWR command

1111

00000000...00000000

SRQ - SWR command

0000

SINT

00000000...00000000

SCK

CMD

SIO0

SIO1

Each packet is repeated

from SIO0 to SIO1

1111

next transaction

Figure 24: Serial Read (SRD) Transaction Control Register

SRQ - SRD command

1111

00000000...00000000

SRQ - SRD command

0000

SINT

00000000...00000000

SCK

CMD

SIO0

SIO1

First 3 packets are repeated

from SIO0 to SIO1

non-addressed RDRAMs pass

0/SD15..SD0/0 from SIO1 to SIO0

1111

next transaction

controller drives

0 on SIO0

addressed RDRAM drives

0/SD15..SD0/0 on SIO0

Page 27

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

Control Register Packets

Table 14 summarizes the formats of the four packet types for
control register transactions. Table 15 summarizes the fields
that are used within the packets.

Figure 25 shows the transaction format for the SETR,
CLRR, and SETF commands. These transactions consist of a
single SRQ packet, rather than four packets like the SWR
and SRD commands. The same framing sequence on the
CMD input is used, however. These commands are used
during initialization prior to any control register read or
write transactions.

Figure 25: SETR, CLRR,SETF Transaction

SCK

CMD

SIO0

SRQ packet - SETR/CLRR/SETF

1111

00000000...00000000

SRQ packet - SETR/CLRR/SETF

0000

SIO1

The packet is repeated

from SIO0 to SIO1

Table 14: Control Register Packet Formats

SCK
Cycle

SIO0 or
SIO1
for SRQ

SIO0 or
SIO1
for SA

SIO0 or
SIO1
for SINT

SIO0 or
SIO1
for SD

SCK
Cycle

SIO0 or
SIO1
for SRQ

SIO0 or
SIO1
for SA

SIO0 or
SIO1
for SINT

SIO0 or
SIO1
for SD

rsrv

SD15

SOP1

SA7

SD7

rsrv

SD14

SOP0

SA6

SD6

rsrv

SD13

SBC

SA5

SD5

rsrv

SD12

SDEV4

SA4

SD4

rsrv

SA11

SD11

SDEV3

SA3

SD3

SDEV5

SA10

SD10

SDEV2

SA2

SD2

SOP3

SA9

SD9

SDEV1

SA1

SD1

SOP2

SA8

SD8

SDEV0

SA0

SD0

Table 15: Field Description for Control Register Packets

Field

Description

rsrv

Reserved. Should be driven as

by controller.

SOP3..SOP0

0000 - SRD. Serial read of control register {SA11..SA0} of RDRAM {SDEV5..SDEV0}.

0001 - SWR. Serial write of control register {SA11..SA0} of RDRAM {SDEV5..SDEV0}.

0010 - SETR. Set Reset bit, all control registers assume their reset values.

16 t

SCYCLE

delay until CLRR command.

0100 - SETF. Set fast (normal) clock mode. 4 t

SCYCLE

delay until next command.

1011 - CLRR. Clear Reset bit, all control registers retain their reset values.

4 t

SCYCLE

delay until next command.

1111 - NOP. No serial operation.

0011, 0101-1010, 1100-1110 - RSRV. Reserved encodings.

SDEV5..SDEV0

Serial device. Compared to SDEVID5..SDEVID0 field of INIT control register field to select the RDRAM to which the transac-
tion is directed.

SBC

Serial broadcast. When set, RDRAMs ignore {SDEV5..SDEV0} for RDRAM selection.

SA11..SA0

Serial address. Selects which control register of the selected RDRAM is read or written.

SD15..SD0

Serial data. The 16 bits of data written to or read from the selected control register of the selected RDRAM.

a. The SETR and CLRR commands must always be applied in two successive transactions to RDRAMs; i.e. they may not be used in isolation. This is called

SETR/CLRR Reset

Page 28

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

Initialization

Initialization refers to the process that a controller must go
through after power is applied to the system or the system is
reset. The controller prepares the RDRAM sub-system for
normal Channel operation by (primarily) using a sequence of
control register transactions on the serial CMOS pins. The
following steps outline the sequence seen by the various
memory subsystem components (including the RDRAM
components) during initialization. This sequence is available
in the form of reference code.

1.0 Start Clocks - This step calculates the proper clock
frequencies for PClk (controller logic), SynClk (RAC
block), RefClk (DRCG component), CTM (RDRAM
component), and SCK (SIO block).

2.0 RAC Initialization - This step causes the INIT block to
generate a sequence of pulses which resets the RAC,
performs RAC maintainance operations, and measures
timing intervals in order to ensure clock stability.

3.0 RDRAM Initialization - This stage performs most of
the steps needed to initialize the RDRAMs. The rest are
performed in stages 5.0, 6.0, and 7.0. All of the steps in 3.0
are carried out through the SIO block interface.

3.1/3.2 SIO Reset - After a delay of t

PAUSE

from step

1.0, this reset operation is performed berore any SIO
control register read or write transactions. It clears six
registers (TEST34, CCA, CCB, SKIP, TEST78, and
TEST79) and places the INIT register into a special
state (all bits cleared except SKP and SDEVID fields
are set to ones).

3.3 Write TEST77 Register - The TEST77 register
must be explicitly written with zeros before any other
registers are read or written.

3.4 Write TCYCLE Register - The TCYCLE register
is written with the cycle time tCYCLE of the CTM
clock (for Channel and RDRAMs) in units of 64ps. The
tCYCLE value is determined in stage 1.0.

3.5 Write SDEVID Register - The SDEVID (serial
device identification) register of each RDRAM is
written with a unique address value so that directed SIO
read and write transactions can be performed. This
address value increases from 0 to 31 according to the
distance an RDRAM is from the ASIC component on
the SIO bus (the closest RDRAM is address 0).

3.6 Write DEVID Register - The DEVID (device iden-
tification) register of each RDRAM is written with a
unique address value so that directed memory read and
write transactions can be performed. This address value
increases from 0 to 31. The DEVID value is not neces-
sarily the same as the SDEVID value. RDRAMs are
sorted into regions of the same core configuration
(number of bank, row, and column address bits and core
type).

3.7 Write PDNX,PDNXA Registers - The PDNX and
PDNXA registers are written with values that are used
to measure the timing intervals connected with an exit
from the PDN (powerdown) power state.

3.8 Write NAPX Register - The NAPX register is
written with values that are used to measure the timing
intervals connected with an exit from the NAP power
state.

3.9 Write TPARM Register - The TPARM register is
written with values which determine the time interval
between a COL packet with a memory read command
and the Q packet with the read data on the Channel. The
values written set each RDRAM to the minimum value
permitted for the system. This will be adjusted later in
stage 6.0.

3.10 Write TCDLY1 Register - The TCDLY1 register
is written with values which determine the time interval
between a COL packet with a memory read command
and the Q packet with the read data on the Channel. The
values written set each RDRAM to the minimum value
permitted for the system. This will be adjusted later in
stage 6.0.

3.11 Write TFRM Register - The TFRM register is
written with a value that is related to the t

RCD

parameter

for the system. The t

RCD

parameter is the time interval

Figure 26: SIO Reset Sequence

SCK

CMD

SIO0

0000000000000000

00001100

SIO1

The packet is repeated

from SIO0 to SIO1

00000000...00000000

Page 29

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

between a ROW packet with an activate command and
the COL packet with a read or write command.

3.12 SETR/CLRR - Each RDRAM is given a SETR
command and a CLRR command through the SIO
block. This sequence performs a second reset operation
on the RDRAMs.

3.13 Write CCA and CCB Registers - These registers
are written with a value halfway between their
minimum and maximum values. This shortens the time
needed for the RDRAMs to reach their steady-state
current control values in stage 5.0.

3.14 Powerdown Exit - The RDRAMs are in the PDN
power state at this point. A broadcast PDNExit
command is performed by the SIO block to place the
RDRAMs in the RLX (relax) power state in which they
are ready to receive ROW packets.

3.15 SETF - Each RDRAM is given a SETF command
through the SIO block. One of the operations performed
by this step is to generate a value for the AS (autoskip)
bit in the SKIP register and fix the RDRAM to a partic-
ular read domain.

4.0 Controller Configuration- This stage initializes the
controller block. Each step of this stage will set a field of the
ConfigRMC[63:0] bus to the appropriate value. Other
controller implementations will have similar initialization
requirements, and this stage may be used as a guide.

4.1 Initial Read Data Offset- The ConfigRMC bus is
written with a value which determines the time interval
between a COL packet with a memory read command
and the Q packet with the read data on the Channel. The
value written sets RMC.d1 to the minimum value
permitted for the system. This will be adjusted later in
stage 6.0.

4.2 Configure Row/Column Timing - This step deter-
mines the values of the t

RAS,MIN

, t

RP,MIN

, t

RC,MIN

RCD,MIN

, t

RR,MIN

, and t

PP,MIN

RDRAM timing param-

eters that are present in the system. The ConfigRMC
busis written with values that will be compatible with
all RDRAM devices that are present.

4.3 Set Refresh Interval - This step determines the
values of the t

REF,MAX

RDRAM timing parameter that

are present in the system. The ConfigRMC bus is
written with a value that will be compatible with all
RDRAM devices that are present.

4.4 Set Current Control Interval - This step deter-
mines the values of the t

CCTRL,MAX

RDRAM timing

parameter that are present in the system. The Confi-

gRMC bus is written with a value that will be compat-
ible with all RDRAM devices that are present.

4.5 Set Slew Rate Control Interval - This step deter-
mines the values of the t

TEMP,MAX

RDRAM timing

parameter that are present in the system. The Confi-
gRMC bus is written with a value that will be compat-
ible with all RDRAM devices that are present.

4.6 Set Bank/Row/Col Address Bits - This step deter-
mines the number of RDRAM bank, row, and column
address bits that are present in the system. It also deter-
mines the RDRAM core types (independent, doubled,
or split) that are present. The ConfigRMC bus is written
with a value that will be compatible with all RDRAM
devices that are present.

5.0 RDRAM Current Control - This step causes the INIT
block to generate a sequence of pulses which performs
RDRAM maintainance operations.

6.0 RDRAM Core, Read Domain Initialization- This
stage completes the RDRAM initialization

6.1 RDRAM Core Initialization - A sequence of 192
memory refresh transactions is performed in order to
place the cores of all RDRAMs into the proper oper-
ating state.

6.2 RDRAM Read Domain Initialization - A memory
write and memory read transaction is performed to each
RDRAM to determine which read domain each
RDRAM occupies. The programmed delay of each
RDRAM is then adjusted so the total RDRAM read
delay (propagation delay plus programmed delay) is
constant. The TPARM and TCDLY1 registers of each
RDRAM are rewritten with the appropriate read delay
values. The ConfigRMC bus is also rewritten with an
updated value.

7.0 Other RDRAM Register Fields - This stage rewrites
the INIT register with the final values of the LSR, NSR, and
PSR fields.

In essence, the controller must read all the read-only config-
uration registers of all RDRAMs (or it must read the SPD
device present on each RIMM), it must process this informa-
tion, and then it must write all the read-write registers to
place the RDRAMs into the proper operating mode.

Initialization Note [1]: During the initialization process, it is
necessary for the controller to perform 128 current control
operations (3xCAL, 1xCAL/SAM) and one temperature
calibrate operation (TCEN/TCAL) after reset or after power-
down (PDN) exit.

Page 30

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

Initialization Note [2]: Does not apply to this RDRAM type;
this note had been generated for earlier 72M devices, but
does not apply to this device.

Initialization Note [3]: After the step of equalizing the total
read delay of each RDRAM has been completed (i.e. after
the TCDLY0 and TCDLY1 fields have been written for the
final time), a single final memory read transaction should be
made to each RDRAM in order to ensure that the output
pipeline stages have been cleared.

Initialization Note [4]: The SETF command (in the serial
SRQ packet) should only be issued once during the Initial-
ization process, as should the SETR and CLRR commands.

Initialization Note [5]: The CLRR command (in the serial
SRQ packet) leaves some of the contents of the memory
core in an indeterminate state.

Control Register Summary

Table 16 summarizes the RDRAM control registers. Detail
is provided for each control register in Figure 27 through
Figure 43. Read-only bits which are shaded gray are unused
and return zero. Read-write bits which are shaded gray are
reserved and should always be written with zero. The RIMM
SPD Application Note describes additional read-only
configuration registers which are present on Direct RIMMs.

The state of the register fields are potentially affected by the
IO Reset operation or the SETR/CLRR operation. This is
indicated in the text accompanying each register diagram.

Table 16: Control Register Summary

SA11..SA0

Register

Field

read-write/ read-only

Description

021

INIT

SDEVID

read-write, 6 bits

Serial device ID. Device address for control register read/write.

PSX

read-write, 1 bit

Power select exit. PDN/NAP exit with device addr on DQA5..0.

SRP

read-write, 1 bit

SIO repeater. Used to initialize RDRAM.

NSR

read-write, 1 bit

NAP self-refresh. Enables self-refresh in NAP mode.

PSR

read-write, 1 bit

PDN self-refresh. Enables self-refresh in PDN mode.

LSR

read-write, 1 bit

Low power self-refresh. Enables low power self-refresh.

TEN

read-write, 1 bit

Temperature sensing enable.

TSQ

read-write, 1 bit

Temperature sensing output.

DIS

read-write, 1 bit

RDRAM disable.

IDM

read-write, 1 bit

Interleaved Device Mode enable

022

TEST34

read-write, 16 bits

Test register. Do not read or write after SIO reset.

023

CNFGA

REFBIT

read-only, 3 bit

Refresh bank bits. Used for multi-bank refresh.

DBL

read-only, 1 bit

Double. Specifies doubled-bank architecture

MVER

read-only, 6 bit

Manufacturer version. Manufacturer identification number.

PVER

read-only, 6 bit

Protocol version. Specifies version of Direct protocol supported.

024

CNFGB

BYT

read-only, 1 bit

Byte. Specifies an 8-bit or 9-bit byte size.

DEVTYP

read-only, 3 bit

Device type. Device can be RDRAM or some other device category.

SPT

read-only, 1 bit

Split-core. Each core half is an individual dependent core.

CORG

read-only, 6 bit

Core organization. Bank, row, column address field sizes.

SVER

read-only, 6 bit

Stepping version. Mask version number.

040

DEVID

read-write, 5 bits

Device ID. Device address for memory read/write.

041

REFB

read-write, 4 bits

Refresh bank. Next bank to be refreshed by self-refresh.

042

REFR

read-write, 9 bits

Refresh row. Next row to be refreshed by REFA, self-refresh.

043

CCA

read-write, 7 bits

Current control A. Controls I

output current for DQA.

ASYMA

read-write, 2 bits

Asymmetry control. Controls asymmetry of V

swing for DQA.

Page 31

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

044

CCB

read-write, 7 bits

Current control B. Controls I

output current for DQB.

ASYMB

read-write, 2 bits

Asymmetry control. Controls asymmetry of V

swing for DQB.

045

NAPX

NAPXA

read-write, 5 bits

NAP exit. Specifies length of NAP exit phase A.

NAPX

read-write, 5 bits

NAP exit. Specifies length of NAP exit phase A + phase B.

DQS

read-write, 1 bits

DQ select. Selects CMD framing for NAP/PDN exit.

046

PDNXA

read-write, 13 bits

PDN exit. Specifies length of PDN exit phase A.

047

PDNX

read-write, 13 bits

PDN exit. Specifies length of PDN exit phase A + phase B.

048

TPARM

TCAS

read-write, 2 bits

CAS-C

core parameter. Determines t

OFFP

datasheet parameter.

TCLS

read-write, 2 bits

CLS-C

core parameter. Determines t

CAC

and t

OFFP

parameters.

TCDLY0

read-write, 3 bits

CDLY0-C

core parameter. Programmable delay for read data.

049

TFRM

read-write, 4 bits

FRM-C

core parameter. Determines ROW-COL packet framing interval.

04a

TCDLY1

read-write, 3 bits

CDLY1-C

core parameter. Programmable delay for read data.

04c

TCYCLE

read-write, 14 bits

CYCLE

datasheet parameter. Specifies cycle time in 64ps units.

04b

SKIP

read-only, 1 bit

Autoskip value established by the SETF command.

MSE

read-write, 1 bit

Manual skip enable. Allows the MS value to override the AS value.

read-write, 1 bit

Manual skip value.

04d

16-

TEST77

read-write, 16 bits

Test register. Write with zero after SIO reset.

04e

16-

TEST78

read-write, 16 bits

Test register. Do not read or write after SIO reset.

04f

16-

TEST79

read-write, 16 bits

Test register. Do not read or write after SIO reset.

080

- 0ff

reserved

vendor-specific

Vendor-specific test registers. Do not read or write after SIO reset.

Table 16: Control Register Summary

SA11..SA0

Register

Field

read-write/ read-only

Description

Page 32

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

. .

Figure 27: INIT Register

Figure 28: CNFGA Register

15 14 13 12 11 10

Control Register: INIT

Read/write register.
Reset values are undefined except as affected by SIO Reset as noted
below. SETR/CLRR Reset does not affect this register.

SDEVID5..0 - Serial Device Identification. Compared to SDEV5..0
serial address field of serial request packet for register read/write transac-
tions. This determines which RDRAM is selected for the register read or
write operation. SDEVID resets to 3f

SDEVID4..SDEVID0

SRP PSX

NSR

PSR

LSR

PSX - Power Exit Select. PDN and NAP are exited with (=0) or without (=1) a device address on the
DQA5..0 pins. PDEV5 (on DQA5) selectes broadcast (1) or directed (0) exit. For a directed exit,
PDEV4..0 (on DQA4..0) is compared to DEVID4..0 to select a device.

SRP - SIO Repeater. Controls value on SIO1; SIO1=SIO0 if SRP=1, SIO1=1 if SRP=0. SRP resets
to 1.

NAP Self-Refresh. NSR=1 enables self-refresh in NAP mode. NSR can't be set while in NAP
mode. NSR resets to 0.

PDN Self-Refresh. PSR=1 enables self-refresh in PDN mode. PSR can't be set while in PDN mode.
PSR resets to 0.

Low Power Self-Refresh. LSR=1 enables longer self-refresh interval. The self-refresh supply
current is reduced. LSR resets to 0.

Temperature Sensing Enable. TEN=1 enables temperature sensing circuitry, permitting the TSQ bit
to be read to determine if a thermal trip point has been exceeded. TEN resets to 0.

Temperature Sensing Output. TSQ=1 when a temperature trip point has been exceeded, TSQ=0
when it has not. TSQ is available during a current control operation (see Figure 51).

RDRAM Disable. DIS=1 causes RDRAM to ignore NAP/PDN exit sequence, DIS=0 permits
normal operation. This mechanism disables an RDRAM. DIS resets to 0.

Interleaved Device Mode. IDM=1 causes 8 RDRAMs interleave read/write data, IDM=0 permits
normal operation . IDM resets to 0.

Address: 021

TEN

TSQ

DIS

SDE
VID

IDM

15 14 13 12 11 10

Control Register: CNFGA

Address: 023

Read-only register.

REFBIT2..0 - Refresh Bank Bits. Specifies the number of
bank address bits used by REFA and REFP commands.
Permits multi-bank refresh in future RDRAMs.

DBL - Doubled-Bank. DBL=1 means the device uses a
doubled-bank architecture with adjacent-bank dependency.
DBL=0 means no dependency.

MVER5..0 - Manufacturer Version. Specifies the manufac-
turer identification number.

PVER5..0 - Protocol Version. Specifies the Direct Protocol
version used by this device:
0 - Reserved
1 - Version 1 protocol.
2 - Version 1 plus Interleaved Device Mode .
3 to 63 - Reserved.

REFBIT2..0

= 101

PVER5..0

= 000001

DBL

MVER5..0

= 010000

Note: In RDRAMs with protocol version 1 PVER[5:0] = 000001, the
range of the PDNX field (PDNX[2:0] in the PDNX register) may not
be large enough to specify the location of the restricted interval in
Figure 47. In this case, the effective t

parameter must increase and

no row or column packets may overlap the restricted interval. See
Figure 47 and Table 19.

Page 33

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

. .

Figure 29: CNFGB Register

15 14 13 12 11 10

Control Register: CNFGB

Address: 024

Read-only register.

BYT - Byte width. B=1 means the device reads and
writes 9-bit memory bytes. B=0 means 8 bits.

DEVTYP2..0 - Device type. DEVTYP = 000 means
that this device is an RDRAM.

DEVTYP2..0

= 000

BYT

SVER5..0

= 000000

CORG4..0

= 01000

SPT

SPT - Split-core. SPT=1 means the core is split, SPT=0 means it is not.

CORG4..0 - Core organization. This field specifies the number of bank (5
bits), row (9 bits), and column (7 bits) address bits.

SVER5..0 - Stepping version. Specifies the mask version number of this
device.

Figure 30: TEST Register

15 14 13 12 11 10

Read/write register.
Reset value of TEST34 is zero (from SIO Reset)
This register are used for testing purposes. It must not
be read or written after SIO Reset.

Control Register: TEST34

Address: 022

Figure 31: DEVID Register

15 14 13 12 11 10

Read/write register.
Reset value is undefined.
Device Identification register.
DEVID4..DEVID0 is compared to DR4..DR0,
DC4..DC0, and DX4..DX0 fields for all memory read
or write transactions. This determines which RDRAM
is selected for the memory read or write transaction.

Control Register: DEVID

Address: 040

DEVID4..DEVID0

Page 34

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

Figure 32: REFB Register

Figure 33: CCA Register

15 14 13 12 11 10

Read/write register.
Reset value is zero (from SETR/CLRR).
Refresh Bank register.
REFB4..REFB0 is the bank that will be refreshed next
during self-refresh. REFB4..0 is incremented after each
self-refresh activate and precharge operation pair.

Control Register: REFB

Address: 041

REFB4..REFB0

15 14 13 12 11 10

Read/write register.
Reset value is zero (SETR/CLRR or SIO Reset).
CCA6..CCA0 - Current Control A. Controls the I

output current for the DQA8..DQA0 pins.

ASYMB0 control the asymmetry of the V

voltage swing about the V

REF

reference voltage for the

DQA8..0 pins.

Control Register: CCA

Address: 043

CCA6..CCA0

ASYMA

Figure 34: REFR Register

Figure 35: CCB Register

15 14 13 12 11 10

Read/write register.
Reset value is zero (from SETR/CLRR).
Refresh Row register.
REFR8..REFR0 is the row that will be refreshed next
by the REFA command or by self-refresh. REFR8..0 is
incremented when BR4..0=11111 for the REFA
command. REFR8..0 is incremented when
REFB4..0=11111 for self-refresh.

Control Register: REFR

Address: 042

REFR8..REFR0

15 14 13 12 11 10

Read/write register.
Reset value is zero (SETR/CLRR or SIO Reset).
CCB6..CCB0 - Current Control B. Controls the I

output current for the DQB8..DQB0 pins.

ASYMB0 control the asymmetry of the V

voltage swing about the V

REF

reference voltage for the

DQB8..0 pins.

Control Register: CCB

Address: 044

CCB6..CCB0

..0

ASYMB

Page 35

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

Figure 36: NAPX Register

15 14 13 12 11 10

Control Register: NAPX

Address: 045

Read/write register.
Reset value is undefined
Note - t

SCYCLE

is t

CYCLE1

(SCK cycle time).

NAPXA4..0 - Nap Exit Phase A. This field specifies
the number of SCK cycles during the first phase for
exiting NAP mode. It must satisfy:

NAPXA·t

SCYCLE

NAPXA,MAX

Do not set this field to zero.

DQS

NAPXA4..0

NAPX4..0

NAPX4..0 - Nap Exit Phase A plus B. This field specifies the number of SCK
cycles during the first plus second phases for exiting NAP mode. It must satisfy:

NAPX·t

SCYCLE

NAPXA·t

SCYCLE

NAPXB,MAX

Do not set this field to zero.

DQS - DQ Select. This field specifies the number of SCK cycles (0 => 0.5
cycles, 1 => 1.5 cycles) between the CMD pin framing sequence and the device
selection on DQ5..0. See Figure 48 - This field must be written with a

for

this RDRAM.

Figure 37: PDNXA Register

15 14 13 12 11 10

Read/write register.
Reset value is undefined
PDNXA4..0 - PDN Exit Phase A. This field specifies
the number of (64·SCK cycle) units during the first
phase for exiting PDN mode. It must satisfy:

PDNXA·64·t

SCYCLE

PDNXA,MAX

Do not set this field to zero.
Note - only PDNXA5..0 are implemented.
Note - t

SCYCLE

is t

CYCLE1

(SCK cycle time).

Control Register: PDNXA

Address: 046

PDNXA12..0

Figure 38: PDNX Register

15 14 13 12 11 10

Read/write register.
Reset value is undefined
PDNX4..0 - PDN Exit Phase A plus B. This field spec-
ifies the number of (256·SCK cycle) units during the
first plus second phases for exiting PDN mode. It
should satisfy:

PDNX·256·t

SCYCLE

PDNXA·64·t

SCYCLE

PDNXB,MAX

If this equation can't be satisfied, then the maximum
PDNX value should be written, and the t

timing

window will be modified (see Figure 49).
Do not set this field to zero.
Note - only PDNX2..0 are implemented.
Note - t

SCYCLE

is t

CYCLE1

(SCK cycle time).

Control Register: PDNX

Address: 047

PDNX12..0

Page 36

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

Figure 39: TPARM Register

15 14 13 12 11 10

Read/write register.
Reset value is undefined.
TCAS1..0 - Specifies the t

CAS-C

core parameter in

CYCLE

units. This should be

(2·t

CYCLE

TCLS1..0 - Specifies the t

CLS-C

core parameter in

CYCLE

units. Should be

(2·t

CYCLE

TCDLY0 - Specifies the t

CDLY0-C

core parameter in

CYCLE

units. This adds a programmable delay to Q

(read data) packets, permitting round trip read delay to
all devices to be equalized. This field may be written
with the values

011

(3·t

CYCLE

) through

101

(5·t

CYCLE

Control Register: TPARM

Address: 048

TCAS

TCLS

The equations relating the core parameters to the
datasheet parameters follow:

CAS-C

= 2·t

CYCLE

CLS-C

= 2·t

CYCLE

CPS-C

= 1·t

CYCLE

Not programmable

OFFP

= t

CPS-C

+ t

CAS-C

+ t

CLS-C

- 1·t

CYCLE

= 4·t

CYCLE

RCD

= t

RCD-C

+ 1·t

CYCLE

- t

CLS-C

= t

RCD-C

- 1·t

CYCLE

CAC

= 3·t

CYCLE

+ t

CLS-C

+ t

CDLY0-C

+ t

CDLY1-C

(see table below for programming ranges)

TCDLY0

011

101

100

TCDLY0

011

3·t

CYCLE

3·t

CYCLE

5·t

CYCLE

4·t

CYCLE

CDLY0-C

3·t

CYCLE

010

001

010

TCDLY1

000

CYCLE

CDLY1-C

CYCLE

CAC

CYCLE

Figure 40: TFRM Register

15 14 13 12 11 10

Read/write register.
Reset value is undefined.
TFRM3..0 - Specifies the position of the framing point
in t

CYCLE

units. This value must be greater than or

equal to the t

FRM,MIN

parameter. This is the minimum

offset between a ROW packet (which places a device
at ATTN) and the first COL packet (directed to that
device) which must be framed. This field may be
written with the values

0111

(7·t

CYCLE

) through

1010

(10·t

CYCLE

). TFRM is usually set to the value

which matches the largest t

RCD,MIN

parameter (modulo

4·t

CYCLE

) that is present in an RDRAM in the memory

system. Thus, if an RDRAM with t

RCD,MIN

= 9·t

CYCLE

were present, then TFRM would be programmed to
5·t

CYCLE

Control Register: TFRM

Address: 049

TFRM3..0

Figure 41: TRDLY Register

15 14 13 12 11 10

Read/write register.
Reset value is undefined.
TCDLY1 - Specifies the value of the t

CDLY1-C

core

parameter in t

CYCLE

units. This adds a programmable

delay to Q (read data) packets, permitting round trip
read delay to all devices to be equalized. This field may
be written with the values

000

(0·t

CYCLE

) through

010

(2·t

CYCLE

). Refer to Figure 39 for more details.

Control Register: TCDLY1

Address: 04a

TCDLY1

Page 37

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

Figure 42: SKIP Register

Figure 43: TEST Registers

15 14 13 12 11 10

Read/write register (except AS field).
Reset value is zero (SIO Reset).
AS - Autoskip. Read-only value determined by
autoskip circuit and stored when SETF serial command
is received by RDRAM during initialization. In figure
58, AS=1 corresponds to the early Q(a1) packet and
AS=0 to the Q(a1) packet one t

CYCLE

later for the four

uncertain cases.
MSE - Manual skip enable (0=auto, 1=manual).
MS - Manual skip (MS must be 1 when MSE=1).>
During initialization, the RDRAMs at the furthest point
in the fifth read domain may have selected the AS=0
value, placing them at the closest point in a sixth read
domain. Setting the MSE/MS fields to 1/1 overrides
the autoskip value and returns them to the furthest
point of the fifth read domain.

Control Register: SKIP

Address: 04b

MSE MS

15 14 13 12 11 10

Read/write registers.
Reset value of TEST78,79 is zero ( SIO Reset).
Do not read or write TEST78,79 after SIO reset.
TEST77 must be written with zero after SIO reset.
These registers must only be used for testing purposes.

Control Register: TEST77

Address: 04d

Control Register: TEST78

Address: 04e

Control Register: TEST79

Address: 04f

Figure 44: TCYCLE Register

15 14 13 12 11 10

Read/write register.
Reset value is undefined
TCYCLE13..0 - Specifies the value of the t

CYCLE

datasheet parameter in 64ps units. For the t

CYCLE,MIN

of 2.5ns (2500ps), this field should be written with the
value

00027

(39·64ps).

Control Register: TCYCLE

Address: 04c

TCYCLE13..TCYCLE0

Page 38

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

Power State Management

Table 17 summarizes the power states available to a Direct
RDRAM. In general, the lowest power states have the
longest operational latencies. For example, the relative
power levels of PDN state and STBY state have a ratio of
about 1:110, and the relative access latencies to get read data
have a ratio of about 250:1.

PDN state is the lowest power state available. The informa-
tion in the RDRAM core is usually maintained with self-
refresh; an internal timer automatically refreshes all rows of
all banks. PDN has a relatively long exit latency because the

TCLK/RCLK block must resynchronize itself to the external
clock signal.

NAP state is another low-power state in which either self-
refresh or REFA-refresh are used to maintain the core. See

Refresh

on page 42 for a description of the two refresh

mechanisms. NAP has a shorter exit latency than PDN
because the TCLK/RCLK block maintains its synchroniza-
tion state relative to the external clock signal at the time of
NAP entry. This imposes a limit (t

NLIMIT

) on how long an

RDRAM may remain in NAP state before briefly returning
to STBY or ATTN to update this synchronization state.

Figure 45 summarizes the transition conditions needed for
moving between the various power states. Note that NAP
and PDN have been divided into two substates (NAP-
A/NAP-S and PDN-A/PDN-S) to account for the fact that a
NAP or PDN exit may be made to either ATTN or STBY
states.

At initialization, the SETR/CLRR Reset sequence will put
the RDRAM into PDN-S state. The PDN exit sequence
involves an optional PDEV specification and bits on the
CMD and SIO

pins.

Once the RDRAM is in STBY, it will move to the
ATTN/ATTNR/ATTNW states when it receives a non-
broadcast ROWA packet or non-broadcast ROWR packet
with the ATTN command. The RDRAM returns to STBY
from these three states when it receives a RLX command.
Alternatively, it may enter NAP or PDN state from ATTN or
STBY states with a NAPR or PDNR command in an ROWR
packet. The PDN or NAP exit sequence involves an optional
PDEV specification and bits on the CMD and SIO0 pins.

The RDRAM returns to the ATTN or STBY state it was
originally in when it first entered NAP or PDN.

An RDRAM may only remain in NAP state for a time
t

NLIMIT

. It must periodically return to ATTN or STBY.

The NAPRC command causes a napdown operation if the
RDRAM's NCBIT is set. The NCBIT is not directly visible.
It is undefined on reset. It is set by a NAPR command to the
RDRAM, and it is cleared by an ACT command to the
RDRAM. It permits a controller to manage a set of
RDRAMs in a mixture of power states.

STBY state is the normal idle state of the RDRAM. In this
state all banks and sense amps have usually been left
precharged and ROWA and ROWR packets on the ROW
pins are being monitored. When a non-broadcast ROWA
packet or non-broadcast ROWR packet (with the ATTN
command) packet addressed to the RDRAM is seen, the
RDRAM enters ATTN state (see the right side of Figure 46).
This requires a time t

during which the RDRAM activates

the specified row of the specified bank. A time
TFRM·t

CYCLE

after the ROW packet, the RDRAM will be

Table 17: Power State Summary

Power

State

Description

Blocks consuming power

Power

State

Description

Blocks consuming power

PDN

Powerdown state.

Self-refresh

NAP

Nap state. Similar to PDN
except lower wake-up
latency.

Self-refresh or

REFA-refresh

TCLK/RCLK-Nap

STBY

Standby state.
Ready for ROW
packets.

REFA-refresh
TCLK/RCLK
ROW demux receiver

ATTN

Attention state.
Ready for ROW and COL
packets.

REFA-refresh
TCLK/RCLK
ROW demux receiver
COL demux receiver

ATTNR

Attention read state.
Ready for ROW and COL
packets.
Sending Q (read data)
packets.

REFA-refresh
TCLK/RCLK
ROW demux receiver
COL demux receiver
DQ mux transmitter
Core power

ATTNW

Attention write state.
Ready for ROW and COL
packets.
Ready for D (write data)
packets.

REFA-refresh
TCLK/RCLK
ROW demux receiver
COL demux receiver
DQ demux receiver
Core power

Page 39

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

able to frame COL packets (TFRM is a control register field
- see Figure 40). Once in ATTN state, the RDRAM will
automatically transition to the ATTNW and ATTNR states
as it receives WR and RD commands.

Once the RDRAM is in ATTN, ATTNW, or ATTNR states,
it will remain there until it is explicitly returned to the STBY
state with a RLX command. A RLX command may be given
in an ROWR, COLC , or COLX packet (see the left side of
Figure 46). It is usually given after all banks of the RDRAM
have been precharged; if other banks are still activated, then
the RLX command would probably not be given.

If a broadcast ROWA packet or ROWR packet (with the
ATTN command) is received, the RDRAM's power state
doesn't change. If a broadcast ROWR packet with RLXR
command is received, the RDRAM goes to STBY.

Figure 47 shows the NAP entry sequence (left). NAP state is
entered by sending a NAPR command in a ROW packet. A
time t

ASN

is required to enter NAP state (this specification is

provided for power calculation purposes). The clock on
CTM/CFM must remain stable for a time t

after the

NAPR command.

The RDRAM may be in ATTN or STBY state when the
NAPR command is issued. When NAP state is exited, the
RDRAM will return to the original starting state (ATTN or
STBY). If it is in ATTN state and a RLXR command is
specified with NAPR, then the RDRAM will return to STBY
state when NAP is exited.

Figure 47 also shows the PDN entry sequence (right). PDN
state is entered by sending a PDNR command in a ROW
packet. A time t

ASP

is required to enter PDN state (this spec-

ification is provided for power calculation purposes). The
clock on CTM/CFM must remain stable for a time t

after

the PDNR command.

The RDRAM may be in ATTN or STBY state when the
PDNR command is issued. When PDN state is exited, the
RDRAM will return to the original starting state (ATTN or
STBY). If it is in ATTN state and a RLXR command is
specified with PDNR, then the RDRAM will return to STBY
state when PDN is exited. The current- and slew-rate-control
levels are re-established.

The RDRAM's write buffer must be retired with the appro-
priate COP command before NAP or PDN are entered. Also,
all the RDRAM's banks must be precharged before NAP or
PDN are entered. The exception to this is if NAP is entered
with the NSR bit of the INIT register cleared (disabling self-
refresh in NAP). The commands for relaxing, retiring, and
precharging may be given to the RDRAM as late as the
ROPa0, COPa0, and XOPa0 packets in Figure 47. No broad-
cast packets nor packets directed to the RDRAM entering
Nap or PDN may overlay the quiet window. This window
extends for a time t

NPQ

after the packet with the NAPR or

PDNR command.

Figure 48 shows the NAP and PDN exit sequences. These
sequences are virtually identical; the minor differences will
be highlighted in the following description.

Before NAP or PDN exit, the CTM/CFM clock must be
stable for a time t

. Then, on a falling and rising edge of

SCK, if there is a

on the CMD input, NAP or PDN state

will be exited. Also, on the falling SCK edge the SIO0 input
must be at a 0 for NAP exit and 1 for PDN exit.

If the PSX bit of the INIT register is 0, then a device
PDEV5..0 is specified for NAP or PDN exit on the DQA5..0
pins. This value is driven on the rising SCK edge 0.5 or 1.5
SCK cycles after the original falling edge, depending upon
the value of the DQS bit of the NAPX register. If the PSX bit
of the INIT register is 1, then the RDRAM ignores the

Figure 45: Power State Transition Diagram

automatic

a
u

t
o

a
t
i
c

a
u

t
o

a
t
i
c

a
u

t
o

a
t
i
c

a
u

t
o

a
t
i
c

ATTNR

ATTNW

ATTN

STBY

SETR/CLRR

NAP-A

NAPR · RLXR

Notation:

SETR/CLRR - SETR/CLRR Reset sequence in SRQ packets

NLIMIT

NAP

NAP-S

PDEV.CMD·SIO0

NAPR · RLXR

PDEV.CMD·SIO0

PDN-A

PDNR

RLXR

PDN

PDN-S

PDEV.CMD·SI O0

PDNR

RLXR

PDEV.CMD·SI O0

PDNR - PDNR command in ROWR packet
NAPR - NAPR command in ROWR packet
RLXR - RLX command in ROWR packet
RLX - RLX command in ROWR,COLC,COLX packets
SIO0 - SIO0 input value
PDEV.CMD - (PDEV=DEVID)·(CMD=01)
ATTN - ROWA packet (non-broadcast) or ROWR packet

(non-broadcast) with ATTN command

Page 40

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

PDEV5..0 address packet and exits NAP or PDN when the
wake-up sequence is presented on the CMD wire. The ROW
and COL pins must be quiet at a time t

around the indi-

cated falling SCK edge (timed with the PDNX or NAPX
register fields). After that, ROW and COL packets may be
directed to the RDRAM which is now in ATTN or STBY
state.

Figure 49 shows the constraints for entering and exiting
NAP and PDN states. On the left side, an RDRAM exits
NAP state at the end of cycle T

. This RDRAM may not re-

enter NAP or PDN state for an interval of t

NU0

. The

RDRAM enters NAP state at the end of cycle T

. This

RDRAM may not re-exit NAP state for an interval of t

NU1

The equations for these two parameters depend upon a
number of factors, and are shown at the bottom of the figure.
NAPX is the value in the NAPX field in the NAPX register.

On the right side of Figure 48, an RDRAM exits PDN state
at the end of cycle T

. This RDRAM may not re-enter PDN

or NAP state for an interval of t

PU0

. The RDRAM enters

PDN state at the end of cycle T

. This RDRAM may not re-

exit PDN state for an interval of t

PU1

. The equations for

these two parameters depend upon a number of factors, and
are shown at the bottom of the figure. PDNX is the value in
the PDNX field in the PDNX register.

Figure 46: STBY Entry (left) and STBY Exit (right)

STBY

ATTN

CTM/CFM

DQA8..0

DQB8..0

COL4

..COL0

ROW2

..ROW0

CTM/CFM

DQA8..0

DQB8..0

COL4

..COL0

ROW2

..ROW0

RLXR

Power

State

ATTN

Power

State

STBY

ROP a0

RLXC
RLXX

TFRM·t

CYCLE

ROP = non-broadcast ROWA
or ROWR/ATTN

a0 = {d0,b0,r0}
a1 = {d1,b1,c1}

No COL packets may be
placed in the three
indicated positions; i.e. at

(TFRM - {1,2,3})·t

CYCLE

A COL packet to device d0
(or any other device) is okay
at

(TFRM)·t

CYCLE

or later.

A COL packet to another
device (d1!= d0) is okay at

(TFRM - 4)·t

CYCLE

or earlier.

COP a1
XOP a1

COP a0
XOP a0

COP a1
XOP a1

Figure 47: NAP Entry (left) and PDN Entry (right)

CTM/CFM

DQA8..0

DQB8..0

COL4

..COL0

ROW2

..ROW0

CTM/CFM

DQA8..0

DQB8..0

COL4

..COL0

ROW2

..ROW0

ROP a0
(NAPR)

Power

State

Power

State

The (eventual) NAP/PDN exit will be to the same ATTN/STBY state the RDRAM was in prior to NAP/PDN entry

ROP a1

COP a0
XOP a0

COP a1
XOP a1

ASN

ATTN/STBY

NAP

ROP a0

(PDNR)

ROP a1

COP a0
XOP a0

COP a1
XOP a1

ASP

ATTN/STBY

PDN

quiet

NPQ

restricted

a0 = {d0,b0,r0,c0}
a1 = {d1,b1,r1,c1}

No ROW or COL packets

directed to device d0 may
overlap the restricted
interval. No broadcast ROW
packets may overlap the quiet
interval.

ROW or COL packets to a
device other than d0 may
overlap the restricted
interval.

ROW or COL packets
directed to device d0 after the
restricted interval will be
ignored.

Page 41

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

Figure 48: NAP and PDN Exit

Figure 49: NAP Entry/Exit Windows (left) and PDN Entry/Exit Windows (right)

CTM/CFM

DQA8..0

DQB8..0

COL4

..COL0

ROW2

..ROW0

ROP

DQS=0

b,c

SCK

CMD

SIO0

SIO1

0/1

PDEV5..0

DQS=1

Use 0 for NAP exit, 1 for PDN exit

Device selection timing slot is selected by DQS field of NAPX register

The packet is repeated

from SIO0 to SIO1

restricted

Power

State

DQS=0

DQS=1

Exit to STBY or ATTN depends upon whether RLXR was

asserted at NAP or PDN entry time

STBY/ATTN

NAP/PDN

(

NAPX)·t

SCYCLE

)/(

256·PDNX·t

SCYCLE

)

restricted

COP
XOP

No ROW packets may
overlap the restricted interval

No COL packets may
overlap the restricted interval
if device PDEV is exiting the
NAP-A or PDN-A states

ROP

COP
XOP

The DQS field must be written with

for this RDRAM.

If PSX=1 in Init register, then
NAP/PDN exit is broadcast
(no PDEV field).

Effective hold becomes
t

'=t

+[PDNXA·64·t

SCYCLE

PDNXB,MAX

]-[PDNX·256·t

SCYCLE

]

if [PDNX·256·t

SCYCLE

] < [PDNXA·64·t

SCYCLE

PDNXB,MAX

PU0

= 5·t

CYCLE

+ (2+256·PDNX)·t

SCYCLE

PU1

= 8·t

CYCLE

- (0.5·t

SCYCLE

)

= 23·t

CYCLE

if PSR=0
if PSR=1

CTM/CFM

CMD

SCK

ROW2

..ROW0

NAPR

NU0

= 5·t

CYCLE

+ (2+NAPX)·t

SCYCLE

no entry to NAP or PDN

NU1

= 8·t

CYCLE

- (0.5·t

SCYCLE

)

PDNR

no exit

NU1

PU0

no exit

PU1

= 23·t

CYCLE

if NSR=0
if NSR=1

NAP entry

PDN entry

no entry to NAP or PDN

NAP exit

PDN exit

CTM/CFM

CMD

SCK

ROW2

..ROW0

Page 42

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

Refresh

RDRAMs, like any other DRAM technology, use volatile
storage cells which must be periodically refreshed. This is
accomplished with the REFA command. Figure 50 shows an
example of this.

The REFA command in the transaction is typically a broad-
cast command (DR4T and DR4F are both set in the ROWR
packet), so that in all devices bank number Ba is activated
with row number REFR, where REFR is a control register in
the RDRAM. When the command is broadcast and ATTN is
set, the power state of the RDRAMs (ATTN or STBY) will
remain unchanged. The controller increments the bank
address Ba for the next REFA command. When Ba is equal
to its maximum value, the RDRAM automatically incre-
ments REFR for the next REFA command.

On average, these REFA commands are sent once every
t

REF

BBIT+RBIT

(where BBIT are the number of bank

address bits and RBIT are the number of row address bits) so
that each row of each bank is refreshed once every t

REF

interval.

The REFA command is equivalent to an ACT command, in
terms of the way that it interacts with other packets (see
Table 10). In the example, an ACT command is sent after
t

to address b0, a different (non-adjacent) bank than the

REFA command.

A second ACT command can be sent after a time t

address c0, the same bank (or an adjacent bank) as the REFA
command.

Note that a broadcast REFP command is issued a time t

RAS

after the initial REFA command in order to precharge the

refreshed bank in all RDRAMs. After a bank is given a
REFA command, no other core operations (activate or
precharge) should be issued to it until it receives a REFP.

It is also possible to interleave refresh transactions (not
shown). In the figure, the ACT b0 command would be
replaced by a REFA b0 command. The b0 address would be
broadcast to all devices, and would be {Broad-
cast,Ba+2,REFR}. Note that the bank address should skip by
two to avoid adjacent bank interference. A possible bank
incrementing pattern would be: {13, 11, 9, 7, 5, 3, 1, 8, 10,
12, 14, 0, 2, 4, 6, 15, 29, 27, 25, 23, 21, 19, 17, 24, 26, 28,
30, 16, 18, 20, 22, 31}. Every time bank 31 is reached, the
REFA command would automatically increment the REFR
register.

A second refresh mechanism is available for use in PDN and
NAP power states. This mechanism is called self-refresh
mode. When the PDN power state is entered, or when NAP
power state is entered with the NSR control register bit set,
then self-refresh is automatically started for the RDRAM.

Self-refresh uses an internal time base reference in the
RDRAM. This causes an activate and precharge to be
carried out once in every t

REF

BBIT+RBIT

interval. The

REFB and REFR control registers are used to keep track of
the bank and row being refreshed.

Before a controller places an RDRAM into self-refresh
mode, it should perform REFA/REFP refreshes until the
bank address is equal to the maximum value. This ensures
that no rows are skipped. Likewise, when a controller returns
an RDRAM to REFA/REFP refresh, it should start with the
minimum bank address value (zero).

Figure 50: REFA/REFP Refresh Transaction Example

CTM/CFM

DQA8..0

DQB8..0

COL4

..COL0

ROW2

..ROW0

REFA a0

ACT c0

RAS

Transaction a: REFA

a0 = {Broadcast,Ba,REFR}

a1 = {Broadcast,Ba}

Transaction c: xx

c0 = {Dc, ==Ba, Rc}

REFA d0

REF

BBIT+RBIT

BBIT = # bank address bits

RBIT = # row address bits

ACT b0

Transaction d: REFA

d0 = {Broadcast,Ba+1,REFR}

REFB = REFB3..REFB0

REFR = REFR8..REFR0

Transaction b: xx

b0 = {Db, /={Ba,Ba+1,Ba-1}, Rb}

REFP a1

Page 43

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

Current and Temperature Control

Figure 51 shows an example of a transaction which performs
current control calibration. It is necessary to perform this
operation once to every RDRAM in every t

CCTRL

interval in

order to keep the I

output current in its proper range.

This example uses four COLX packets with a CAL
command. These cause the RDRAM to drive four calibra-
tion packets Q(a0) a time t

CAC

later. An offset of t

RDTOCC

must be placed between the Q(a0) packet and read data
Q(a1)from the same device. These calibration packets are
driven on the DQA4..3 and DQB4..3 wires. The TSQ bit of
the INIT register is driven on the DQA5 wire during same
interval as the calibration packets. The remaining DQA and
DQB wires are not used during these calibration packets.
The last COLX packet also contains a SAM command
(concatenated with the CAL command). The RDRAM

samples the last calibration packet and adjusts its I

current

value.

Unlike REF commands, CAL and SAM commands cannot
be broadcast. This is because the calibration packets from
different devices would interfere. Therefore, a current
control transaction must be sent every t

CCTRL

/N, where N is

the number of RDRAMs on the Channel. The device field
Da of the address a0 in the CAL/SAM command should be
incremented after each transaction.

Figure 52 shows an example of a temperature calibration
sequence to the RDRAM. This sequence is broadcast once
every t

TEMP

interval to all the RDRAMs on the Channel.

The TCEN and TCAL are ROP commands, and cause the
slew rate of the output drivers to adjust for temperature drift.
During the quiet interval t

TCQUIET

the devices being cali-

brated can't be read, but they can be written.

Figure 51: Current Control CAL/SAM Transaction Example

Figure 52: Temperature Calibration (TCEN-TCAL) Transactions to RDRAM

CTM/CFM

DQA8..0

DQB8..0

COL4

..COL0

ROW2

..ROW0

Transaction a0: CAL/SAM

a0 = {Da, Bx}

Transaction a1: RD

a1 = {Da, Bx}

CAL a0

CAL a2

Q (a0)

CAC

CAL a0

CAL/SAM a0

CAL

Q (a1)

READTOCC

a2 = {Da, Bx}

Transaction a2: CAL/SAM

Read data from the same
device from an earlier RD
command must be at this
packet position or earlier.

Read data from a different
device from an earlier RD
command can be anywhere
prior to the Q(a0) packet. .

Q (a1)

CCSAMTOREAD

Read data from a different
device from a later RD
command can be anywhere
after to the Q(a0) packet.

Read data from the same device
from a later RD command must
be at this packet position or
later.

CCTRL

DQA5 of the first calibrate packet has the inverted TSQ bit of INIT
control register; i.e. logic 0 or high voltage means hot temperature.
When used for monitoring, it should be enabled with the DQA3
bit (current control one value) in case there is no RDRAM present:

HotTemp = DQA5·DQA3

Note that DQB3 could be used instead of DQA3.

CTM/CFM

DQA8..0

DQB8..0

COL4

..COL0

ROW2

..ROW0

TCEN

TCAL

TCEN

TCAL

No read data from devices

TCQUIET

being calibrated

TEMP

Any ROW packet may be placed
in the gap between the ROW
packets with the TCEN and
TCAL commands.

Page 44

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

Electrical Conditions

Timing Conditions

Table 18: Electrical Conditions

Symbol

Parameter and Conditions

Min

Max

Unit

Junction temperature under bias

100

DD,

DDA

Supply voltage

2.50 - 0.13

2.50 + 0.13

DD,N,

DDA,N

Supply voltage droop (DC) during NAP interval (t

NLIMIT

)

2.0

DD,N,

DDA,N

Supply voltage ripple (AC) during NAP interval (t

NLIMIT

)

-2.0

2.0

CMOS

Supply voltage for CMOS pins (2.5V controllers)
Supply voltage for CMOS pins (1.8V controllers)

2.50 - 0.13

1.80 - 0.1

2.50 + 0.25

1.80 + 0.2

V
V

TERM

Termination voltage

1.80 - 0.1

1.80 + 0.1

REF

Reference voltage

1.40 - 0.2

1.40 + 0.2

DIL

RSL data input - low voltage

REF

- 0.5

REF

- 0.2

DIH

RSL data input - high voltage

REF

+ 0.2

REF

+ 0.5

DIS

RSL data input swing: V

DIS

= V

DIH

- V

DIL

0.4

1.0

RSL data asymmetry: A

= [(V

DIH

- V

REF

) + (V

DIL

- V

REF

)]/V

DIS

-20

RSL clock input - crossing point of true and complement signals

1.3

1.8

RSL clock input - common mode V

= (V

CIH

CIL)

1.4

1.7

CIS,CTM

RSL clock input swing: V

CIS

= V

CIH

- V

CIL

(CTM,CTMN pins).

0.35

0.70

CIS,CFM

RSL clock input swing: V

CIS

= V

CIH

- V

CIL

(CFM,CFMN pins).

0.125

0.70

IL,CMOS

CMOS input low voltage

- 0.3

CMOS

/2 - 0.25

IH,CMOS

CMOS input high voltage

CMOS

/2 + 0.25

CMOS

+0.3

Table 19: Timing Conditions

Symbol

Parameter

Min

Max

Unit

Figure(s)

CYCLE

CTM and CFM cycle times (-600)
CTM and CFM cycle times (-711)
CTM and CFM cycle times (-800)

3.33
2.80
2.50

3.83
3.83
3.83

ns
ns
ns

Figure 53
Figure 53
Figure 53

, t

CTM and CFM input rise and fall times

0.2

0.5

Figure 53

, t

CTM and CFM high and low times

40%

60%

CYCLE

Figure 53

CTM-CFM differential (MSE/MS=0/0)
CTM-CFM differential (MSE/MS=1/1)

0.0
0.9

1.0
1.0

CYCLE

Figure 42
Figure 53

DCW

Domain crossing window

-0.1

0.1

CYCLE

Figure 59

, t

DQA/DQB/ROW/COL input rise/fall times

0.2

0.65

Figure 54

, t

DQA/DQB/ROW/COL-to-CFM set/hold @ t

CYCLE

=3.33ns

DQA/DQB/ROW/COL-to-CFM set/hold @ t

CYCLE

=2.81ns

DQA/DQB/ROW/COL-to-CFM set/hold @ t

CYCLE

=2.50ns

0.275

b,d

0.240

c,d

0.200

-
-
-

ns
ns
ns

Figure 54
Figure 54
Figure 54

DR1,

DF1

SIO0, SIO1 input rise and fall times

5.0

Figure 56

Page 45

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

DR2,

DF2

CMD, SCK input rise and fall times

2.0

Figure 56

CYCLE1

SCK cycle time - Serial control register transactions

1000

Figure 56

SCK cycle time - Power transitions

Figure 56

CH1

, t

CL1

SCK high and low times

4.25

Figure 56

CMD setup time to SCK rising or falling edge

1.25

Figure 56

CMD hold time to SCK rising or falling edge

Figure 56

SIO0 setup time to SCK falling edge

Figure 56

SIO0 hold time to SCK falling edge

Figure 56

PDEV setup time on DQA5..0 to SCK rising edge.

Figure 48,

Figure 57

PDEV hold time on DQA5..0 to SCK rising edge.

5.5

ROW2..0, COL4..0 setup time for quiet window

-1

CYCLE

Figure 48

ROW2..0, COL4..0 hold time for quiet window

CYCLE

Figure 48

IL,CMOS

CMOS input low voltage - over/undershoot voltage duration is less
than or equal to 5ns

- 0.7

CMOS

/2 -

0.4

IH,CMOS

CMOS input high voltage - over/undershoot voltage duration is
less than or equal to 5ns

CMOS

+ 0.4

CMOS

0.7

NPQ

Quiet on ROW/COL bits during NAP/PDN entry

CYCLE

Figure 47

READTOCC

Offset between read data and CC packets (same device)

CYCLE

Figure 51

CCSAMTOREAD

Offset between CC packet and read data (same device)

CYCLE

Figure 51

CTM/CFM stable before NAP/PDN exit

CYCLE

Figure 48

CTM/CFM stable after NAP/PDN entry

100

CYCLE

Figure 47

FRM

ROW packet to COL packet ATTN framing delay

CYCLE

Figure 46

NLIMIT

Maximum time in NAP mode

10.0

Figure 45

REF

Refresh interval

Figure 50

CCTRL

Current control interval

34 t

CYCLE

100ms

ms/t

CYCLE

Figure 51

TEMP

Temperature control interval

100

Figure 52

TCEN

TCE command to TCAL command

150

CYCLE

Figure 52

TCAL

TCAL command to quiet window

CYCLE

Figure 52

TCQUIET

Quiet window (no read data)

140

CYCLE

Figure 52

PAUSE

RDRAM delay (no RSL operations allowed)

200.0

page 28

a. MSE/MS are fields of the SKIP register. For this combination (skip override) the tDCW parameter range is effectively 0.0 to 0.0.
b. This parameter also applies to a -800 or -711 part when operated with t

CYCLE

=3.33ns.

c. This parameter also applies to a -800 part when operated with t

CYCLE

=2.81ns.

d. t

S,MIN

and t

H,MIN

for other t

CYCLE

values can be interpolated between or extrapolated from the timings at the 3 specified t

CYCLE

values.

e. With V

IL,CMOS

=0.5V

CMOS

-0.4V and V

IH,CMOS

=0.5V

CMOS

+0.4V

f. Effective hold becomes t

'=t

+[PDNXA·64·t

SCYCLE

PDNXB,MAX

]-[PDNX·256·t

SCYCLE

]

if [PDNX·256·t

SCYCLE

] < [PDNXA·64·t

SCYCLE

PDNXB,MAX

]. See Figure 48.

Table 19: Timing Conditions

Symbol

Parameter

Min

Max

Unit

Figure(s)

Page 46

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

Electrical Characteristics

Timing Characteristics

Table 20: Electrical Characteristics

Symbol

Parameter and Conditions

Min

Max

Unit

Junction-to-Case thermal resistance

0.2

C/Watt

REF

current @ V

REF,MAX

-10

RSL output high current @ (0

OUT

)

-10

ALL

RSL I

current @ V

= 0.9V, V

DD,MIN

, T

J,MAX

30.0

90.0

RSL I

current resolution step

2.0

OUT

Dynamic output impedance

150

I,CMOS

CMOS input leakage current @ (0

I,CMOS

CMOS

)

-10.0

10.0

OL,CMOS

CMOS output voltage @ I

OL,CMOS

= 1.0mA

0.3

OH,CMOS

CMOS output high voltage @ I

OH,CMOS

= -0.25mA

CMOS

-0.3

a. This measurement is made in manual current control mode; i.e. with all output device legs sinking current.

Table 21: Timing Characteristics

Symbol

Parameter

Min

Max

Unit

Figure(s)

CTM-to-DQA/DQB output time @ t

CYCLE

=3.33ns

CTM-to-DQA/DQB output time @ t

CYCLE

=2.81ns

CTM-to-DQA/DQB output time @ t

CYCLE

=2.50ns

-0.350

a,c

-0.300

b,c

-0.260

+0.350

a,c

+0.300

b,c

+0.260

ns
ns
ns

Figure 55
Figure 55
Figure 55

, t

DQA/DQB output rise and fall times

0.2

0.45

Figure 55

SCK(neg)-to-SIO0 delay @ C

LOAD,MAX

= 20pF (SD read data valid).

Figure 58

QR1

, t

QF1

SIO

OUT

rise/fall @ C

LOAD,MAX

= 20pF

Figure 58

PROP1

SIO0-to-SIO1 or SIO1-to-SIO0 delay @ C

LOAD,MAX

= 20pF

Figure 58

NAPXA

NAP exit delay - phase A

Figure 48

NAPXB

NAP exit delay - phase B

Figure 48

PDNXA

PDN exit delay - phase A

Figure 48

PDNXB

PDN exit delay - phase B

9000

CYCLE

Figure 48

ATTN-to-STBY power state delay

CYCLE

Figure 46

STBY-to-ATTN power state delay

CYCLE

Figure 46

ASN

ATTN/STBY-to-NAP power state delay

CYCLE

Figure 47

ASP

ATTN/STBY-to-PDN power state delay

CYCLE

Figure 47

a. This parameter also applies to a -800 or -711 part when operated with t

CYCLE

=3.33ns.

b. This parameter also applies to a -800 part when operated with t

CYCLE

=2.81ns.

c. t

Q,MIN

and t

Q,MAX

for other t

CYCLE

values can be interpolated between or extrapolated from the timings at the 3 specified t

CYCLE

values.

Page 47

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

RSL - Clocking

Figure 53 is a timing diagram which shows the detailed
requirements for the RSL clock signals on the Channel.

The CTM and CTMN are differential clock inputs used for
transmitting information on the DQA and DQB, outputs.

Most timing is measured relative to the points where they
cross. The t

CYCLE

parameter is measured from the falling

CTM edge to the falling CTM edge. The t

and t

param-

eters are measured from falling to rising and rising to falling
edges of CTM. The t

and t

rise- and fall-time parame-

ters are measured at the 20% and 80% points.

The CFM and CFMN are differential clock outputs used for
receiving information on the DQA, DQB, ROW and COL
outputs. Most timing is measured relative to the points
where they cross. The t

CYCLE

parameter is measured from

the falling CFM edge to the falling CFM edge. The t

and

parameters are measured from falling to rising and rising

to falling edges of CFM. The t

and t

rise- and fall-time

parameters are measured at the 20% and 80% points.

The t

parameter specifies the phase difference that may be

tolerated with respect to the CTM and CFM differential
clock inputs (the CTM pair is always earlier).

Figure 53: RSL Timing - Clock Signals

CIH

50%

CIL

80%

20%

CTM

CTMN

CIH

50%

CIL

80%

20%

CFM

CFMN

CYCLE

X+

X-

X+

X-

Page 48

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

RSL - Receive Timing

Figure 54 is a timing diagram which shows the detailed
requirements for the RSL input signals on the Channel.

The DQA, DQB, ROW, and COL signals are inputs which
receive information transmitted by a Direct RAC on the
Channel. Each signal is sampled twice per t

CYCLE

interval.

The set/hold window of the sample points is t

The

sample points are centered at the 0% and 50% points of a
cycle, measured relative to the crossing points of the falling
CFM clock edge. The set and hold parameters are measured
at the V

REF

voltage point of the input transition.

The t

and t

rise- and fall-time parameters are measured

at the 20% and 80% points of the input transition.

Figure 54: RSL Timing - Data Signals for Receive

DIH

REF

DIL

80%

20%

CIH

50%

CIL

80%

20%

CFM

CFMN

DQA

ROW

DQB

0.5·t

CYCLE

even

odd

COL

X+

X-

Page 49

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

RSL - Transmit Timing

Figure 55 is a timing diagram which shows the detailed
requirements for the RSL output signals on the Channel.

The DQA and DQB signals are outputs to transmit informa-
tion that is received by a Direct RAC on the Channel. Each
signal is driven twice per t

CYCLE

interval. The beginning

and end of the even transmit window is at the 75% point of
the previous cycle and at the 25% point of the current cycle.
The beginning and end of the odd transmit window is at the

25% point and at the 75% point of the current cycle. These
transmit points are measured relative to the crossing points
of the falling CTM clock edge. The size of the actual
transmit window is less than the ideal t

CYCLE

/2, as indicated

by the non-zero values of t

Q,MIN

and t

Q,MAX

. The t

param-

eters are measured at the 50% voltage point of the output
transition.

The t

and t

rise- and fall-time parameters are measured

at the 20% and 80% points of the output transition.

Figure 55: RSL Timing - Data Signals for Transmit

Q,MIN

Q,MAX

Q,MIN

0.25·t

CYCLE

50%

80%

20%

CIH

50%

CIL

80%

20%

CTM

CTMN

even

odd

0.75·t

CYCLE

0.75·t

CYCLE

DQA

DQB

X+

X-

Page 50

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

CMOS - Receive Timing

Figure 56 is a timing diagram which shows the detailed
requirements for the CMOS input signals .

The CMD and SIO0 signals are inputs which receive infor-
mation transmitted by a controller (or by another RDRAM's
SIO1 output. SCK is the CMOS clock signal driven by the
controller. All signals are high true.

The cycle time, high phase time, and low phase time of the
SCK clock are t

CYCLE1

, t

CH1

and t

CL1

, all measured at the

50% level. The rise and fall times of SCK, CMD, and SIO0
are t

DR1

and t

DF1

, measured at the 20% and 80% levels.

The CMD signal is sampled twice per t

CYCLE1

interval, on

the rising edge (odd data) and the falling edge (even data).
The set/hold window of the sample points is t

H1.

The

SCK and CMD timing points are measured at the 50% level.

The SIO0 signal is sampled once per t

CYCLE1

interval on the

falling edge. The set/hold window of the sample points is
t

H2.

The SCK and SIO0 timing points are measured at the

50% level.

Figure 56: CMOS Timing - Data Signals for Receive

IH,CMOS

50%

IL,CMOS

80%

20%

SCK

CMD

DR2

even

odd

DF2

IH,CMOS

50%

IL,CMOS

80%

20%

DR2

DF2

CH1

CL1

CYCLE1

SIO0

DR1

DF1

IH,CMOS

50%

IL,CMOS

80%

20%

Page 51

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

The SCK clock is also used for sampling data on RSL inputs
in one situation. Figure 48 shows the PDN and NAP exit
sequences. If the PSX field of the INIT register is one (see
Figure 27), then the PDN and NAP exit sequences are broad-
cast; i.e. all RDRAMs that are in PDN or NAP will perform
the exit sequence. If the PSX field of the INIT register is
zero, then the PDN and NAP exit sequences are directed; i.e.

only one RDRAM that is in PDN or NAP will perform the
exit sequence.

The address of that RDRAM is specified on the DQA[5:0]
bus in the set hold window t

around the rising edge of

SCK. This is shown in Figure 57. The SCK timing point is
measured at the 50% level, and the DQA[5:0] bus signals are
measured at the V

REF

level.

Figure 57: CMOS Timing - Device Address for NAP or PDN Exit

IH,CMOS

50%

IL,CMOS

80%

20%

SCK

DIH

REF

DIL

80%

20%

DQA[5:0]

PDEV

Page 53

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

Figure 58 also shows the combinational path connecting
SIO0 to SIO1 and the path connecting SIO1 to SIO0 (read
data only). The t

PROP1

parameter specified this propagation

delay. The rise and fall times of SIO0 and SIO1 inputs must
be t

DR1

and t

DF1

, measured at the 20% and 80% levels. The

rise and fall times of SIO0 and SIO1 outputs are t

QR1

and

QF1

, measured at the 20% and 80% levels.

RSL - Domain Crossing Window

When read data is returned by the RDRAM, imformation
must cross from the receive clock domain (CFM) to the
transmit clock domain (CTM). The t

parameter permits

the CFM to CTM phase to vary through an entire cycle; i.e.
there is no restriction on the alignment of these two clocks.
A second parameter t

DCW

is needed in order to describe how

the delay between a RD command packet and read data
packet varies as a function of the t

value.

Figure 59 shows this timing for five distinct values of t

Case A (t

=0) is what has been used throughout this docu-

ment. The delay between the RD command and read data is
t

CAC

. As t

varies from zero to t

CYCLE

(cases A through

E), the command to data delay is (t

CAC

-t

). When the t

value is in the range 0 to t

DCW,MAX

, the command to data

delay can also be (t

CAC

-t

CYCLE

). This is shown as cases

A' and B' (the gray packets). Similarly, when the t

value

is in the range (t

CYCLE

DCW,MIN

) to t

CYCLE

, the command

to data delay can also be (t

CAC

-t

CYCLE

). This is shown

as cases D' and E' (the gray packets). The RDRAM will
work reliably with either the white or gray packet timing.
The delay value is selected at initialization, and remains
fixed thereafter.

Figure 59: RSL Transmit - Crossing Read Domains

CFM

COL

CTM

DQA/B

CYCLE

Case A

Case A'

CTM

DQA/B

DCW,MAX

Case B

DCW,MAX

Case B'

CTM

DQA/B

=0.5·t

CYCLE

Case C

CTM

DQA/B

CYCLE

DCW,MIN

Case D

CYCLE

DCW,MIN

Case D'

CTM

DQA/B

CYCLE

Case E

CYCLE

Case E'

RD a1

Q(a1)

CAC

-t

CAC

-t

CYCLE

Q(a1)

CAC

-t

CAC

-t

CYCLE

CAC

-t

CAC

-t

CYCLE

CAC

-t

CAC

-t

CYCLE

CAC

-t

···

Page 54

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

Timing Parameters

Table 22: Timing Parameter Summary

Parameter

Description

Min
-45
-800

Min
-45
-711

Min
-53
-600

Max

Units

Figure(s)

Row Cycle time of RDRAM banks -the interval between ROWA packets

with ACT commands to the same bank.

CYCLE

Figure 15

Figure 16

RAS

RAS-asserted time of RDRAM bank - the interval between ROWA packet

with ACT command and next ROWR packet with PRER

command to the

same bank.

CYCLE

Figure 15

Figure 16

Row Precharge time of RDRAM banks - the interval between ROWR packet

with PRER

command and next ROWA packet with ACT command to the

same bank.

CYCLE

Figure 15

Figure 16

Precharge-to-precharge time of RDRAM device - the interval between suc-

cessive ROWR packets with PRER

commands to any banks of the same

device.

CYCLE

Figure 12

RAS-to-RAS time of RDRAM device - the interval between successive

ROWA packets with ACT commands to any banks of the same device.

CYCLE

Figure 13

RCD

RAS-to-CAS Delay - the interval from ROWA packet with ACT command

to COLC packet with RD or WR command). Note - the RAS-to-CAS delay

seen by the RDRAM core (t

RCD-C

) is equal to t

RCD-C

= 1 + t

RCD

because of

differences in the row and column paths through the RDRAM interface.

CYCLE

Figure 15

Figure 16

CAC

CAS Access delay - the interval from RD command to Q read data. The

equation for t

CAC

is given in the TPARM register in Figure 39.

CYCLE

Figure 4

Figure 39

CWD

CAS Write Delay (interval from WR command to D write data.

CYCLE

Figure 4

CAS-to-CAS time of RDRAM bank - the interval between successive COLC

commands).

CYCLE

Figure 15

Figure 16

PACKET

Length of ROWA, ROWR, COLC, COLM or COLX packet.

CYCLE

Figure 3

RTR

Interval from COLC packet with WR command to COLC packet which

causes retire, and to COLM packet with bytemask.

CYCLE

Figure 17

OFFP

The interval (offset) from COLC packet with RDA command, or from

COLC packet with retire command (after WRA automatic precharge), or

from COLC packet with PREC command, or from COLX packet with PREX

command to the equivalent ROWR packet with PRER. The equation for

OFFP

is given in the TPARM register in Figure 39.

CYCLE

Figure 14

Figure 39

RDP

Interval from last COLC packet with RD command to ROWR packet with

PRER.

CYCLE

Figure 15

RTP

Interval from last COLC packet with automatic retire command to ROWR

packet with PRER.

CYCLE

Figure 16

a. Or equivalent PREC or PREX command. See Figure 14.

b. This is a constraint imposed by the core, and is therefore in units of

s rather than t

CYCLE

Page 55

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

Absolute Maximum Ratings

- Supply Current Profile

Table 23: Absolute Maximum Ratings

Symbol

Parameter

Min

Max

Unit

I,ABS

Voltage applied to any RSL or CMOS pin with respect to Gnd

- 0.3

+0.3

DD,ABS

, V

DDA,ABS

Voltage on VDD and VDDA with respect to Gnd

- 0.5

+1.0

STORE

Storage temperature

- 50

100

Table 24: Supply Current Profile

value

RDRAM blocks consuming power

Max

-45

-800

Max

-45

-711

Max

-53.3

-600

Unit

DD,PDN

Self-refresh only for INIT.LSR=0

TBD

DD,NAP

T/RCLK-Nap

TBD

DD,STBY

T/RCLK, ROW-demux

TBD

DD,ATTN

T/RCLK, ROW-demux, COL-demux

TBD

DD,ATTN-W

T/RCLK, ROW-demux,COL-demux,DQ-demux,1

WR-SenseAmp, 4

ACT-

Bank

TBD

DD,ATTN-R

T/RCLK, ROW-demux,COL-demux,DQ-mux,1

RD-SenseAmp, 4

ACT-

Bank

TBD

a. The CMOS interface consumes power in all power states.
b. This does not include the IOL sink current. The RDRAM dissipates IOL

VOL in each output driver when a logic one is driven.

Page 57

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

This circuit does not include pin coupling effects that are
often present in the packaged device. Because coupling
effects make the effective single-pin inductance L

, and

capacitance C

, a function of neighboring pins, these param-

eters are intrinsically data-dependent. For purposes of speci-
fying the device electrical loading on the Channel, the
effective L

and C

are defined as the worst-case values over

all specified operating conditions.

is defined as the effective pin inductance based on the

device pin assignment. Because the pad assignment places

each RSL signal adjacent to an AC ground (a Gnd or Vdd
pin), the effective inductance must be defined based on this
configuration. Therefore, L

assumes a loop with the RSL

pin adjacent to an AC ground.

is defined as the effective pin capacitance based on the

device pin assignment. It is the sum of the effective package
pin capacitance and the IO pad capacitance.

Table 25: RSL Pin Parasitics

Symbol

Parameter and Conditions - RSL pins

Min

Max

Unit

RSL effective input inductance

4.0

Mutual inductance between any DQA or DQB RSL signals.

0.2

Mutual inductance between any ROW or COL RSL signals.

0.6

Difference in L

value between any RSL pins of a single device.

1.8

RSL effective input capacitance

-800

RSL effective input capacitance

-711

RSL effective input capacitance

-600

2.0
2.0
2.0

2.4
2.4
2.6

pF
pF
pF

Mutual capacitance between any RSL signals.

0.1

Difference in C

value between average of CTM/CFM and any

RSL pins of a single device.

0.06

RSL effective input resistance

a. This value is a combination of the device IO circuitry and package capacitances.

Table 26: CMOS Pin Parasitics

Symbol

Parameter and Conditions - CMOS pins

Min

Max

Unit

I ,CMOS

CMOS effective input inductance

8.0

I ,CMOS

CMOS effective input capacitance (SCK,CMD)

1.7

2.1

I ,CMOS,SIO

CMOS effective input capacitance (SIO1, SIO0)

7.0

a. This value is a combination of the device IO circuitry and package capacitances.

Page 59

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

Glossary of Terms

ACT

Activate command from AV field.

activate

To access a row and place in sense amp.

adjacent

Two RDRAM banks which share sense
amps (also called doubled banks).

ASYM

CCA register field for RSL V

ATTN

Power state - ready for ROW/COL
packets.

ATTNR

Power state - transmitting Q packets.

ATTNW

Power state - receiving D packets.

Opcode field in ROW packets.

bank

A block of 2

RBIT

·2

CBIT

storage cells in the

core of the RDRAM.

Bank address field in COLC packet.

BBIT

CNFGA register field - # bank address
bits.

broadcast

An operation executed by all RDRAMs.

Bank address field in ROW packets.

bubble

Idle cycle(s) on RDRAM pins needed
because of a resource constraint.

BYT

CNFGB register field - 8/9 bits per byte.

Bank address field in COLX packet.

Column address field in COLC packet.

CAL

Calibrate (I

) command in XOP field.

CBIT

CNFGB register field - # column address
bits.

CCA

Control register - current control A.

CCB

Control register - current control B.

CFM,CFMN

Clock pins for receiving packets.

Channel

ROW/COL/DQ pins and external wires.

CLRR

Clear reset command from SOP field.

CMD

CMOS pin for initialization/power control.

CNFGA

Control register with configuration fields.

CNFGB

Control register with configuration fields.

COL

Pins for column-access control.

COL

COLC,COLM,COLX packet on COL pins.

COLC

Column operation packet on COL pins.

COLM

Write mask packet on COL pins.

column

Rows in a bank or activated row in sense
amps have 2

CBIT

dualocts column storage.

command

A decoded bit-combination from a field.

COLX

Extended operation packet on COL pins.

controller

A logic-device which drives the
ROW/COL /DQ wires for a Channel of
RDRAMs.

COP

Column opcode field in COLC packet.

core

The banks and sense amps of an RDRAM.

CTM,CTMN

Clock pins for transmitting packets.

current control

Periodic operations to update the proper

value of RSL output drivers.

Write data packet on DQ pins.

DBL

CNFGB register field - doubled-bank.

Device address field in COLC packet.

device

An RDRAM on a Channel.

DEVID

Control register with device address that is
matched against DR, DC, and DX fields.

Device match for ROW packet decode.

doubled-bank

RDRAM with shared sense amp.

DQA and DQB pins.

DQA

Pins for data byte A.

DQB

Pins for data byte B.

DQS

NAPX register field - PDN/NAP exit.

DR,DR4T,DR4F

Device address field and packet framing

fields in ROWA and ROWR packets.

dualoct

16 bytes - the smallest addressable datum.

Device address field in COLX packet.

field

A collection of bits in a packet.

INIT

Control register with initialization fields.

initialization

Configuring a Channel of RDRAMs so
they are ready to respond to transactions.

LSR

CNFGA register field - low-power self-
refresh.

Mask opcode field (COLM/COLX packet).

Field in COLM packet for masking byte A.

Field in COLM packet for masking byte B.

MSK

Mask command in M field.

MVER

Control register - manufacturer ID.

NAP

Power state - needs SCK/CMD wakeup.

NAPR

Nap command in ROP field.

NAPRC

Conditional nap command in ROP field.

NAPXA

NAPX register field - NAP exit delay A.

NAPXB

NAPX register field - NAP exit delay B.

NOCOP

No-operation command in COP field.

NOROP

No-operation command in ROP field.

Page 60

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

NOXOP

No-operation command in XOP field.

NSR

INIT register field- NAP self-refresh.

packet

A collection of bits carried on the Channel.

PDN

Power state - needs SCK/CMD wakeup.

PDNR

Powerdown command in ROP field.

PDNXA

Control register - PDN exit delay A.

PDNXB

Control register - PDN exit delay B.

pin efficiency

The fraction of non-idle cycles on a pin.

PRE

PREC,PRER,PREX precharge commands.

PREC

Precharge command in COP field.

precharge

Prepares sense amp and bank for activate.

PRER

Precharge command in ROP field.

PREX

Precharge command in XOP field.

PSX

INIT register field - PDN/NAP exit.

PSR

INIT register field - PDN self-refresh.

PVER

CNFGB register field - protocol version.

Read data packet on DQ pins.

Row address field of ROWA packet.

RBIT

CNFGB register field - # row address bits.

RD/RDA

Read (/precharge) command in COP field.

read

Operation of accesssing sense amp data.

receive

Moving information from the Channel into
the RDRAM (a serial stream is demuxed).

REFA

Refresh-activate command in ROP field.

REFB

Control register - next bank (self-refresh).

REFBIT

CNFGA register field - ignore bank bits
(for REFA and self-refresh).

REFP

Refresh-precharge command in ROP field.

REFR

Control register - next row for REFA.

refresh

Periodic operations to restore storage cells.

retire

The automatic operation that stores write
buffer into sense amp after WR command.

RLX

RLXC,RLXR,RLXX relax commands.

RLXC

Relax command in COP field.

RLXR

Relax command in ROP field.

RLXX

Relax command in XOP field.

ROP

Row-opcode field in ROWR packet.

row

CBIT

dualocts of cells (bank/sense amp).

ROW

Pins for row-access control

ROW

ROWA or ROWR packets on ROW pins.

ROWA

Activate packet on ROW pins.

ROWR

Row operation packet on ROW pins.

Alternate name for ROW/COL pins.

RSL

Rambus Signaling Levels.

SAM

Sample (I

) command in XOP field.

Serial address packet for control register
transactions w/ SA address field.

SBC

Serial broadcast field in SRQ.

SCK

CMOS clock pin..

Serial data packet for control register
transactions w/ SD data field.

SDEV

Serial device address in SRQ packet.

SDEVID

INIT register field - Serial device ID.

self-refresh

Refresh mode for PDN and NAP.

sense amp

Fast storage that holds copy of bank's row.

SETF

Set fast clock command from SOP field.

SETR

Set reset command from SOP field.

SINT

Serial interval packet for control register
read/write transactions.

SIO0,SIO1

CMOS serial pins for control registers.

SOP

Serial opcode field in SRQ.

SRD

Serial read opcode command from SOP.

SRP

INIT register field - Serial repeat bit.

SRQ

Serial request packet for control register
read/write transactions.

STBY

Power state - ready for ROW packets.

SVER

Control register - stepping version.

SWR

Serial write opcode command from SOP.

TCAS

TCLSCAS register field - t

CAS

core delay.

TCLS

TCLSCAS register field - t

CLS

core delay.

TCLSCAS

Control register - t

CAS

and t

CLS

delays.

TCYCLE

Control register - t

CYCLE

delay.

TDAC

Control register - t

DAC

delay.

TEST77

Control register - for test purposes.

TEST78

Control register - for test purposes.

TRDLY

Control register - t

RDLY

delay.

transaction

ROW,COL,DQ packets for memory
access.

transmit

Moving information from the RDRAM
onto the Channel (parallel word is muxed).

WR/WRA

Write (/precharge) command in COP field.

write

Operation of modifying sense amp data.

XOP

Extended opcode field in COLX packet.

Page 61

Direct RDRAM

K4R881869M

Rev. 0.9 Jan. 2000

Preliminary

Table Of Contents

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Key Timing Parameters/Part Numbers . . . . . . . . . . . 1

Pinouts and Definitions . . . . . . . . . . . . . . . . . . . . . . . 2

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6,7

Field Encoding Summary . . . . . . . . . . . . . . . . . . . . .8,9

DQ Packet Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 10

COLM Packet to D Packet Mapping . . . . . . . . . .10,11

ROW-to-ROW Packet Interaction . . . . . . . . . . . 12, 13

ROW-to-COL Packet Interaction . . . . . . . . . . . . . . . 13

COL-to-COL Packet Interaction . . . . . . . . . . . . . . . . 14

COL-to-ROW Packet Interaction . . . . . . . . . . . . . . . 15

ROW-to-ROW Examples . . . . . . . . . . . . . . . . . . .16,17

Row and Column Cycle Description . . . . . . . . . . . . 17

Precharge Mechanisms . . . . . . . . . . . . . . . . . . . .18,19

Read Transaction - Example . . . . . . . . . . . . . . . . . . 20

Write Transaction - Example . . . . . . . . . . . . . . . . . . 21

Write/Retire - Examples . . . . . . . . . . . . . . . . . . . 22, 23

Interleaved Write - Example. . . . . . . . . . . . . . . . . . . 24

Interleaved Read - Example . . . . . . . . . . . . . . . . . . 25

Interleaved RRWW . . . . . . . . . . . . . . . . . . . . . . . . . 25

Control Register Transactions . . . . . . . . . . . . . . . . . 26

Control Register Packets . . . . . . . . . . . . . . . . . . . . . 27

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28-29

Control Register Summary. . . . . . . . . . . . . . . . . 30-37

Power State Management . . . . . . . . . . . . . . . . . 38-41

Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Current and Temperature Control . . . . . . . . . . . . . . 43

Electrical Conditions . . . . . . . . . . . . . . . . . . . . . . . . 44

Timing Conditions . . . . . . . . . . . . . . . . . . . . . . . .44-45

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 46

Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . 46

RSL Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

RSL - Receive Timing . . . . . . . . . . . . . . . . . . . . . . . 48

RSL - Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . 49

CMOS - Receive Timing . . . . . . . . . . . . . . . . . . .50-51

CMOS - Transmit Timing . . . . . . . . . . . . . . . . . . .52-53

RSL - Domain Crossing Window . . . . . . . . . . . . . . . 53

Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . 54

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . 55

- Supply Current Profile . . . . . . . . . . . . . . . . . . . 55

Capacitance and Inductance . . . . . . . . . . . . . . . .56-57

Center-Bonded

BGA Package . . . . . . . . . . . . . . . . 58

Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . .59-60

Direct Rambus and Direct RDRAM are trademarks of
Rambus Inc. Rambus, RDRAM, and the Rambus Logo are
registered trademarks of Rambus Inc.

This document contains advanced information that is subject
to change by Samsung without notice.

Document Version 0.9

Samsung Electronics Co., Ltd.
San #24 Nongseo-Ri, Kiheung-Eup Yongin-City
Kyunggi-Do, KOREA

Telephone: 82-331-209-4519

Fax: 82-2-760-7990
http://www.samsungsemi.com

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