SDRAM 128Mb F-die (x4, x8, x16)
CMOS SDRAM
Rev. 1.2 May 2004
* Samsung Electronics reserves the right to change products or specification without notice.
128Mb F-die SDRAM Specification
Revision 1.2
May 2004
SDRAM 128Mb F-die (x4, x8, x16)
CMOS SDRAM
Rev. 1.2 May 2004
Revision History
Revision 0.0 (Agust, 2003)
- First release.
Revision 0.1 (November, 2003)
- completed DC characteristics.
Revision 0.2 (November, 2003)
- Preliminary spec release.
Revision 1.0 (January, 2004)
- Revision 1.0 spec release.
- Modified ICC4 current from 110mA -> 140mA at x16
- Modified tSH from 0.8ns -> 1.0ns at 166MHz.
Revision 1.1 (February, 2004)
- Corrected typo.
Revision 1.2 (May, 2004)
Added Note 5. sentense of tRDL parameter
SDRAM 128Mb F-die (x4, x8, x16)
CMOS SDRAM
Rev. 1.2 May 2004
Part No.
Orgainization
Max Freq.
Interface
Package
K4S280432F-TC(L)75
32M x 4
133MHz (CL=3)
LVTTL
54pin TSOP(II)
K4S280832F-TC(L)75
16M x 8
133MHz (CL=3)
K4S281632F-TC(L)60/75
8M x 16
166MHz (CL=3)
The K4S280432F / K4S280832F / K4S281632F is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x
8,388,608 words by 4 bits / 4 x 4,194,304 words by 8 bits / 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG
s high perfor-
mance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible
on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to
be useful for a variety of high bandwidth, high performance memory system applications.
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system clock.
Burst read single-bit write operation
DQM (x4,x8) & L(U)DQM (x16) for masking
Auto & self refresh
64ms refresh period (4K Cycle)
GENERAL DESCRIPTION
FEATURES
8M x 4Bit x 4 Banks / 4M x 8Bit x 4 Banks / 2M x 16Bit x 4 Banks SDRAM
Ordering Information
Row & Column address configuration
Organization
Row Address
Column Address
32Mx4
A0~A11
A0-A9, A11
16Mx8
A0~A11
A0-A9
8Mx16
A0~A11
A0-A8
SDRAM 128Mb F-die (x4, x8, x16)
CMOS SDRAM
Rev. 1.2 May 2004
11
.
7
6
0.2
0
0.46
3
0.0
0
8
0.002
0.05
MIN
0.008
0.21
0.002
0.05
0
.
020
0.
5
0
(
)
0.005
-0.001
+0.003
0.125
-0.035
+0.075
0.40
0
10.1
6
0.4
5
~0.7
5
0.
018~
0.03
0
0.010
0.25
TYP
0~8
C
#54
#28
#1
#27
0.004
0.10
MAX
0.028
0.71
( )
0.012
0.30
0.0315
0.80
0.047
1.20
MAX
0.039
1.00
0.004
0.10
0.891
22.62
MAX
0.875
22.22
0.004
0.10
+0.10
-0.05
+
0.004
-0.002
54Pin TSOP(II) Package Dimension
Package Physical Dimension
SDRAM 128Mb F-die (x4, x8, x16)
CMOS SDRAM
Rev. 1.2 May 2004
Bank Select
Data Input Register
8M x 4 / 4M x 8 / 2M x 16
8M x 4 / 4M x 8 / 2M x 16
Sense AMP
O
u
tput Buf
f
er
I/O Control
Column Decoder
Latency & Burst Length
Programming Register
Addre
s
s Register
Row Buf
f
er
Refresh Co
unter
Row Deco
der
Col. Buf
f
er
LRAS
LCBR
LCKE
LRAS
LCBR
LWE
LDQM
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
LWE
LDQM
DQi
CLK
ADD
LCAS
LWCBR
8M x 4 / 4M x 8 / 2M x 16
8M x 4 / 4M x 8 / 2M x 16
Timing Register
* Samsung Electronics reserves the right to change products or specification without notice.
FUNCTIONAL BLOCK DIAGRAM
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