K4S281633D-RL(N)
Rev. 0.6 Nov. 2001
CMOS SDRAM
Preliminary
8Mx16
Revision 0.6
November 2001
SDRAM 54CSP
(V
DD
/V
DDQ
3.0V/3.0V & 3.3V/3.3V)
K4S281633D-RL(N)
Rev. 0.6 Nov. 2001
CMOS SDRAM
Preliminary
Revision History
Revision 0.0 (February 21. 2001, Target)
First generation of 128Mb Low Power SDRAM without special function (V
DD
3.0V, V
DDQ
3.0V)
Revision 0.1 (June 4. 2001, Target)
Addition of DC Current value.
Revision 0.2 (June 20. 2001, Target)
Changed device name from low power sdram to mobile dram.
Revision 0.3 (August 1. 2001, Target)
Change of tSAC from 6ns to 6.5ns in case of -1L part, from 7ns to 7.5ns in case of -15 part.
Change of tOH from 3ns to 3.5ns.
Change V
IH
min. from 2.0 V to 0.8xV
DDQ
and V
OH
min. from 2.4V to 0.9xV
DDQ.
Revision 0.4 (October 6. 2001, Preliminary)
Changed DC current.
Changed of CL2 tSAC from 6ns to 7ns and CL3 tSAC from 6.5ns to 7ns for -75 part.
Changed of CL2 tSAC from 6.5ns to 8ns and CL1 tSAC from 18ns to 20ns for -1L part.
Changed of tOH from 3ns to 2.5ns.
Changed of tSS from 2.5ns to 2.0ns for -75 part and from 3.0ns to 2.5ns for -1L part.
Integration of VDDQ 1.8V device and 2.5V device.
Changed VIH min. from 0.8xVDDQ to 0.9xVDDQ and VOH min. from 0.9xVDDQ to 0.95xVDDQ.
Changed VIL max. from 0.8V to 0.3V and VOL min. from 0.4V to 0.2V.
Changed IOH from -0.1mA to -2mA and IOL from 0.1mA to 2mA.
Erased -15 bin and added -1H bin.
Revision 0.5 (October 12. 2001, Preliminary)
Changed VIH min. from 0.9xVDDQ to 2.0V and VOH min. from 0.95xVDDQ to 2.4V.
Changed VIL max. from 0.3V to 0.8V and VOL min. from 0.2V to 0.4V.
Revision 0.6 (November 7. 2001, Preliminary)
Changed VIH min. from 2.0V to 2.2V and VIL max. from 0.8V to 0.5V.
K4S281633D-RL(N)
Rev. 0.6 Nov. 2001
CMOS SDRAM
Preliminary
3.0V & 3.3V power supply.
LVTTL compatible with multiplexed address.
Four banks operation.
MRS cycle with address key programs.
-. CAS latency (1 & 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
All inputs are sampled at the positive going edge of the system
clock.
Burst read single-bit write operation.
.
DQM for masking.
Auto refresh.
64ms refresh period (4K cycle).
Commercial Temperature Operation (-25
C ~ 70
C).
Extended Temperature Operation (-25
C ~ 85
C).
FEATURES
The K4S281633D is 134,217,728 bits synchronous high data
rate Dynamic RAM organized as 4 x 2,097,152 words by 16
bits, fabricated with SAMSUNG
s high performance CMOS
technology. Synchronous design allows precise cycle control
with the use of system clock and I/O transactions are possible
on every clock cycle. Range of operating frequencies, program-
mable burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high perfor-
mance memory system applications.
GENERAL DESCRIPTION
2M x 16Bit x 4 Banks SDRAM in 54CSP
Bank Select
Data Input Register
2M x 16
2M x 16
S
e
n
s
e
A
M
P
O
u
t
p
u
t
B
u
f
f
e
r
I
/
O
C
o
n
t
r
o
l
Column Decoder
Latency & Burst Length
Programming Register
A
d
d
r
e
s
s
R
e
g
i
s
t
e
r
R
o
w
B
u
f
f
e
r
R
e
f
r
e
s
h
C
o
u
n
t
e
r
R
o
w
D
e
c
o
d
e
r
C
o
l
.
B
u
f
f
e
r
L
R
A
S
L
C
B
R
LCKE
LRAS
LCBR
LWE
LDQM
CLK
CKE
CS
RAS
CAS
WE
LDQM
LWE
LDQM
DQi
CLK
ADD
LCAS
LWCBR
2M x 16
2M x 16
Timing Register
UDQM
* Samsung Electronics reserves the right to change products or specification without notice.
FUNCTIONAL BLOCK DIAGRAM
ORDERING INFORMATION
Part No.
Max Freq.
Interface Package
K4S281633D-RL/N75
133MHz(CL=3)
100MHz(CL=2)
LVTTL
54 CSP
K4S281633D-RL/N1H
100MHz(CL=2)
K4S281633D-RL/N1L 100MHz(CL=3)
*1
-RN ; Low Power, Operating Temperature : -25'C~85'C.
-RL ; Low Power, Operating Temperature : -25'C~70'C.
1. In case of 40MHz Frequency, CL1 can be supported.
Note :
K4S281633D-RL(N)
Rev. 0.6 Nov. 2001
CMOS SDRAM
Preliminary
54Ball(6x9) CSP
1
2
3
7
8
9
A
V
SS
DQ15
V
SSQ
V
DDQ
DQ0
V
D D
B
DQ14
DQ13
V
DDQ
V
SSQ
DQ2
DQ1
C
DQ12
DQ11
V
SSQ
V
DDQ
DQ4
DQ3
D
DQ10
DQ9
V
DDQ
V
SSQ
DQ6
DQ5
E
DQ8
NC
V
SS
V
D D
LDQM
DQ7
F
UDQM
CLK
CKE
CAS
RAS
WE
G
NC
A11
A9
BA0
BA1
CS
H
A8
A7
A6
A0
A1
A10
J
V
SS
A5
A4
A3
A2
V
D D
Pin Name
Pin Function
CLK
System Clock
CS
Chip Select
CKE
Clock Enable
A
0
~ A
11
Address
BA
0
~ BA
1
Bank Select Address
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
L(U)DQM
Data Input/Output Mask
DQ
0
~
15
Data Input/Output
V
DD
/V
SS
Power Supply/Ground
V
DDQ
/V
SSQ
Data Output Power/Ground
Package Dimension and Pin Configuration
< Bottom View
*1
>
< Top View
*2
>
< Top View
*2
>
*2: Top View
Symbol
Min
Typ
Max
A
0.90
0.95
1.00
A
1
0.30
0.35
0.40
E
-
8.00
-
E
1
-
6.40
-
D
-
8.00
-
D
1
-
6.40
-
e
-
0.80
-
b
0.40
0.45
0.50
-
-
0.08
[Unit:mm]
5
2
1
6
3
4
8
9
7
F
E
D
C
B
J
H
G
A
e
D
D
/
2
D
1
E
1
E
E/2
A
A1
b
Encapsulant
Max. 0.20
K
4
S
2
8
1
6
3
3
D
-
R
L
(
N
)
S
A
M
S
U
N
G
W
E
E
K
#A1 Ball Origin Indicator
*1: Bottom View
K4S281633D-RL(N)
Rev. 0.6 Nov. 2001
CMOS SDRAM
Preliminary
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
=-25
C ~ 70
C (Commercial), -25
C ~ 85
C (Extended))
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply voltage
V
D D
2.7
3.0
3.6
V
V
DDQ
2.7
3.0
3.6
V
Input logic high voltage
V
I H
2.2
3.0
V
DDQ
+0.3
V
1
Input logic low voltage
V
IL
-0.3
0
0.5
V
2
Output logic high voltage
V
O H
2.4
-
-
V
I
O H
= -2mA
Output logic low voltage
V
OL
-
-
0.4
V
I
OL
= 2mA
Input leakage current
I
LI
-10
-
10
uA
3
CAPACITANCE
(V
DD
= 3.0V, T
A
= 23
C, f = 1MHz, V
REF
=0.9V
50
mV)
Pin
Symbol
Min
Max
Unit
Note
Clock
C
CLK
2.0
4.0
pF
RAS, CAS, WE, CS, CKE, DQM
C
IN
2.0
4.0
pF
Address
C
ADD
2.0
4.0
pF
D Q
0
~ DQ
15
C
OUT
3.5
6.0
pF
1. V
IH
(max) = 5.3V AC. The overshoot voltage duration is
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
3ns.
3. Any input 0V
V
IN
V
DDQ
.
Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Dout is disabled, 0V
V
OUT
V
DDQ.
Note
:
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
V
I N
, V
OUT
-1.0 ~ 4.6
V
Voltage on V
D D
supply relative to Vss
V
DD
, V
DDQ
-1.0 ~ 4.6
V
Storage temperature
T
STG
-55 ~ +150
C
Power dissipation
P
D
1
W
Short circuit current
I
OS
50
mA
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Note :
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