K4S283232E-T
Rev. 1.0 May. 2003
CMOS SDRAM
Revision 1.0
4Mx32 SDRAM
E-die TSOP
May. 2003
K4S283232E-T
Rev. 1.0 May. 2003
CMOS SDRAM
Revision History
Revision 1.0 (May 14. 2003)
First spec release.
K4S283232E-T
Rev. 1.0 May. 2003
CMOS SDRAM
GENERAL DESCRIPTION
FEATURES
1M x 32Bit x 4 Banks SDRAM in 86
TSOP2
FUNCTIONAL BLOCK DIAGRAM
ORDERING INFORMATION
Part No.
Max Freq.
Interface Package
K4S283232E-TC/L60 166MHz(CL=3)
LVTTL 86TSOP2
K4S283232E-TC/L75 133MHz(CL=3)
K4S283232E-TC/L1L 100MHz(CL=3)
. 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system
clock
. Burst read single-bit write operation
DQM for masking
. Auto & self refresh
. 64ms refresh period (4K cycle).
. 86TSOP2.
Bank Select
Data Input Register
1M x 32
1M x 32
Sens
e AMP
Output Buf
f
er
I/
O C
o
nt
rol
Column Decoder
Latency & Burst Length
Programming Register
Addres
s Register
Row Buf
f
er
Refresh Counter
Row De
coder
Col. Buf
f
er
LRA
S
LCB
R
LCKE
LRAS
LCBR
LWE
CLK
CKE
CS
RAS
CAS
WE
DQM
LWE
LDQM
DQi
CLK
ADD
LCAS
LWCBR
1M x 32
1M x 32
Timing Register
* Samsung Electronics reserves the right to change products or specification without notice.
The K4S283232E is 134,217,728 bits synchronous high data
rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits,
fabricated with SAMSUNG
s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock and I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst lengths and programmable latencies allow the same
device to be useful for a variety of high bandwidth and high per-
formance memory system applications.
K4S283232E-T
Rev. 1.0 May. 2003
CMOS SDRAM
PIN CONFIGURATION (Top view)
V
DD
DQ0
V
DDQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
SSQ
DQ7
N.C
V
DD
DQM0
WE
CAS
RAS
CS
A11
BA0
BA1
A10/AP
A0
A1
A2
DQM2
V
DD
N.C
DQ16
V
SSQ
DQ17
DQ18
V
DDQ
DQ19
DQ20
V
SSQ
DQ21
DQ22
V
DDQ
DQ23
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V
SS
DQ15
V
SSQ
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
SSQ
DQ10
DQ9
V
DDQ
DQ8
N.C
V
SS
DQM1
N.C
N.C
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
V
SS
N.C
DQ31
V
DDQ
DQ30
DQ29
V
SSQ
DQ28
DQ27
V
DDQ
DQ26
DQ25
V
SSQ
DQ24
V
SS
86Pin TSOP (II)
(400mil x 875mil)
(0.5 mm Pin pitch)
K4S283232E-T
Rev. 1.0 May. 2003
CMOS SDRAM
PIN FUNCTION DESCRIPTION
Pin
Name
Input Function
CLK
System clock
Active on the positive going edge to sample all inputs.
CS
Chip select
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
A
0
~ A
11
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA
0
~ RA
11
, Column address : CA
0
~ CA
7
BA
0
~ BA
1
Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
Column address strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE
Write enable
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM
Data input/output mask
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active.
DQ
0
~
31
Data input/output
Data inputs/outputs are multiplexed on the same pins.
V
DD
/V
SS
Power supply/ground
Power and ground for the input buffers and the core logic.
V
DDQ
/V
SSQ
Data output power/ground
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
N.C/RFU
No connection
/reserved for future use
This pin is recommended to be left No Connection on the device.
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