K4S28323LF - F(H)E/N/S/C/L/R
February 2004
Mobile-SDRAM
2.5V power supply.
LVCMOS compatible with multiplexed address.
Four banks operation.
MRS cycle with address key programs.
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
EMRS cycle with address key programs.
All inputs are sampled at the positive going edge of the system
clock.
Burst read single-bit write operation.
Special Function Support.
-. PASR (Partial Array Self Refresh).
-. Internal TCSR (Temperature Compensated Self Refresh)
DQM for masking.
Auto refresh.
64ms refresh period (4K cycle).
Commercial Temperature Operation (-25
C ~ 70
C).
Extended Temperature Operation (-25
C ~ 85
C).
90Balls FBGA with 0.8mm ball pitch
( -FXXX : Leaded, -HXXX : Lead Free).
FEATURES
The K4S28323LF is 134,217,728 bits synchronous high data
rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits,
fabricated with SAMSUNG's high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock and I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst lengths and programmable latencies allow the same
device to be useful for a variety of high bandwidth and high per-
formance memory system applications.
GENERAL DESCRIPTION
ORDERING INFORMATION
- F(H)E/N/S : Normal/Low/Super Low Power, Extended Temperature(-25
C ~ 85
C)
- F(H)C/L/R : Normal/Low/Super Low Power, Commercial Temperature(-25
C ~ 70
C)
NOTES :
1. In case of 40MHz Frequency, CL1 can be supported.
2. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake.
Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific
purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.
Part No.
Max Freq.
Interface
Package
K4S28323LF-F(H)E/N/S/C/L/R60
166MHz(CL=3)
LVCMOS
90 FBGA
Leaded (Lead Free)
K4S28323LF-F(H)E/N/S/C/L/R75
133MHz(CL=3)
K4S28323LF-F(H)E/N/S/C/L/R1H
105MHz(CL=2)
K4S28323LF-F(H)E/N/S/C/L/R1L
105MHz(CL=3)
*1
1M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA
K4S28323LF - F(H)E/N/S/C/L/R
February 2004
Mobile-SDRAM
Bank Select
Data Input Register
1M x 32
1M x 32
Sense AMP
Output Buf
f
er
I/O Con
t
rol
Column Decoder
Latency & Burst Length
Programming Register
Addr
ess Re
gister
Ro
w
Bu
f
f
e
r
R
e
fresh Counte
r
Row Deco
der
C
ol.
Buf
f
er
LR
AS
LC
BR
LCKE
LRAS
LCBR
LWE
LDQM
CLK
CKE
CS
RAS
CAS
WE
DQM
LWE
LDQM
DQi
CLK
ADD
LCAS
LWCBR
1M x 32
1M x 32
Timing Register
FUNCTIONAL BLOCK DIAGRAM
K4S28323LF - F(H)E/N/S/C/L/R
February 2004
Mobile-SDRAM
90Ball(6x15) FBGA
1
2
3
7
8
9
A
DQ26
DQ24
V
SS
V
DD
DQ23
DQ21
B
DQ28
V
DDQ
V
SSQ
V
DDQ
V
SSQ
DQ19
C
V
SSQ
DQ27
DQ25
DQ22
DQ20
V
DDQ
D
V
SSQ
DQ29
DQ30
DQ17
DQ18
V
DDQ
E
V
DDQ
DQ31
NC
NC
DQ16
V
SSQ
F
V
SS
DQM3
A3
A2
DQM2
V
DD
G
A4
A5
A6
A10
A0
A1
H
A7
A8
NC
NC
BA1
A11
J
CLK
CKE
A9
BA0
CS
RAS
K
DQM1
NC
NC
CAS
WE
DQM0
L
V
DDQ
DQ8
V
SS
V
DD
DQ7
V
SSQ
M
V
SSQ
DQ10
DQ9
DQ6
DQ5
V
DDQ
N
V
SSQ
DQ12
DQ14
DQ1
DQ3
V
DDQ
P
DQ11
V
DDQ
V
SSQ
V
DDQ
V
SSQ
DQ4
R
DQ13
DQ15
V
SS
V
DD
DQ0
DQ2
Pin Name
Pin Function
CLK
System Clock
CS
Chip Select
CKE
Clock Enable
A
0
~ A
11
Address
BA
0
~ BA
1
Bank Select Address
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
DQM
0
~ DQM
3
Data Input/Output Mask
DQ
0
~
31
Data Input/Output
V
DD
/V
SS
Power Supply/Ground
V
DDQ
/V
SSQ
Data Output Power/Ground
Package Dimension and Pin Configuration
< Bottom View
*1
>
< Top View
*2
>
< Top View
*2
>
Symbol
Min
Typ
Max
A
-
1.10
1.20
A
1
0.30
0.35
0.40
E
-
8.00
-
E
1
-
6.40
-
D
-
13.00
-
D
1
-
11.20
-
e
-
0.80
-
b
0.40
0.45
0.50
z
-
-
0.10
[Unit:mm]
5
2
1
6
3
4
8
9
7
F
E
D
C
B
J
H
G
A
e
D
D/2
D
1
E
1
E
E/2
z
b
Substrate(2Layer)
#A1 Ball Origin Indicator
M
L
K
R
P
N
K4S28323LF-XXXX
SAMSUNG W
eek
A
A1
K4S28323LF - F(H)E/N/S/C/L/R
February 2004
Mobile-SDRAM
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= -25 to 85
C for Extended, -25 to 70
C for Commercial)
NOTES :
1. Samsung can support VDDQ 2.5V(in general case) and 1.8V(in specific case) for VDD 2.5V products.
Please contact to the memory marketing team in Samsung Electronics when considering the use of VDDQ 1.8V(Min 1.65V).
2. VIH (max) = 3.0V AC.The overshoot voltage duration is
3ns.
3. VIL (min) = -1.0V AC. The undershoot voltage duration is
3ns.
4. Any input 0V
VIN
VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.
5. Dout is disabled, 0V
VOUT
VDDQ.
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply voltage
V
DD
2.3
2.5
2.7
V
V
DDQ
2.3
2.5
2.7
V
1.65
-
2.7
V
1
Input logic high voltage
V
IH
0.8 x V
DDQ
-
V
DDQ
+ 0.3
V
2
Input logic low voltage
V
IL
-0.3
0
0.3
V
3
Output logic high voltage
V
OH
V
DDQ
-0.2
-
-
V
I
OH
= -0.1mA
Output logic low voltage
V
OL
-
-
0.2
V
I
OL
= 0.1mA
Input leakage current
I
LI
-10
-
10
uA
4
CAPACITANCE
(V
DD
= 2.5V, T
A
= 23
C, f = 1MHz, V
REF
=0.9V
50 mV)
Pin
Symbol
Min
Max
Unit
Note
Clock
C
CLK
-
4.0
pF
RAS, CAS, WE, CS, CKE
C
IN
-
4.0
pF
DQM
C
IN
-
4.0
pF
Address
C
ADD
-
4.0
pF
DQ
0
~ DQ
31
C
OUT
-
6.0
pF
ABSOLUTE MAXIMUM RATINGS
NOTES:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Parameter
Symbol
Value
Unit
Voltage on any pin relative to V
ss
V
IN
, V
OUT
-1.0 ~ 3.6
V
Voltage on V
DD
supply relative to V
ss
V
DD
, V
DDQ
-1.0 ~ 3.6
V
Storage temperature
T
STG
-55 ~ +150
C
Power dissipation
P
D
1.0
W
Short circuit current
I
OS
50
mA
K4S28323LF - F(H)E/N/S/C/L/R
February 2004
Mobile-SDRAM
DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= -25 to 85
C for Extended, -25 to 70
C for Commercial)
NOTES:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Internal TCSR can be supported.
In commercial Temp : Max 40
C/Max 70
C, In extended Temp : Max 40
C/Max 85
C
4. K4S28323LF-F(H)E/C**
5. K4S28323LF-F(H)N/L**
6. K4S28323LF-F(H)S/R**
7. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ).
Parameter
Symbol
Test Condition
Version
Unit
Note
-60
-75
-1H
-1L
Operating Current
(One Bank Active)
I
CC1
Burst length = 1
t
RC
t
RC
(min)
I
O
= 0 mA
90
75
75
70
mA
1
Precharge Standby Current
in power-down mode
I
CC2
P
CKE
V
IL
(max), t
CC
= 10ns
0.5
mA
I
CC2
PS CKE & CLK
V
IL
(max), t
CC
=
0.5
Precharge Standby Current
in non power-down mode
I
CC2
N
CKE
V
IH
(min), CS
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during
20ns
15
mA
I
CC2
NS
CKE
V
IH
(min), CLK
V
IL
(max), t
CC
=
Input signals are stable
7
Active Standby Current
in power-down mode
I
CC3
P
CKE
V
IL
(max), t
CC
= 10ns
5
mA
I
CC3
PS CKE & CLK
V
IL
(max), t
CC
=
5
Active Standby Current
in non power-down mode
(One Bank Active)
I
CC3
N
CKE
V
IH
(min), CS
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during
20ns
25
mA
I
CC3
NS
CKE
V
IH
(min), CLK
V
IL
(max), t
CC
=
Input signals are stable
20
mA
Operating Current
(Burst Mode)
I
CC
4
I
O
= 0 mA
Page burst
4Banks Activated
t
CCD
= 2CLKs
100
75
70
70
mA
1
Refresh Current
I
CC
5
t
RC
t
RC
(min)
170
150
140
120
mA
2
Self Refresh Current
I
CC
6
CKE
0.2V
-E/C
1500
uA
4
-N/L
600
5
-S/R
Internal TCSR
Max 40
Max 85/70
C
3
Full Array
300
600
uA
6
1/2 of Full Array
260
450
1/4 of Full Array
240
350
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