CMOS SDRAM
SDRAM 512Mb B-die (x4, x8, x16)
Rev. 1.0 July, 2003
512Mb B-die SDRAM Specification
Revision 1.0
July, 2003
* Samsung Electronics reserves the right to change products or specification without notice.
CMOS SDRAM
SDRAM 512Mb B-die (x4, x8, x16)
Rev. 1.0 July, 2003
Revision History
Revision 1.0 (July, 2003)
- First release.
CMOS SDRAM
SDRAM 512Mb B-die (x4, x8, x16)
Rev. 1.0 July, 2003
Part No.
Orgainization
Max Freq.
Interface
Package
K4S510432B-TC(L)75
128Mb x 4
133MHz
LVTTL
54pin TSOP
K4S510832B-TC(L)75
64Mb x 8
133MHz
LVTTL
54pin TSOP
K4S511632B-TC(L)75
32Mb x 16
133MHz
LVTTL
54pin TSOP
The K4S510432B / K4S510832B / K4S511632B is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x
33,554,432 words by 4 bits / 4 x 16,777,216 words by 8 bits / 4 x 8,388,608 words by 16 bits, fabricated with SAMSUNG's high perfor-
mance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible
on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to
be useful for a variety of high bandwidth, high performance memory system applications.
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8)
-. Burst type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system clock.
Burst read single-bit write operation
DQM (x4,x8) & L(U)DQM (x16) for masking
Auto & self refresh
64ms refresh period (8K Cycle)
GENERAL DESCRIPTION
FEATURES
32M x 4Bit x 4 Banks / 16M x 8Bit x 4 Banks / 8M x 16Bit x 4 Banks SDRAM
Ordering Information
Row & Column address configuration
Organization
Row Address
Column Address
128Mx4
A0~A12
A0-A9, A11, A12
64Mx8
A0~A12
A0-A9, A11
32Mx16
A0~A12
A0-A9
CMOS SDRAM
SDRAM 512Mb B-die (x4, x8, x16)
Rev. 1.0 July, 2003
11
.
7
6
0.20
0.
4
6
3
0.008
0.002
0.05
MIN
0.008
0.21
0.002
0.05
0.
0
2
0
0.
5
0
(
)
0.005
-0.001
+0.003
0.125
-0.035
+0.075
0.
40
0
10
.
1
6
0.
4
5
~
0
.
7
5
0
.
01
8~
0.
0
3
0
0.010
0.25
TYP
0~8
C
#54
#28
#1
#27
0.004
0.10
MAX
0.028
0.71
( )
0.012
0.30
0.0315
0.80
0.047
1.20
MAX
0.039
1.00
0.004
0.10
0.891
22.62
MAX
0.875
22.22
0.004
0.10
+0.10
-0.05
+
0.004
-0.002
54Pin TSOP Package Dimension
Package Physical Dimension
CMOS SDRAM
SDRAM 512Mb B-die (x4, x8, x16)
Rev. 1.0 July, 2003
Bank Select
Data Input Register
Sense AMP
Output
Buf
f
er
I
/O Contr
o
l
Column Decoder
Latency & Burst Length
Programming Register
Add
r
ess Regis
t
er
Row
Buf
f
er
Refresh Cou
n
ter
Row Decoder
C
ol. Buf
f
er
LRAS
LCBR
LCKE
LRAS
LCBR
LWE
LDQM
CLK
CKE
CS
RAS
CAS
WE
LWE
LDQM
DQi
CLK
ADD
LCAS
LWCBR
32Mx4 / 16Mx8 / 8Mx16
Timing Register
32Mx4 / 16Mx8 / 8Mx16
32Mx4 / 16Mx8 / 8Mx16
32Mx4 / 16Mx8 / 8Mx16
FUNCTIONAL BLOCK DIAGRAM
L(U)DQM
* Samsung Electronics reserves the right to change products or specification without notice.
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