K4S510832C

CMOS SDRAM

Rev. 0.2 Nov. 2001

DDP 512Mbit SDRAM

16M x 8bit x 4 Banks

Synchronous DRAM

LVTTL

Revision 0.2

Nov. 2001

* Samsung Electronics reserves the right to change products or specification without notice.

This is to advise Samsung customers that, until August 1, 2003, in accordance with certain terms of an agreement, Samsung is prohibited
from selling any DRAM products configured in "Multi-Die Plastic" format for use as components in general and scientific computers, such as
mainframes, servers, work stations or desk top personal computers (hereinafter "Prohibited Computer Use"). Applications such as mobile,
including cell phones, telecom, including televisions and display monitors, or non-desktop computer systems, including laptops, notebook
computers, are, however, permissible. "Multi-Die Plastic" is defined as two or more Dram die encapsulated within a single plastic leaded
package

K4S510832C

CMOS SDRAM

Rev. 0.2 Nov. 2001

The K4S510832C is 536,870,912 bits synchronous high data rate
Dynamic RAM organized as 4 x 16,785,216 words by 8 bits, fabri-
cated with SAMSUNG's high performance CMOS technology. Syn-
chronous design allows precise cycle control with the use of
system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and
programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system appli-
cations.

· JEDEC standard 3.3V power supply
· LVTTL compatible with multiplexed address
· Four banks operation
· MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
· All inputs are sampled at the positive going edge of the system

clock.
· Burst read single-bit write operation
· DQM for masking
· Auto & self refresh
· 64ms refresh period (8K Cycle)

GENERAL DESCRIPTION

FEATURES

FUNCTIONAL BLOCK DIAGRAM

16M x 8Bit x 4 Banks Synchronous DRAM

Bank Select

Data Input Register

2 x 8M x 8

t
p

t

B

f
f
e

I
/
O

t
r
o

Column Decoder

Latency & Burst Length

Programming Register

d
r
e

s
s

i
s
t
e

f
f
e

f
r
e

s
h

t
e

c
o

l
.

B

f
f
e

LCKE

LRAS

LCBR

LWE

LDQM

CLK

CKE

RAS

CAS

DQM

LWE

LDQM

DQi

CLK

ADD

LCAS

LWCBR

2 x 8M x 8

Timing Register

* Samsung Electronics reserves the right to change products or specification without notice.

ORDERING INFORMATION

Part No.

Max Freq.

Interface Package

K4S510832C-KC/L7C

133MHz(CL=2)

LVTTL

54pin

TSOP(II)

K4S510832C-KC/L75

133MHz(CL=3)

K4S510832C-KC/L1H

100MHz(CL=2)

K4S510832C-KC/L1L

100MHz(CL=3)

K4S510832C

CMOS SDRAM

Rev. 0.2 Nov. 2001

DQ0

DDQ

N.C

DQ1

SSQ

N.C

DQ2

DDQ

N.C

DQ3

SSQ

N.C

CS1

CAS
RAS

CS0

BA0
BA1

A10/AP

A0
A1

A2
A3

1
2

3
4
5

6
7
8

9
10
11

12
13

14
15
16

17
18
19

20
21
22

23
24

25
26
27

54
53

52
51
50

49
48

47
46
45

44
43
42

41
40
39

38
37
36

35
34

33
32
31

30
29
28

PIN CONFIGURATION (Top view)

DQ7

SSQ

N.C
DQ6

DDQ

N.C
DQ5

SSQ

N.C
DQ4

DDQ

N.C

CKE1
DQM

CLK
CKE0
A12

A11
A9
A8

A7
A6

A5
A4
V

54Pin TSOP (II)

(400mil x 875mil)

(0.8 mm Pin pitcH)

PIN FUNCTION DESCRIPTION

Pin

Name

Input Function

CLK

System clock

Active on the positive going edge to sample all inputs.

CS 0~1

Chip select

Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM

CKE0~1

Clock enable

Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.

~ A

Address

Row/column addresses are multiplexed on the same pins.
Row address : RA

~ RA

, Column address : CA

~ CA

~ BA

Bank select address

Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.

RAS

Row address strobe

Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.

CAS

Column address strobe

Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.

Write enable

Enables write operation and row precharge.
Latches data in starting from CAS , WE active.

DQM

Data input/output mask

Makes data output Hi-Z, t

SHZ

after the clock and masks the output.

Blocks data input when DQM active.

Data input/output

Data inputs/outputs are multiplexed on the same pins.

Power supply/ground

Power and ground for the input buffers and the core logic.

DDQ

SSQ

Data output power/ground

Isolated power supply and ground for the output buffers to provide improved noise
immunity.

K4S510832C

CMOS SDRAM

Rev. 0.2 Nov. 2001

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Value

Unit

Voltage on any pin relative to Vss

I N

, V

OUT

-1.0 ~ 4.6

Voltage on V

supply relative to Vss

, V

DDQ

-1.0 ~ 4.6

Storage temperature

STG

-55 ~ +150

Power dissipation

Short circuit current

Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Note :

DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to V

= 0V, T

= 0 to 70

Parameter

Symbol

Min

Typ

Max

Unit

Note

Supply voltage

, V

DDQ

3.0

3.3

3.6

Input logic high voltage

2.0

3.0

+0.3

Input logic low voltage

-0.3

0.8

Output logic high voltage

2.4

= -2mA

Output logic low voltage

0.4

= 2mA

Input leakage current

-10

1. V

I H

(max) = 5.6V AC. The overshoot voltage duration is

3ns.

2. V

(min) = -2.0V AC. The undershoot voltage duration is

3ns.

3. Any input 0V

DDQ

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

Notes :

CAPACITANCE

= 3.3V, T

= 23

C, f = 1MHz, V

REF

=1.4V

200

mV)

Pin

Symbol

Min

Max

Unit

Note

Clock

CLK

5.0

9.0

RAS, CAS , WE, DQM

5.0

10.0

Address

ADD

5.0

10.0

CS0~1, CKE0~1

Ccs

2.5

5.5

~ DQ

OUT

8.0

14.0

K4S510832C

CMOS SDRAM

Rev. 0.2 Nov. 2001

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, T

= 0 to 70

Parameter

Symbol

Test Condition

Version

Unit

Note

-7C

-75

-1H

-1L

Operating current
(One bank active)

CC1

Burst length = 1
t

R C

(min)

= 0 mA

120

110

Precharge standby current in
power-down mode

CC2

CKE

(max), t

= 10ns

CC2

CKE & CLK

(max), t

Precharge standby current in
non power-down mode

CC2

CKE

I H

(min), CS

I H

(min), t

= 10ns

Input signals are changed one time during 20ns

CC2

CKE

I H

(min), CLK

(max), t

Input signals are stable

Active Standby current
in power-down mode

CC3

CKE

(max), t

= 10ns

CC3

CKE & CLK

(max), t

Active standby current in
non power-down mode
(One bank active)

CC3

CKE

I H

(min), CS

I H

(min), t

= 10ns

Input signals are changed one time during 20ns

CC3

CKE

I H

(min), CLK

(max), t

Input signals are stable

Operating current
(Burst mode)

CC4

= 0 mA

Page burst
4banks activated.
t

CCD

= 2CLKs

140

130

Refresh current

CC5

R C

(min)

240

220

210

Self refresh current

CC6

CKE

0.2V

1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S510832C-KC**
4. K4S510832C-KL**
5. Unless otherwise noticed, input swing level is CMOS(V

DDQ

SSQ

Notes :

K4S510832C

CMOS SDRAM

Rev. 0.2 Nov. 2001

(AC operating conditions unless otherwise noted)

Parameter

Symbol

Version

Unit

Note

-7C

-75

-1H

-1L

Row active to row active delay

RRD

(min)

RAS to CAS delay

RCD

(min)

Row precharge time

(min)

Row active time

RAS

(min)

RAS

(max)

100

Row cycle time

(min)

Last data in to row precharge

RDL

(min)

CLK

2, 5

Last data in to Active delay

DAL

(min)

2 CLK + tRP

Last data in to new col. address delay

CDL

(min)

CLK

Last data in to burst stop

BDL

(min)

CLK

Col. address to col. address delay

CCD

(min)

CLK

Number of valid output data

CAS latency=3

CAS latency=2

AC OPERATING TEST CONDITIONS

= 3.3V

0.3V, T

= 0 to 70

Parameter

Value

Unit

AC input levels (Vih/Vil)

2.4/0.4

Input timing measurement reference level

1.4

Input rise and fall time

tr/tf = 1/1

Output timing measurement reference level

1.4

Output load condition

See Fig. 2

3.3V

1200

870

Output

50pF

(DC) = 2.4V, I

O H

= -2mA

(DC) = 0.4V, I

= 2mA

Vtt = 1.4V

Output

50pF

Z0 = 50

(Fig. 2) AC output load circuit

(Fig. 1) DC output load circuit

OPERATING AC PARAMETER

Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time

and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.

5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.

K4S510832C

CMOS SDRAM

Rev. 0.2 Nov. 2001

1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.

Notes :

AC CHARACTERISTICS

(AC operating conditions unless otherwise noted)

Parameter

Symbol

-7C

-75

-1H

-1L

Unit Note

Min

Max

Min

Max

Min

Max

Min

Max

CLK cycle time

CAS latency=3

7.5

1000

7.5

1000

CAS latency=2

7.5

CLK to valid
output delay

CAS latency=3

SAC

5.4

1,2

CAS latency=2

5.4

Output data
hold time

CAS latency=3

O H

CAS latency=2

CLK high pulse width

2.5

CLK low pulse width

2.5

Input setup time

1.5

Input hold time

0.8

CLK to output in Low-Z

SLZ

CLK to output
in Hi-Z

CAS latency=3

SHZ

5.4

CAS latency=2

5.4

K4S510832C

CMOS SDRAM

Rev. 0.2 Nov. 2001

SIMPLIFIED TRUTH TABLE

(V=Valid, X=Don't care, H=Logic high, L=Logic low)

Command

CKEn-1

CKEn

RAS

CAS

DQM

0,1

/AP

11,

12,

~ A

Note

Mode register set

OP code

1,2

Refresh

Auto refresh

Self
refresh

Entry

Exit

Bank active & row addr.

Row address

Read &
column address

Auto precharge disable

Column

address

~ A

)

Auto precharge enable

4,5

Write &
column address

Auto precharge disable

Column

address

~ A

)

Auto precharge enable

4,5

Burst Stop

Precharge

Bank selection

All banks

Clock suspend or
active power down

Entry

Exit

Precharge power down mode

Entry

Exit

DQM

No operation command

1. OP Code : Operand code
A

~ A

& BA

~ BA

: Program keys. (@ MRS)

2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA

~ BA

: Bank select addresses.

If both BA

and BA

are "Low" at read, write, row active and precharge, bank A is selected.

If both BA

is "High" and BA

is "Low" at read, write, row active and precharge, bank B is selected.

If both BA

is "Low" and BA

is "High" at read, write, row active and precharge, bank C is selected.

If both BA

and BA

are "High" at read, write, row active and precharge, bank D is selected.

If A

/AP is "High" at row precharge, BA

and BA

is ignored and all banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t

after the end of burst.

6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

Notes :

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: K4S510832C-KC/L7C

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: K4S510832C-KC/L7C