K4S511533C-YL/N/P
Rev. 1.2 Dec. 2002
CMOS SDRAM
Revision 1.2
December 2002
16Mx16
54CSP 2/CS
(VDD/VDDQ 3.0V/3.0V or 3.3V/3.3V)
Mobile SDRAM
K4S511533C-YL/N/P
Rev. 1.2 Dec. 2002
CMOS SDRAM
The K4S511533C is 536,870,912 bits synchronous high data
rate Dynamic RAM organized as 4 x 8,388,608 words by 16bits,
fabricated with SAMSUNG's high performance CMOS technology.
Synchronous design allows precise cycle control with the use of
system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and
programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system
applications.
3.0V power supply
LVCMOS compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
-. CAS latency (1 & 2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system
clock.
Burst read single-bit write operation.
DQM for masking
Auto & self refresh
64ms refresh period (8K cycle)
2 /CS Support.
Commercial Temperature Operation (-25
C ~ 70
C).
Extended Temperature Operation (-25
C ~ 85
C).
Industrial Temperature Operation (-40
C ~ 85
C).
54balls DDP CSP
GENERAL DESCRIPTION
FEATURES
FUNCTIONAL BLOCK DIAGRAM
8M x 16Bit x 4 Banks Mobile SDRAM
Samsung Electronics reserves the right to change products or specification without notice.
*
ORDERING INFORMATION
- YN : Low Power, Operating Temp : -25
C ~ 85
C.
- YL : Low Power, Operating Temp : -25
C ~ 70
C.
- YP : Low Power, Operating Temp : -40
C ~ 85
C.
Note :
1. In case of 33MHz Frequency, CL1 can be supported.
Part No.
Max Freq.
Interface Package
K4S511533C-YL/N/P80
125MHz(CL=3)
100MHz(CL=2)
LVCMOS
54 CSP
K4S511533C-YL/N/P1H
100MHz(CL=2)
K4S511533C-YL/N/P1L
100MHz(CL=3)
*1
16Mx16
16Mx16
DQ0~DQ15
A0~A12, BA0, BA1
CLK, /CAS, /RAS,
/WE, DQM, CKE
/CS1
/CS0
K4S511533C-YL/N/P
Rev. 1.2 Dec. 2002
CMOS SDRAM
54Ball(6x9) CSP
1
2
3
7
8
9
A
V
SS
DQ15
V
SSQ
V
DDQ
DQ0
V
D D
B
DQ14
DQ13
V
DDQ
V
SSQ
DQ2
DQ1
C
DQ12
DQ11
V
SSQ
V
DDQ
DQ4
DQ3
D
DQ10
DQ9
V
DDQ
V
SSQ
DQ6
DQ5
E
DQ8
CS1
V
SS
V
D D
LDQM
DQ7
F
UDQM
CLK
CKE
CAS
RAS
WE
G
A12
A11
A9
BA0
BA1
CS0
H
A8
A7
A6
A0
A1
A10
J
V
SS
A5
A4
A3
A2
V
D D
Pin Name
Pin Function
CLK
System Clock
CS
0
~
1
Chip Select
CKE
Clock Enable
A
0
~ A
12
Address
BA
0
~ BA
1
Bank Select Address
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
L(U)DQM
Data Input/Output Mask
DQ
0
~
15
Data Input/Output
V
DD
/V
SS
Power Supply/Ground
V
DDQ
/V
SSQ
Data Output Power/Ground
Package Dimension and Pin Configuration
Symbol
Min
Typ
Max
A
1.00
1.10
1.30
A
1
0.27
0.32
0.37
E
-
9.50
-
E
1
-
6.40
-
D
-
15.50
-
D
1
-
6.40
-
e
-
0.80
-
b
0.40
0.45
0.50
z
-
-
0.10
[Unit:mm]
5
2
1
6
3
4
8
9
7
F
E
D
C
B
J
H
G
A
e
D
D
/
2
D
1
E
1
E
E/2
A
A1
z
b
Encapsulant
Max. 0.20
K
4
S
5
1
1
5
3
3
C
-
X
X
X
X
#A1 Ball Origin Indicator
< Bottom View
*1
>
< Top View
*2
>
< Top View
*2
>
*1: Bottom View
*2: Top View
S
A
M
S
U
N
G
W
e
e
k
K4S511533C-YL/N/P
Rev. 1.2 Dec. 2002
CMOS SDRAM
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
=Commercial, Extended and Industrial)
Notes :
1. V
IH
(max) = 5.3V AC. The overshoot voltage duration is
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
3ns.
3. Any input 0V
V
IN
V
DDQ
.
Input leakage currents include HI-Z output leakage for all bi-directional buffers with tri-state outputs.
4. Dout is disabled, 0V
V
OUT
V
DDQ.
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply voltage
V
DD
2.7
3.0
3.6
V
V
DDQ
2.7
3.0
3.6
V
Input logic high voltage
V
I H
2.2
3.0
V
DDQ
+0.3
V
1
Input logic low voltage
V
IL
-0.3
0
0.5
V
2
Output logic high voltage
V
O H
2.4
-
-
V
I
O H
= -2mA
Output logic low voltage
V
OL
-
-
0.4
V
I
OL
= 2mA
Input leakage current
I
LI
-10
-
10
uA
3
ABSOLUTE MAXIMUM RATINGS
Notes :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
V
I N
, V
OUT
-1.0 ~ 4.6
V
Voltage on V
D D
supply relative to Vss
V
DD
, V
DDQ
-1.0 ~ 4.6
V
Storage temperature
T
STG
-55 ~ +150
C
Power dissipation
P
D
1
W
Short circuit current
I
OS
50
mA
CAPACITANCE
(V
DD
= 3.0V or 3.3V, T
A
= 23
C, f = 1MHz, V
REF
=0.9V
50
mV)
Pin
Symbol
Min
Max
Unit
Note
Clock
C
CLK
3.0
9.0
pF
RAS, CAS, WE, CKE, DQM
C
IN
3.0
9.0
pF
CS
C
IN
1.5
4.5
pF
Address
C
ADD
3.0
9.0
pF
DQ
0
~ DQ
15
C
OUT
6.0
13.0
pF
K4S511533C-YL/N/P
Rev. 1.2 Dec. 2002
CMOS SDRAM
DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= Commercial, Extended and Industrial)
Notes :
1. Measured with outputs open
2. Measured with operating(Icc1) condition for 1chip and precharge stanby condition in non power down mode for 1chip(Icc2N).
(Icc1
* = Icc1 +Icc2N)
3. Measured with operating(Icc4) condition for 1chip and active stanby condition in non power down mode for 1chip(Icc3N).
(Icc4
* = Icc4 +Icc3N)
4. Measured with active stanby condition in power down mode for 1chip (Icc3P/PS) and precharge stanby condition in
power down mode for 1chip (Icc2P/PS). (Icc3P/PS
* = Icc3P/PS +Icc2P/PS)
5. Measured with active stanby condition in non power down mode for 1chip (Icc3N/NS) and precharge stanby condition in
non power down mode for 1chip (Icc2N/NS). (Icc3N/NS
* = Icc3N/NS +Icc2N/NS)
6. Refresh period is 64ms.
Measured with refresh condition for 1chip (Icc5) and precharge stanby condition in non power down mode for 1chip (Icc2N).
(Icc5
* = Icc5 +Icc2N)
7. K4S511533C-YL**
8. K4S511533C-YN**
9. K4S511533C-YP**
10. Unless otherwise noted, input swing IeveI is CMOS(V
IH
/V
IL
=V
DDQ
/V
SSQ)
Parameter
Symbol
Test Condition
Version
Unit Note
-80
-1H
-1L
Operating Current
(One Bank Active)
I
C C 1
*
Burst length = 1
t
RC
t
R C
(min)
I
O
= 0 mA
100
90
85
mA
1.2
Precharge Standby Current
in power-down mode
I
CC2
P
CKE
V
IL
(max), t
CC
= 10ns
2
mA
I
C C 2
PS CKE & CLK
V
IL
(max), t
CC
=
2
Precharge Standby Current
in non power-down mode
I
CC2
N
CKE
V
IH
(min), CS
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
35
mA
I
CC2
NS
CKE
V
IH
(min), CLK
V
IL
(max), t
CC
=
Input signals are stable
25
Active Standby Current
in power-down mode
I
CC3
P
* CKE
V
IL
(max), t
CC
= 10ns
8
mA
4
I
CC3
PS
* CKE & CLK
V
IL
(max), t
CC
=
8
Active Standby Current
in non power-down mode
(One Bank Active)
I
C C 3
N
*
CKE
V
IH
(min), CS
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
45
mA
5
I
CC3
NS
*
CKE
V
IH
(min), CLK
V
IL
(max), t
CC
=
Input signals are stable
35
mA
Operating Current
(Burst Mode)
I
C C 4
*
I
O
= 0 mA
Page burst
4Banks Activated
t
CCD
= 2CLKs
145
125
115
mA
1.3
Refresh Current
I
C C 5
*
t
RC
t
R C
(min)
190
170
160
mA
6
Self Refresh Current
I
CC6
CKE
0.2V
-YL
1800
uA
7
-YN
8
-YP
9
K4S511533C-YL/N/P
Rev. 1.2 Dec. 2002
CMOS SDRAM
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. Minimum tRDL=2CLK and tDAL(=tRDL + tRP) is required to complete both of last data wite command(tRDL) and precharge
command(tRP). tRDL=1CLK can be supported only in the case under 100MHz with manual precharge mode.
4. All parts allow every cycle column address change.
5. In case of row precharge interrupt, auto precharge and read burst stop.
Parameter
Symbol
Version
Unit
Note
- 80
-1H
-1L
Row active to row active delay
t
RRD
(min)
16
20
20
ns
1
RAS to CAS delay
t
RCD
(min)
20
20
24
ns
1
Row precharge time
t
RP
(min)
20
20
24
ns
1
Row active time
t
RAS
(min)
48
50
60
ns
1
t
RAS
(max)
100
us
Row cycle time
t
R C
(min)
68
70
84
ns
1
Last data in to row precharge
t
R D L
(min)
2
CLK
2,3
Last data in to Active delay
t
DAL
(min)
tRDL + tRP
-
3
Last data in to new col. address delay
t
C D L
(min)
1
CLK
2
Last data in to burst stop
t
BDL
(min)
1
CLK
2
Col. address to col. address delay
t
CCD
(min)
1
CLK
4
Number of valid output data
CAS latency=3
2
ea
5
CAS latency=2
1
CAS latency=1
-
0
VDDQ
1200
870
Output
30pF
V
O H
(DC) = 2.4V, I
O H
= -2mA
V
OL
(DC) = 0.4V, I
OL
= 2mA
Vtt = 0.5 x VDDQ
50
Output
30pF
Z0 = 50
(Fig. 2) AC output load circuit
(Fig. 1) DC output load circuit
AC OPERATING TEST CONDITIONS
(V
DD
= 2.7V ~ 3.6V, T
A
= Commercial, Extended and Industrial)
Parameter
Value
Unit
AC input levels (Vih/Vil)
2.4
/ 0.4
V
Input timing measurement reference level
0.5 x V
DDQ
V
Input rise and fall time
tr/tf = 1/1
ns
Output timing measurement reference level
0.5 x V
DDQ
V
Output load condition
See Fig. 2
K4S511533C-YL/N/P
Rev. 1.2 Dec. 2002
CMOS SDRAM
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Parameter
Symbol
-80
-1H
-1L
Unit
Note
Min
Max
Min
Max
Min
Max
CLK cycle time
CAS latency=3
t
C C
8
1000
10
1000
10
1000
ns
1
CAS latency=2
10
10
12
CAS latency=1
-
-
25
CLK to valid output delay
CAS latency=3
t
SAC
6
7
7
ns
1,2
CAS latency=2
7
7
8
CAS latency=1
-
-
20
Output data hold time
CAS latency=3
t
O H
2.5
2.5
2.5
ns
2
CAS latency=2
2.5
2.5
2.5
CAS latency=1
-
-
2.5
CLK high pulse width
t
C H
2.5
3
3
ns
3
CLK low pulse width
t
C L
2.5
3
3
ns
3
Input setup time
t
SS
2.0
2.5
2.5
ns
3
Input hold time
t
SH
1.0
1.5
1.5
ns
3
CLK to output in Low-Z
t
SLZ
1
1
1
ns
2
CLK to output in Hi-Z
CAS latency=3
t
SHZ
6
7
7
ns
CAS latency=2
7
7
8
CAS latency=1
-
-
20
Notes :
1. This is to advise Samsung customers that, in accordance with certain terms of an agreement, Samsung is prohibited from
selling any DRAM products configured in "Multi-Die Plastic" format for use as components in general and scientific computers,
such as mainframes, servers, work stations or desk top personal computers (hereinafter "Prohibited Computer Use").
Applications such as mobile, including cell phones, telecom, including televisions and display monitors, or non-desktop
computer systems, including laptops, notebook computers, are, however, permissible. "Multi-Die Plastic" is defined as two or
more DRAM die encapsulated within a single plastic leaded package.
2. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life
is potentially at stake. Please contact to the memory marketing team in samsung electronics when considering the use of
a product contained herein for any specific purpose, such as medical, aerospace, nuclear, military, vehicular or undersea
repeater use.
K4S511533C-YL/N/P
Rev. 1.2 Dec. 2002
CMOS SDRAM
SIMPLIFIED TRUTH TABLE
(V=Valid, X=Don
t Care, H=Logic High, L=Logic Low)
Notes :
1. OP Code : Operand Code
A
0
~ A
12
& BA
0
~ BA
1
: Program keys. (@MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are the same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA
0
~ BA
1
: Bank select addresses.
If both BA
0
and BA
1
are "Low" at read, write, row active and precharge, bank A is selected.
If BA
0
is "Low" and BA
1
is "High" at read, write, row active and precharge, bank B is selected.
If BA
0
is "High" and BA
1
is "Low" at read, write, row active and precharge, bank C is selected.
If both BA
0
and BA
1
are "High" at read, write, row active and precharge, bank D is selected.
If A
10
/AP is "High" at row precharge, BA
0
and BA
1
are ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t
RP
after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency
is 0), but in read operation it makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2).
COMMAND
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
BA
0,1
A
10
/AP
A
11,
A
12,
A
9
~ A
0
Note
Register
Mode Register Set
H
X
L
L
L
L
X
OP CODE
1, 2
Refresh
Auto Refresh
H
H
L
L
L
H
X
X
3
Self
Refresh
Entry
L
3
Exit
L
H
L
H
H
H
X
X
3
H
X
X
X
3
Bank Active & Row Addr.
H
X
L
L
H
H
X
V
Row Address
Read &
Column Address
Auto Precharge Disable
H
X
L
H
L
H
X
V
L
Column
Address
(A
0
~ A
8
)
4
Auto Precharge Enable
H
4, 5
Write &
Column Address
Auto Precharge Disable
H
X
L
H
L
L
X
V
L
Column
Address
(A
0
~ A
8
)
4
Auto Precharge Enable
H
4, 5
Burst Stop
H
X
L
H
H
L
X
X
6
Precharge
Bank Selection
H
X
L
L
H
L
X
V
L
X
All Banks
X
H
Clock Suspend or
Active Power Down
Entry
H
L
H
X
X
X
X
X
L
V
V
V
Exit
L
H
X
X
X
X
X
Precharge Power Down Mode
Entry
H
L
H
X
X
X
X
X
L
H
H
H
Exit
L
H
H
X
X
X
X
L
V
V
V
DQM
H
X
V
X
7
No Operation Command
H
X
H
X
X
X
X
X
L
H
H
H
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