K4S51163LF-Y(P)C_L_F-R10.fm
K4S51163LF-Y(P)C/L/F
September 2004
1
Mobile-SDRAM
VDD/VDDQ = 2.5V/2.5V or 2.5V/1.8V.
LVCMOS compatible with multiplexed address.
Four banks operation.
MRS cycle with address key programs.
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
EMRS cycle with address key programs.
All inputs are sampled at the positive going edge of the system
clock.
Burst read single-bit write operation.
Special Function Support.
-. PASR (Partial Array Self Refresh).
-. Internal TCSR (Temperature Compensated Self Refresh)
DQM for masking.
Auto refresh.
64ms refresh period (8K cycle).
Commercial Temperature Operation (-25
C ~ 70
C).
1 /CS Support.
2Chips DDP 54Balls FBGA ( -YXXX -Pb, -PXXX -Pb Free).
FEATURES
The K4S51163LF is 536,870,912 bits synchronous high data
rate Dynamic RAM organized as 4 x 8,388,608 words by 16 bits,
fabricated with SAMSUNG's high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock and I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length and programmable latencies allow the same device
to be useful for a variety of high bandwidth, high performance
memory system applications.
GENERAL DESCRIPTION
ORDERING INFORMATION
- Y(P)C/L/F : Normal / Low Power, Commercial Temperature(-25
C ~ 70
C)
NOTES :
1. In case of 40MHz Frequency, CL1 can be supported.
2. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake.
Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific pur
pose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.
Part No.
Max Freq.
Interface
Package
K4S51163LF-Y(P)C/L/F75
133MHz(CL3), 111MHz(CL2)
LVCMOS
54 FBGA Pb
(Pb Free)
K4S51163LF-Y(P)C/L/F1H
111MHz(CL2)
K4S51163LF-Y(P)C/L/F1L
111MHz(CL=3)*1, 83MHz(CL2)
8M x 16Bit x 4 Banks Mobile SDRAM
Address configuration
Organization
Bank
Row
Column Address
32M x16
BA0,BA1
A0 - A12
A0 - A9
K4S51163LF-Y(P)C/L/F
September 2004
2
Mobile-SDRAM
Bank Select
Data Input Register
8M x 16
8M x 16
Sense AMP
Output Buf
f
er
I/O Con
t
rol
Column Decoder
Latency & Burst Length
Programming Register
Addr
ess Re
gister
Ro
w
Bu
f
f
e
r
R
e
fresh Counte
r
Row Deco
der
C
ol.
Buf
f
er
LR
AS
LC
BR
LCKE
LRAS
LCBR
LWE
LDQM
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
LWE
LDQM
DQi
CLK
ADD
LCAS
LWCBR
8M x 16
8M x 16
Timing Register
FUNCTIONAL BLOCK DIAGRAM
K4S51163LF-Y(P)C/L/F
September 2004
3
Mobile-SDRAM
54Ball(6x9) FBGA
1
2
3
7
8
9
A
VSS
DQ15
VSSQ VDDQ
DQ0
VDD
B
DQ14
DQ13
VDDQ VSSQ
DQ2
DQ1
C
DQ12
DQ11
VSSQ VDDQ
DQ4
DQ3
D
DQ10
DQ9
VDDQ VSSQ
DQ6
DQ5
E
DQ8
NC
VSS
VDD
LDQM
DQ7
F
UDQM
CLK
CKE
CAS
RAS
WE
G
A12
A11
A9
BA0
BA1
CS
H
A8
A7
A6
A0
A1
A10
J
VSS
A5
A4
A3
A2
VDD
Pin Name
Pin Function
CLK
System Clock
CS
Chip Select
CKE
Clock Enable
A
0
~ A
12
Address
BA
0
~ BA
1
Bank Select Address
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
L(U)DQM
Data Input/Output Mask
DQ
0
~
15
Data Input/Output
V
DD
/V
SS
Power Supply/Ground
V
DDQ
/V
SSQ
Data Output Power/Ground
Symbol
Min
Typ
Max
A
1.00
1.10
1.20
A
1
0.27
0.32
0.37
E
-
11.5
-
E
1
-
6.40
-
D
-
10.0
-
D
1
-
6.40
-
e
-
0.80
-
b
0.45
0.50
0.55
z
-
-
0.10
[Unit:mm]
Package Dimension and Pin Configuration
< Top View
*2
>
< Bottom View
*1
>
#A1 Ball Origin Indicator
K4S51
163LF
SEC
We
e
k
XXXX
5
2
1
6
3
4
8
9
7
F
E
D
C
B
J
H
G
A
e
D
D/2
D
1
E
1
E
E/2
< Top View
*2
>
z
b
Substrate(2Layer)
A
A1
*2: Top View
*1: Bottom View
K4S51163LF-Y(P)C/L/F
September 2004
4
Mobile-SDRAM
ABSOLUTE MAXIMUM RATINGS
NOTES:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Parameter
Symbol
Value
Unit
Voltage on any pin relative to V
ss
V
IN
, V
OUT
-1.0 ~ 3.6
V
Voltage on V
DD
supply relative to V
ss
V
DD
, V
DDQ
-1.0 ~ 3.6
V
Storage temperature
T
STG
-55 ~ +150
C
Power dissipation
P
D
1.0
W
Short circuit current
I
OS
50
mA
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= -25 to 70
C)
NOTES :
1. Samsung can support VDDQ 2.5V(in general case) and 1.8V(in specific case) for VDD 2.5V products. Please contact to the
memory marketing team in Samsung Electronics when considering the use of VDDQ 1.8V(Min 1.65V).
2. VIH (max) = 3.0V AC.The overshoot voltage duration is
3ns.
3. VIL (min) = -1.0V AC. The undershoot voltage duration is
3ns.
4. Any input 0V
VIN
VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.
5. Dout is disabled, 0V
VOUT
VDDQ.
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply voltage
V
DD
2.3
2.5
2.7
V
V
DDQ
2.3
2.5
2.7
V
1.65
-
2.7
V
1
Input logic high voltage
V
IH
0.8 x V
DDQ
-
V
DDQ
+ 0.3
V
2
Input logic low voltage
V
IL
-0.3
0
0.3
V
3
Output logic high voltage
V
OH
V
DDQ
-0.2
-
-
V
I
OH
= -0.1mA
Output logic low voltage
V
OL
-
-
0.2
V
I
OL
= 0.1mA
Input leakage current
I
LI
-2
-
2
uA
4
CAPACITANCE
(V
DD
= 1.8V, T
A
= 23
C, f = 1MHz, V
REF
=0.9V
50 mV)
Pin
Symbol
Min
Max
Unit
Note
Clock
C
CLK
3.0
6.0
pF
RAS, CAS, WE, CS, CKE
C
IN
3.0
6.0
pF
DQM
C
IN
1.5
3.0
pF
Address
C
ADD
3.0
6.0
pF
DQ
0
~ DQ
15
C
OUT
3.0
5.0
pF
K4S51163LF-Y(P)C/L/F
September 2004
5
Mobile-SDRAM
DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= -25 to 70
C)
NOTES:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Internal TCSR can be supported(In commercial Temp : Max 40
C/Max 70
C).
4. K4S51163LF-Y(P)C**
5. K4S51163LF-Y(P)L**
6. K4S51163LF-Y(P)F**
7. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ).
Parameter
Symbol
Test Condition
Version
Unit
Note
-75
-1H
-1L
Operating Current
(One Bank Active)
I
CC1
Burst length = 1
t
RC
t
RC
(min)
I
O
= 0 mA
120
120
110
mA
1
Precharge Standby Current in
power-down mode
I
CC2
P
CKE
V
IL
(max), t
CC
= 10ns
1.0
mA
I
CC2
PS CKE & CLK
V
IL
(max), t
CC
=
1.0
Precharge Standby Current
in non power-down mode
I
CC2
N
CKE
V
IH
(min), CS
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
20
mA
I
CC2
NS
CKE
V
IH
(min), CLK
V
IL
(max), t
CC
=
Input signals are stable
10
Active Standby Current
in power-down mode
I
CC3
P
CKE
V
IL
(max), t
CC
= 10ns
8
mA
I
CC3
PS CKE & CLK
V
IL
(max), t
CC
=
4
Active Standby Current
in non power-down mode
(One Bank Active)
I
CC3
N
CKE
V
IH
(min), CS
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
45
mA
I
CC3
NS
CKE
V
IH
(min), CLK
V
IL
(max), t
CC
=
Input signals are stable
30
mA
Operating Current
(Burst Mode)
I
CC
4
I
O
= 0 mA
Page burst
4Banks Activated
t
CCD
= 2CLKs
170
150
150
mA
1
Refresh Current
I
CC
5
t
RC
t
RC
(min)
300
280
240
mA
2
Self Refresh Current
I
CC
6
CKE
0.2V
-C
1500
uA
4
-L
1200
5
-F
Internal TCSR
Max 40
Max 70
C
3
Full Array
900
1200
uA
6
1/2 of Full Array
800
900
1/4 of Full Array
700
800
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