K4S641633D-G
CMOS SDRAM
Rev. 0.1 Dec. 2000
4Mx16 SDRAM
Revision 0.1
December 2000
D-die, 3.0V, CSP
K4S641633D-G
CMOS SDRAM
Rev. 0.1 Dec. 2000
Revision History
Version 0.0(October. 2000. Preliminary)
First generation based on 64Mb D-die.
Version 0.1(Dec. 29. 2000)
Final Specification of 64Mb D-die
K4S641633D-G
CMOS SDRAM
Rev. 0.1 Dec. 2000
The K4S641633D is 67,108,864 bits synchronous high data
rate Dynamic RAM organized as 4x1,048,576 words by 16 bits,
fabricated with SAMSUNG
s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance mem-
ory system applications.
3.0V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS latency (2 & 3)
- Burst length (1, 2, 4, 8 & Full page)
- Burst type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system
clock
Burst read single-bit write operation
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
Available in CSP
GENERAL DESCRIPTION
FEATURES
FUNCTIONAL BLOCK DIAGRAM
1M x 16Bit x 4 Banks Synchronous DRAM with CSP
Samsung Electronics reserves the right to
change products or specification without
notice.
*
Bank Select
Data Input Register
1M x 16
1M x 16
S
e
n
s
e
A
M
P
O
u
t
p
u
t
B
u
f
f
e
r
I
/
O
C
o
n
t
r
o
l
Column Decoder
Latency & Burst Length
Programming Register
A
d
d
r
e
s
s
R
e
g
i
s
t
e
r
R
o
w
B
u
f
f
e
r
R
e
f
r
e
s
h
C
o
u
n
t
e
r
R
o
w
D
e
c
o
d
e
r
C
o
l
.
B
u
f
f
e
r
L
R
A
S
L
C
B
R
LCKE
LRAS
LCBR
LWE
LDQM
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
LWE
LDQM
DQi
CLK
ADD
LCAS
LWCBR
1M x 16
1M x 16
Timing Register
ORDERING INFORMATION
Part No.
Max Freq.
Temp.
Interface
K4S641633D-GC/L1H
100MHz(CL=2) Commer-
cial
LVTTL
K4S641633D-GC/L1L
100MHz(CL=3)
K4S641633D-GE/N1H
100MHz(CL=2)
Extended
K4S641633D-GE/N1L
100MHz(CL=3)
K4S641633D-G
CMOS SDRAM
Rev. 0.1 Dec. 2000
F
E
D
C
B
N
L
J
H
G
52Ball(4x13) CSP
1
2
5
6
A
Vss
DQ15
DQ0
V
DD
B
DQ14
V
SSQ
V
DDQ
DQ1
C
DQ13
V
DDQ
V
SSQ
DQ2
D
DQ12
DQ11
DQ4
DQ3
E
DQ10
V
SSQ
V
DDQ
DQ5
F
DQ9
V
DDQ
V
SSQ
DQ6
G
DQ8
V
DD
Vss
DQ7
H
CLK
UDQM
LDQM
WE
J
CKE
CS
RAS
CAS
K
A11
A9
BA1
BA0
L
A8
A7
A0
A10
M
A6
A5
A2
A1
N
Vss
A4
A3
V
DD
Pin Name
Pin Function
CLK
System Clock
CS
Chip Select
CKE
Clock Enable
A
0
~ A
11
Address
BA
0
~ BA
1
Bank Select Address
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
L(U)DQM
Data Input/Output Mask
D Q
0
~
15
Data Input/Output
V
DD
/V
SS
Power Supply/Ground
V
DDQ
/V
SSQ
Data Output Power/Ground
A
Package Dimension and Pin Configuration
M
K
< Bottom View
*1
>
E
1
5
2
1
6
3
4
e
D
1
D
D
/
2
E
E/2
#A1 Ball Origin Indicator
S
A
M
S
U
N
G
< Top View
*2
>
< Top View
*2
>
W
E
E
K
A
A1
b
*1: Bottom View
*2: Top View
Symbol
Min
Typ
Max
A
1.00
1.05
1.10
A
1
-
0.35
-
E
-
6.60
-
E
1
-
3.75
-
D
-
11.00
-
D
1
-
9.0
-
e
-
0.75
-
b
0.40
0.45
0.5
-
-
0.08
[Unit:mm]
Max. 0.20
Encapsulant
K
4
S
6
4
1
6
3
3
D
-
G
K4S641633D-G
CMOS SDRAM
Rev. 0.1 Dec. 2000
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
V
I N
, V
OUT
-1.0 ~ 3.3
V
Voltage on V
DD
supply relative to Vss
V
DD
, V
DDQ
-1.0 ~ 3.3
V
Storage temperature
T
STG
-55 ~ +150
C
Power dissipation
P
D
1
W
Short circuit current
I
OS
50
mA
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Note :
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, Commercial : T
A
= 0 to 70
C, Extended : T
A
= -25 to 85
C )
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply voltage
V
D D
, V
DDQ
2.7
3.0
3.3
V
Input logic high votlage
V
I H
2.0
3.0
V
DDQ
+0.3
V
1
Input logic low voltage
V
IL
-0.3
0
0.8
V
2
Output logic high voltage
V
O H
2.4
-
-
V
I
O H
= -2mA
Output logic low voltage
V
OL
-
-
0.4
V
I
OL
= 2mA
Input leakage current(Inputs)
I
IL
-5
-
5
uA
3
Input leakage current (I/O pins)
I
IL
-5
-
5
uA
3,4
CAPACITANCE
(V
D D
= 3.0V, T
A
= 23
C, f = 1MHz, V
REF
=1.4V + 200
mV)
Pin
Symbol
Min
Max
Unit
Clock
C
CLK
2.0
3.5
pF
RAS, CAS, WE, CS, CKE, L(U)DQM
C
IN
2.0
4.5
pF
Address
C
ADD
2.0
4.5
pF
D Q
0
~ DQ
15
C
OUT
3.5
6.0
pF
1. V
IH
(max) = 5.3V AC. The overshoot voltage duration is
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
3ns.
3. Any input 0V
V
IN
V
DDQ
.
Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Dout is disabled, 0V
V
OUT
V
DDQ.
Note
:
K4S641633D-G
CMOS SDRAM
Rev. 0.1 Dec. 2000
1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S641633D-GC(E)**
4. K4S641633D-GL(N)**
Notes :
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, Commercial : T
A
= 0 to 70
C, Extended : T
A
= -25 to 85
C )
Parameter
Symbol
Test Condition
CAS
Latency
Version
Unit
Note
-1H
-1L
Operating current
(One bank active)
I
C C 1
Burst length = 1
t
RC
t
R C
(min)
I
OL
= 0 mA
70
70
mA
1
Precharge standby current in
power-down mode
I
CC2
P
CKE
V
IL
(max), t
CC
= 15ns
1
mA
I
CC2
PS CKE & CLK
V
IL
(max), t
CC
=
1
Precharge standby current in
non power-down mode
I
C C 2
N
CKE
V
IH
(min), CS
V
IH
(min), t
CC
= 15ns
Input signals are changed one time during 30ns
12
mA
I
CC2
NS
CKE
V
IH
(min), CLK
V
IL
(max), t
CC
=
Input signals are stable
6
Active standby current in
power-down mode
I
CC3
P
CKE
V
IL
(max), t
CC
= 15ns
2
mA
I
CC3
PS CKE & CLK
V
IL
(max), t
CC
=
2
Active standby current in
non power-down mode
(One bank active)
I
C C 3
N
CKE
V
IH
(min), CS
V
IH
(min), t
CC
= 15ns
Input signals are changed one time during 30ns
20
mA
I
CC3
NS
CKE
V
IH
(min), CLK
V
IL
(max), t
CC
=
Input signals are stable
10
mA
Operating current
(Burst mode)
I
C C 4
I
OL
= 0 mA
Page burst
2Banks activated
t
C C D
= 2CLKs
3
90
90
mA
1
2
90
85
Refresh current
I
C C 5
t
RC
t
R C
(min)
125
mA
2
Self refresh current
I
C C 6
CKE
0.2V
1
mA
3
400
uA
4
K4S641633D-G
CMOS SDRAM
Rev. 0.1 Dec. 2000
AC OPERATING TEST CONDITIONS
(V
DD
= 3.3V
0.3V, Commercial : T
A
= 0 to 70
C, Extended : T
A
= -25 to 85
C)
Parameter
Value
Unit
AC input levels (Vih/Vil)
2.4/0.4
V
Input timing measurement reference level
1.4
V
Input rise and fall time
tr/tf = 1/1
ns
Output timing measurement reference level
1.4
V
Output load condition
See Fig. 2
3.3V
1200
870
Output
50pF
V
OH
(DC) = 2.4V, I
OH
= -2mA
V
OL
(DC) = 0.4V, I
OL
= 2mA
Vtt = 1.4V
50
Output
50pF
Z0 = 50
(Fig. 2) AC output load circuit
(Fig. 1) DC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Version
Unit
Note
-1H
-1L
Row active to row active delay
t
R R D
(min)
20
20
ns
RAS to CAS delay
t
R C D
(min)
20
20
ns
Row precharge time
t
R P
(min)
20
20
ns
Row active time
t
RAS
(min)
50
50
ns
t
RAS
(max)
100
us
Row cycle time
t
R C
(min)
70
70
ns
Last data in to row precharge
t
RDL
(min)
10
10
ns
1
Last data in to new col. address Delay
t
CDL
(min)
1
CLK
1
Last data in to burst stop
t
BDL
(min)
1
CLK
1
Col. address to col. address delay
t
C C D
(min)
1
CLK
2
Number of valid output data
CAS latency=3
2
ea
3
CAS latency=2
1
1. Minimum delay is required to complete write.
2. All parts allow every cycle column address change.
3. In case of row precharge interrupt, auto precharge and read burst stop.
Notes :
K4S641633D-G
CMOS SDRAM
Rev. 0.1 Dec. 2000
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Notes :
DQ BUFFER OUTPUT DRIVE CHARACTERISTICS
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Notes
Output rise time
trh
Measure in linear
region : 1.2V ~ 1.8V
1.37
4.37
Volts/ns
3
Output fall time
tfh
Measure in linear
region : 1.2V ~ 1.8V
1.30
3.8
Volts/ns
3
Output rise time
trh
Measure in linear
region : 1.2V ~ 1.8V
2.8
3.9
5.6
Volts/ns
1,2
Output fall time
tfh
Measure in linear
region : 1.2V ~ 1.8V
2.0
2.9
5.0
Volts/ns
1,2
1. Rise time specification based on 0pF + 50
to V
SS
, use these values to design to.
2. Fall time specification based on 0pF + 50
to V
DD
, use these values to design to.
3. Measured into 50pF only, use these values to characterize to.
4. All measurements done with respect to V
SS
.
Notes :
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
Parameter
Symbol
-1H
-1L
Unit
Note
Min
Max
Min
Max
CLK cycle time
CAS latency=3
t
C C
10
1000
10
1000
ns
1
CAS latency=2
10
12
CLK to valid
output delay
CAS latency=3
t
SAC
6
6
ns
1,2
CAS latency=2
6
7
Output data
hold time
CAS latency=3
t
O H
3
3
ns
2
CAS latency=2
3
3
CLK high pulse width
t
C H
3
3
ns
3
CLK low pulse width
t
CL
3
3
ns
3
Input setup time
t
SS
2
2
ns
3
Input hold time
t
SH
1
1
ns
3
CLK to output in Low-Z
t
SLZ
1
1
ns
2
CLK to output
in Hi-Z
CAS latency=3
t
SHZ
6
6
ns
CAS latency=2
6
7
K4S641633D-G
CMOS SDRAM
Rev. 0.1 Dec. 2000
SIMPLIFIED TRUTH TABLE
(V=Valid, X=Don
t care, H=Logic high, L=Logic low)
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
BA
0,1
A
10
/AP
A
11,
A
9
~ A
0
Note
Register
Mode register set
H
X
L
L
L
L
X
OP code
1,2
Refresh
Auto refresh
H
H
L
L
L
H
X
X
3
Self
refresh
Entry
L
3
Exit
L
H
L
H
H
H
X
X
3
H
X
X
X
3
Bank active & row addr.
H
X
L
L
H
H
X
V
Row address
Read &
column address
Auto precharge disable
H
X
L
H
L
H
X
V
L
Column
address
(A
0
~ A
7
)
4
Auto precharge enable
H
4,5
Write &
column address
Auto precharge disable
H
X
L
H
L
L
X
V
L
Column
address
(A
0
~ A
7
)
4
Auto precharge enable
H
4,5
Burst stop
H
X
L
H
H
L
X
X
6
Precharge
Bank selection
H
X
L
L
H
L
X
V
L
X
All banks
X
H
Clock suspend or
active power down
Entry
H
L
H
X
X
X
X
X
L
V
V
V
Exit
L
H
X
X
X
X
X
Precharge power down mode
Entry
H
L
H
X
X
X
X
X
L
H
H
H
Exit
L
H
H
X
X
X
X
L
V
V
V
DQM
H
V
X
7
No operation command
H
X
H
X
X
X
X
X
L
H
H
H
1. OP Code : Operand code
A
0
~ A
11
& BA
0
~ BA
1
: Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA
0
~ BA
1
: Bank select addresses.
If both BA
0
and BA
1
are "Low" at read, write, row active and precharge, bank A is selected.
If both BA
0
is "Low" and BA
1
is "High" at read, write, row active and precharge, bank B is selected.
If both BA
0
is "High" and BA
1
is "Low" at read, write, row active and precharge, bank C is selected.
If both BA
0
and BA
1
are "High" at read, write, row active and precharge, bank D is selected.
If A
10
/AP is "High" at row precharge, BA
0
and BA
1
is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t
RP
after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Notes :
X
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