CMOS SDRAM

- 2 -

SDRAM 64Mb H-die (x32)

Rev. 1.4 August 2004

Revision 0.0 (June, 2003)

- Target spec First release.

Revision 0.1 (July, 2003)

- Delete speed 4.5ns.

Revision 0.2 (September, 2003)

- Preliminary spec release.

Revision 1.0 (November, 2003)

- Final spec release

Revision 1.1 (December, 2003)

- Corrected typo

Revision 1.2 (December, 2003)

- Modified load cap 50pF -> 30pF & Typo

Revision 1.3 (February, 2004)

- Corrected typo.

Revision 1.4 (August, 2004)

- Corrected typo.

Revision History

CMOS SDRAM

- 3 -

SDRAM 64Mb H-die (x32)

Rev. 1.4 August 2004

The K4S643232H is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits, fabricated
with SAMSUNG

s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock.

I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable
latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

512K x 32Bit x 4 Banks SDRAM

· JEDEC standard 3.3V power supply
· LVTTL compatible with multiplexed address
· Four banks operation
· MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
· All inputs are sampled at the positive going edge of the system clock.
· Burst read single-bit write operation
· DQM for masking
· Auto & self refresh
· 64ms refresh period(4K Cycle)

FEATURES

GENERAL DESCRIPTION

Part No.

Orgainization

Max Freq.

Interface

Package

K4S643232H-TC/L70

2Mb x 32

143MHz(CL=3)

LVTTL

86pin TSOP(II)

K4S643232H-TC/L60

166MHz(CL=3)

K4S643232H-TC/L55

183MHz(CL=3)

K4S643232H-TC/L50

200MHz(CL=3)

Ordering Information

Row & Column address configuration

Organization

Row Address

Column Address

2Mx32

A0~A10

A0-A7

CMOS SDRAM

- 4 -

SDRAM 64Mb H-die (x32)

Rev. 1.4 August 2004

0.002

0.05

MIN

0.008

0.21

0.002

0.05

2
0

(

)

0.005

-0.001

+0.003

0.125

-0.035

+0.075

.
1
6

5
~

0
.
7
5

.
01

3
0

0.010

0.25

TYP

0~8

0.004

0.10

MAX

0.024

0.61

( )

0.0079

0.20

0.0197

0.50

0.047

1.20

MAX

0.039

1.00

0.004

0.10

0.891

22.62

MAX

0.875

22.22

0.004

0.10

+0.07

-0.03

0.003

-0.001

86Pin TSOP(II) Package Dimension

Package Physical Dimension

.
7
6

0.20

0.008

#86

#44

#43

CMOS SDRAM

- 6 -

SDRAM 64Mb H-die (x32)

Rev. 1.4 August 2004

PIN CONFIGURATION (Top view)

DQ0

DDQ

DQ1
DQ2

SSQ

DQ3
DQ4

DDQ

DQ5
DQ6

SSQ

DQ7

N.C

DQM0

CAS
RAS

N.C

BA0
BA1

A10/AP

A0
A1
A2

DQM2

N.C

DQ16

SSQ

DQ17
DQ18

DDQ

DQ19
DQ20

SSQ

DQ21
DQ22

DDQ

DQ23

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43

86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

DQ15
V

SSQ

DQ14
DQ13
V

DDQ

DQ12
DQ11
V

SSQ

DQ10
DQ9
V

DDQ

DQ8
N.C
V

DQM1
N.C
N.C
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
V

N.C
DQ31
V

DDQ

DQ30
DQ29
V

SSQ

DQ28
DQ27
V

DDQ

DQ26
DQ25
V

SSQ

DQ24
V

86Pin TSOP (II)

(400mil x 875mil)

(0.5 mm Pin pitch)

CMOS SDRAM

- 7 -

SDRAM 64Mb H-die (x32)

Rev. 1.4 August 2004

PIN FUNCTION DESCRIPTION

Pin

Name

Input Function

CLK

System clock

Active on the positive going edge to sample all inputs.

Chip select

Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM.

CKE

Clock enable

Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disables input buffers for power down mode.

~ A

Address

Row/column addresses are multiplexed on the same pins.
Row address : RA

~ RA

, Column address : CA

~ CA

BA0,1

Bank select address

Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.

RAS

Row address strobe

Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.

CAS

Column address strobe

Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.

Write enable

Enables write operation and row precharge.
Latches data in starting from CAS, WE active.

DQM0 ~ 3

Data input/output mask

Makes data output Hi-Z, t

SHZ

after the clock and masks the output.

Blocks data input when DQM active.

Data input/output

Data inputs/outputs are multiplexed on the same pins.

Power supply/ground

Power and ground for the input buffers and the core logic.

DDQ

SSQ

Data output power/ground

Isolated power supply and ground for the output buffers to provide improved noise
immunity.

No Connection

This pin is recommended to be left No connection on the device.

CMOS SDRAM

- 8 -

SDRAM 64Mb H-die (x32)

Rev. 1.4 August 2004

DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to V

= 0V, T

= 0 to 70

Parameter

Symbol

Min

Typ

Max

Unit

Note

Supply voltage

, V

DDQ

3.0

3.3

3.6

Input logic high voltage

2.0

3.0

DDQ

+0.3

Input logic low voltage

-0.3

0.8

Output logic high voltage

2.4

= -2mA

Output logic low voltage

0.4

= 2mA

Input leakage current

-10

1. V

(max) = 5.6V AC.The overshoot voltage duration is

3ns.

2. V

(min) = -2.0V AC. The undershoot voltage duration is

3ns.

3. Any input 0V

DDQ

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

Notes :

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Value

Unit

Voltage on any pin relative to Vss

, V

OUT

-1.0 ~ 4.6

Voltage on V

supply relative to Vss

, V

DDQ

-1.0 ~ 4.6

Storage temperature

STG

-55 ~ +150

Power dissipation

Short circuit current

Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Note :

CAPACITANCE

= 3.3V, T

= 23

C, f = 1MHz, V

REF

= 1.4V

200

mV)

Pin

Symbol

Min

Max

Unit

Clock

CLK

RAS, CAS, WE, CS, CKE, DQM

4.5

Address

ADD

4.5

~ DQ

OUT

6.5

CMOS SDRAM

- 9 -

SDRAM 64Mb H-die (x32)

Rev. 1.4 August 2004

(Recommended operating condition unless otherwise noted, T

= 0 to 70

Parameter

Symbol

Test Condition

CAS

Latency

Speed

Unit

Note

Operating Current
(One Bank Active)

CC1

Burst Length =1

(min), t

(min), I

= 0mA

140

130

110

Precharge Standby Current in
power-down mode

CC2

CKE

(max), t

= 10ns

CC2

CKE

CLK

(max), t

Precharge Standby Current
in non power-down mode

CC2

CKE

(min), CS

(min), t

= 10ns

Input signals are changed one time during 30ns

CC2

CKE

(min), CLK

(max), t

Input signals are stable

Active Standby Current
in power-down mode

CC3

CKE

(max), t

= 10ns

CC3

CKE

(max), t

Active Standby Current
in non power-down mode
(One Bank Active)

CC3

CKE

(min), CS

(min), t

= 10ns

Input signals are changed one time during 30ns

CC3

CKE

(min), CLK

(max), t

Input signals are stable

Operating Current
(Burst Mode)

CC4

= 0 mA, Page Burst

All bank Activated, t

CCD

= t

CCD

(min)

170

160

150

140

120

Refresh Current

CC5

(min)

150

140

120

Self Refresh Current

CC6

CKE

0.2V

450

DC CHARACTERISTICS

1. Unless otherwise notes, Input level is CMOS(V

DDQ

SSQ

) in LVTTL.

2. Measured with outputs open.
3. Refresh period is 64ms.
4. K4S643232H-TC
5. K4S643232H-TL

Notes :

CMOS SDRAM

- 10

SDRAM 64Mb H-die (x32)

Rev. 1.4 August 2004

AC OPERATING TEST CONDITIONS

= 3.3V

0.3V, T

= 0 to 70

Parameter

Value

Unit

AC input levels (Vih/Vil)

2.4/0.4

Input timing measurement reference level

1.4

Input rise and fall time

tr/tf = 1/1

Output timing measurement reference level

1.4

Output load condition

See Fig. 2

3.3V

1200

870

Output

30pF

(DC) = 2.4V, I

= -2mA

(DC) = 0.4V, I

= 2mA

Vtt = 1.4V

Output

30pF

Z0 = 50

(Fig. 2) AC output load circuit

(Fig. 1) DC output load circuit

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer. Refer to the following ns-unit based AC table.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.

Note :

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Parameter

Symbol

Unit

Note

Min

Max

Min

Max

Min

Max

Min

Max

CLK cycle time

CAS

1000

5.5

1000

CAS

Row active to row active delay

RRD(min)

CLK

RAS to CAS delay

RCD(min)

CLK

Row precharge time

RP(min)

CLK

Row active time

RAS(min)

CLK

RAS(max)

100

Row cycle time

(

min

)

CLK

Last data in to row precharge

RDL(min)

CLK

Last data in to new col.address delay

CDL(min)

CLK

Last data in to burst stop

BDL(min)

CLK

Col. address to col. address delay

CCD(min)

CLK

Mode Register Set cycle time

MRS(min)

CLK

Number of valid
output data

CAS Latency=3

CAS Latency=2

CMOS SDRAM

- 11

SDRAM 64Mb H-die (x32)

Rev. 1.4 August 2004

1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.

Note :

AC CHARACTERISTICS

(AC operating conditions unless otherwise noted)

Parameter

Symbol

Unit

Note

Min

Max

Min

Max

Min

Max

Min

Max

CLK cycle time

CAS Latency=3

1000

5.5

1000

CAS Latency=2

CLK to valid
output delay

CAS Latency=3

SAC

4.5

5.0

5.5

1, 2

CAS Latency=2

Output data hold time

CLK high pulse
width

CAS Latency=3

2.5

CAS Latency=2

CLK low
pulse width

CAS Latency=3

2.5

CAS Latency=2

Input setup time

CAS Latency=3

1.5

1.75

CAS Latency=2

2.5

Input hold time

CLK to output in Low-Z

SLZ

CLK to output
in Hi-Z

CAS latency=3

SHZ

4.5

5.0

5.5

CAS latency=2

CMOS SDRAM

- 12

SDRAM 64Mb H-die (x32)

Rev. 1.4 August 2004

SIMPLIFIED TRUTH TABLE

(V=Valid, X=Don

t care, H=Logic high, L=Logic low)

Command

CKEn-1

CKEn

RAS

CAS

DQM

0,1

/AP

11,

~ A

Note

Mode register set

OP code

1,2

Refresh

Auto refresh

Self
refresh

Entry

Exit

Bank active & row addr.

Row address

Read &
column address

Auto precharge disable

Column

address

Auto precharge enable

4,5

Write &
column address

Auto precharge disable

Column

address

Auto precharge enable

4,5

Burst Stop

Precharge

Bank selection

All banks

Clock suspend or
active power down

Entry

Exit

Precharge power down mode

Entry

Exit

DQM

No operation command

1. OP Code : Operand code
A

~ A

& BA

~ BA

: Program keys. (@ MRS)

2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA

~ BA

: Bank select addresses.

If both BA

and BA

are "Low" at read, write, row active and precharge, bank A is selected.

If both BA

is "Low" and BA

is "High" at read, write, row active and precharge, bank B is selected.

If both BA

is "High" and BA

is "Low" at read, write, row active and precharge, bank C is selected.

If both BA

and BA

are "High" at read, write, row active and precharge, bank D is selected.

If A

/AP is "High" at row precharge, BA

and BA

is ignored and all banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t

after the end of burst.

6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

Notes :

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