CMOS SDRAM

- 3 -

Preliminary

SDRAM 64Mb H-die (x32)

Rev. 0.2 Septermber. 2003

The K4S643232H is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits, fabricated
with SAMSUNG

s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock.

I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable
latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

512K x 32Bit x 4 Banks

· JEDEC standard 3.3V power supply
· LVTTL compatible with multiplexed address
· Four banks operation
· MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
· All inputs are sampled at the positive going edge of the system clock.
· Burst read single-bit write operation
· DQM (x4,x8) & L(U)DQM (x16) for masking
· Auto & self refresh
· 15.6us refresh duty cycle

FEATURES

GENERAL DESCRIPTION

Part No.

Orgainization

Max Freq.

Interface

Package

K4S643232H-TC/L70

512K x 32

143MHz

LVTTL

86pin TSOP

K4S643232H-TC/L60

512K x 32

166MHz

LVTTL

86pin TSOP

K4S643232H-TC/L55

512K x 32

183MHz

LVTTL

86pin TSOP

K4S643232H-TC/L50

512K x 32

200MHz

LVTTL

86pin TSOP

Ordering Information

Row & Column address configuration

Organization

Row Address

Column Address

1Mx32

A0~A10

A0-A7

CMOS SDRAM

- 7 -

Preliminary

SDRAM 64Mb H-die (x32)

Rev. 0.2 Septermber. 2003

PIN FUNCTION DESCRIPTION

Pin

Name

Input Function

CLK

System clock

Active on the positive going edge to sample all inputs.

Chip select

Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM.

CKE

Clock enable

Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disables input buffers for power down mode.

~ A

Address

Row/column addresses are multiplexed on the same pins.
Row address : RA

~ RA

, Column address : CA

~ CA

BA0,1

Bank select address

Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.

RAS

Row address strobe

Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.

CAS

Column address strobe

Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.

Write enable

Enables write operation and row precharge.
Latches data in starting from CAS, WE active.

DQM0 ~ 3

Data input/output mask

Makes data output Hi-Z, t

SHZ

after the clock and masks the output.

Blocks data input when DQM active.

Data input/output

Data inputs/outputs are multiplexed on the same pins.

Power supply/ground

Power and ground for the input buffers and the core logic.

DDQ

SSQ

Data output power/ground

Isolated power supply and ground for the output buffers to provide improved noise
immunity.

No Connection

This pin is recommended to be left No connection on the device.

CMOS SDRAM

- 8 -

Preliminary

SDRAM 64Mb H-die (x32)

Rev. 0.2 Septermber. 2003

DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to V

= 0V, T

= 0 to 70

Parameter

Symbol

Min

Typ

Max

Unit

Note

Supply voltage

, V

DDQ

3.0

3.3

3.6

Input logic high voltage

2.0

3.0

DDQ

+0.3

Input logic low voltage

-0.3

0.8

Output logic high voltage

2.4

= -2mA

Output logic low voltage

0.4

= 2mA

Input leakage current

-10

1. V

(max) = 5.6V AC.The overshoot voltage duration is

3ns.

2. V

(min) = -2.0V AC. The undershoot voltage duration is

3ns.

3. Any input 0V

DDQ

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

Notes :

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Value

Unit

Voltage on any pin relative to Vss

, V

OUT

-1.0 ~ 4.6

Voltage on V

supply relative to Vss

, V

DDQ

-1.0 ~ 4.6

Storage temperature

STG

-55 ~ +150

Power dissipation

Short circuit current

Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Note :

CAPACITANCE

= 3.3V, T

= 23

C, f = 1MHz, V

REF

= 1.4V

200

mV)

Pin

Symbol

Min

Max

Unit

Clock

CLK

RAS, CAS, WE, CS, CKE, DQM

4.5

Address

ADD

4.5

~ DQ

OUT

6.5

CMOS SDRAM

- 9 -

Preliminary

SDRAM 64Mb H-die (x32)

Rev. 0.2 Septermber. 2003

(Recommended operating condition unless otherwise noted, T

= 0 to 70

C, V

IH(min)

IL(max)

=2.0V/0.8V)

Parameter

Symbol

Test Condition

CAS

Latency

Speed

Unit

Note

-50

-55

-60

-70

Operating Current
(One Bank Active)

CC1

Burst Length =1

(min), t

(min), I

= 0mA

140

130

110

Precharge Standby Current in
power-down mode

CC2

CKE

(max), t

= 15ns

CC2

CKE

CLK

(max), t

Precharge Standby Current
in non power-down mode

CC2

CKE

(min), CS

(min), t

= 15ns

Input signals are changed one time during 30ns

CC2

CKE

(min), CLK

(max), t

Input signals are stable

Active Standby Current
in power-down mode

CC3

CKE

(max), t

= 15ns

CC3

CKE

(max), t

Active Standby Current
in non power-down mode
(One Bank Active)

CC3

CKE

(min), CS

(min), t

= 15ns

Input signals are changed one time during 30ns

CC3

CKE

(min), CLK

(max), t

Input signals are stable

Operating Current
(Burst Mode)

CC4

= 0 mA, Page Burst

All bank Activated, t

CCD

= t

CCD

(min)

170

160

150

140

120

Refresh Current

CC5

(min)

150

140

120

Self Refresh Current

CC6

CKE

0.2V

450

DC CHARACTERISTICS

1. Unless otherwise notes, Input level is CMOS(V

DDQ

SSQ

) in LVTTL.

2. Measured with outputs open.
3. Refresh period is 64ms.
4. K4S643232H-TC
5. K4S643232H-TL

Notes :

CMOS SDRAM

- 10

Preliminary

SDRAM 64Mb H-die (x32)

Rev. 0.2 Septermber. 2003

AC OPERATING TEST CONDITIONS

= 3.3V

0.3V, T

= 0 to 70

Parameter

Value

Unit

AC input levels (Vih/Vil)

2.4/0.4

Input timing measurement reference level

1.4

Input rise and fall time

tr/tf = 1/1

Output timing measurement reference level

1.4

Output load condition

See Fig. 2

3.3V

1200

870

Output

50pF

(DC) = 2.4V, I

= -2mA

(DC) = 0.4V, I

= 2mA

Vtt = 1.4V

Output

50pF

Z0 = 50

(Fig. 2) AC output load circuit

(Fig. 1) DC output load circuit

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer. Refer to the following ns-unit based AC table.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.

Note :

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Parameter

Symbol

Version

Unit

Note

-50

-55

-60

-70

Row active to row active delay

RRD(min)

CLK

RAS to CAS delay

RCD(min)

CLK

Row precharge time

RP(min)

CLK

Row active time

RAS(min)

CLK

RAS(max)

100

Row cycle time

(

min

)

CLK

Last data in to row precharge

RDL(min)

CLK

Last data in to new col.address delay

CDL(min)

CLK

Last data in to burst stop

BDL(min)

CLK

Col. address to col. address delay

CCD(min)

CLK

Mode Register Set cycle time

MRS(min)

CLK

Number of valid
output data

CAS Latency=3

CAS Latency=2

CMOS SDRAM

- 11

Preliminary

SDRAM 64Mb H-die (x32)

Rev. 0.2 Septermber. 2003

1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.

Note :

AC CHARACTERISTICS

(AC operating conditions unless otherwise noted)

Parameter

Symbol

-50

-55

-60

-70

Unit

Note

Min

Max

Min

Max

Min

Max

Min

Max

CLK cycle time

CAS Latency=3

1000

5.5

1000

CAS Latency=2

CLK to valid
output delay

CAS Latency=3

SAC

4.5

5.0

5.5

1, 2

CAS Latency=2

Output data hold time

CLK high pulse
width

CAS Latency=3

2.5

CAS Latency=2

CLK low
pulse width

CAS Latency=3

2.5

CAS Latency=2

Input setup time

CAS Latency=3

1.5

1.75

CAS Latency=2

2.5

Input hold time

CLK to output in Low-Z

SLZ

CLK to output
in Hi-Z

CAS latency=3

SHZ

4.5

5.0

5.5

CAS latency=2

CMOS SDRAM

- 12

Preliminary

SDRAM 64Mb H-die (x32)

Rev. 0.2 Septermber. 2003

SIMPLIFIED TRUTH TABLE

(V=Valid, X=Don

t care, H=Logic high, L=Logic low)

Command

CKEn-1

CKEn

RAS

CAS

DQM

0,1

/AP

~ A

Note

Mode register set

OP code

1,2

Refresh

Auto refresh

Self
refresh

Entry

Exit

Bank active & row addr.

Row address

Read &
column address

Auto precharge disable

Column

address

~ A

)

Auto precharge enable

4,5

Write &
column address

Auto precharge disable

Column

address

~ A

)

Auto precharge enable

4,5

Burst Stop

Precharge

Bank selection

All banks

Clock suspend or
active power down

Entry

Exit

Precharge power down mode

Entry

Exit

DQM

No operation command

1. OP Code : Operand code
A

~ A

& BA

~ BA

: Program keys. (@ MRS)

2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA

~ BA

: Bank select addresses.

If both BA

and BA

are "Low" at read, write, row active and precharge, bank A is selected.

If both BA

is "Low" and BA

is "High" at read, write, row active and precharge, bank B is selected.

If both BA

is "High" and BA

is "Low" at read, write, row active and precharge, bank C is selected.

If both BA

and BA

are "High" at read, write, row active and precharge, bank D is selected.

If A

/AP is "High" at row precharge, BA

and BA

is ignored and all banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t

after the end of burst.

6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

Notes :

CMOS SDRAM

- 13

Preliminary

SDRAM 64Mb H-die (x32)

Rev. 0.2 Septermber. 2003

MODE REGISTER FIELD TABLE TO PROGRAM MODES

Address
Function

/AP

RFU

W.B.L

CAS Latency

Burst Length

BT = 0

Test Mode

Type

Mode Register Set

Reserved
Reserved
Reserved

0
0
1
1

0
1
0
1

Write Burst Length

0
1

Length

Burst

Single Bit

Latency

Reserved
Reserved

2
3

Reserved
Reserved
Reserved
Reserved

CAS Latency

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Burst Type

0
1

BT = 1

Burst Length

Type

Sequential

Interleave

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

1
2
4
8

Reserved
Reserved
Reserved
Full Page

1
2
4
8

Reserved
Reserved
Reserved
Reserved

POWER UP SEQUENCE

SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

1. Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 is regardless of the order.

The device is now ready for normal operation.

Note : 1. If A

is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.

2. RFU (Reserved for future use) should stay "0" during MRS cycle.

Full Page Length : x32 (256)

~ BA

RFU

- 15

Device Operation &

x32 SDRAM

Timing Diagram

Rev. 0.1 July. 2003

DEVICE OPERATIONS

NOP and DEVICE DESELECT

When RAS, CAS and WE are high, the SDRAM performs no
operation (NOP). NOP does not initiate any new operation, but
is needed to complete operations which require more than sin-
gle clock cycle like bank activate, burst read, auto refresh, etc.
The device deselect is also a NOP and is entered by asserting
CS high. CS high disables the command decoder so that RAS,
CAS, WE and all the address inputs are ignored.

POWER-UP

SDRAMs must be powered up and initialized in a pre-
defined manner to prevent undefined operations.

1. Apply power and start clock. Must maintain CKE= "H", DQM=
"H" and the other pins are NOP condition at the inputs.
2. Maintain stable power, stable clock and NOP input condition
for a minimum of 200us.
3. Issue precharge commands for both banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode reg-
ister.
cf.) Sequence of 4 & 5 is regardless of the order.

The device is now ready for normal operation.

CLOCK (CLK)

The clock input is used as the reference for all SDRAM opera-
tions. All operations are synchronized to the positive going edge
of the clock. The clock transitions must be monotonic between
V

and V

. During operation with CKE high all inputs are

assumed to be in a valid state (low or high) for the duration of
set-up and hold time around positive edge of the clock in order
to function well Q perform and I

specifications.

CLOCK ENABLE (CKE)

The clock enable(CKE) gates the clock onto SDRAM. If CKE
goes low synchronously with clock (set-up and hold time are the-
same as other inputs), the internal clock is suspended from the
next clock cycle and the state of output and burst address is fro-
zen as long as the CKE remains low. All other inputs are ignored
from the next clock cycle after CKE goes low. When all banks
are in the idle state and CKE goes low synchronously with clock,
the SDRAM enters the power down mode from the next clock
cycle. The SDRAM remains in the power down mode ignoring
the other inputs as long as CKE remains low. The power down
exit is synchronous as the internal clock is suspended. When
CKE goes high at least "1CLK + t

" before the high going edge

of the clock, then the SDRAM becomes active from the same
clock edge accepting all the input commands.

BANK ADDRESSES (BA0 ~ BA1)

This SDRAM is organized as four independent banks of 524,288
words x 32 bits memory arrays. The BA

~ BA

inputs are

latched at the time of assertion of RAS and CAS to select the
bank to be used for the operation. The bank addresses BA

are latched at bank active, read, write, mode register set

and precharge operations.

ADDRESS INPUTS (A0 ~ A10)

The 19 address bits are required to decode the 524,288 word
locations are multiplexed into 11 address input pins (A

~ A

The 11 bit row addresses are latched along with RAS and BA

during bank activate command. The 8 bit column addresses

are latched along with CAS, WE and BA

~ BA

during read or

write command.

- 16

Device Operation &

x32 SDRAM

Timing Diagram

Rev. 0.1 July. 2003

MODE REGISTER SET (MRS)

The mode register stores the data for controlling the various
operating modes of SDRAM. It programs the CAS latency, burst
type, burst length, test mode and various vendor specific options
to make SDRAM useful for variety of different applications. The
default value of the mode register is not defined, therefore the
mode register must be written after power up to operate the
SDRAM. The mode register is written by asserting low on CS,
RAS, CAS and WE (The SDRAM should be in active mode with
CKE already high prior to writing the mode register). The state of
address pins A

~ A

and BA

~ BA

in the same cycle as CS,

RAS, CAS and WE going low is the data written in the mode
register. Two clock cycles is required to complete the write in the
mode register. The mode register contents can be changed
using the same command and clock cycle requirements during
operation as long as all banks are in the idle state. The mode
register is divided into various fields depending on the fields of
functions. The burst length field uses A

~ A

, burst type uses

, CAS latency (read latency from column address) use A

, vendor specific options or test mode use A

~ A

, A

/AP

and BA

~ BA

. The write burst length is programmed using A

~ A

, A

/AP and BA

~ BA

must be set to low for normal

SDRAM operation. Refer to the table for specific codes for vari-
ous burst length, burst type and CAS latencies.

BANK ACTIVATE

The bank activate command is used to select a random row in
an idle bank. By asserting low on RAS and CS with desired row
and bank address, a row access is initiated. The read or write
operation can occur after a time delay of t

RCD

(min) from the time

of bank activation. t

RCD

is an internal timing parameter of

SDRAM, therefore it is dependent on operating clock frequency.
The minimum number of clock cycles required between bank
activate and read or write command should be calculated by
dividing t

RCD

(min) with cycle time of the clock and then rounding

off the result to the next higher integer. The SDRAM has four
internal banks in the same chip and shares part of the internal
circuitry to reduce chip area, therefore it restricts the activation
of four banks simultaneously. Also the noise generated during
sensing of each bank of SDRAM is high, requiring some time for
power supplies to recover before another bank can be sensed
reliably. t

RRD

(min) specifies the minimum time required between

activating different bank. The number of clock cycles required
between different bank activation must be calculated similar to
t

RCD

specification. The minimum time required for the bank to be

active to initiate sensing and restoring the complete row of
dynamic cells is determined by t

RAS

(min). Every SDRAM bank

activate command must satisfy t

RAS

(min) specification before a

precharge command to that active bank can be asserted. The
maximum time any bank can be in the active state is determined
by t

RAS

(max). The number of cycles for both t

RAS

(min) and

RAS

(max) can be calculated similar to t

RCD

specification.

BURST READ

The burst read command is used to access burst of data on con-
secutive clock cycles from an active row in an active bank. The
burst read command is issued by asserting low on CS and CAS
with WE being high on the positive edge of the clock. The bank
must be active for at least t

RCD

(min) before the burst read com-

mand is issued. The first output appears in CAS latency number
of clock cycles after the issue of burst read command. The burst
length, burst sequence and latency from the burst read com-
mand is determined by the mode register which is already pro-
grammed. The burst read can be initiated on any column
address of the active row. The address wraps around if the initial
address does not start from a boundary such that number of out-
puts from each I/O are equal to the burst length programmed in
the mode register. The output goes into high-impedance at the
end of the burst, unless a new burst read was initiated to keep
the data output gapless. The burst read can be terminated by
issuing another burst read or burst write in the same bank or the
other active bank or a precharge command to the same bank.
The burst stop command is valid at every page burst length.

BURST WRITE

The burst write command is similar to burst read command and
is used to write data into the SDRAM on consecutive clock
cycles in adjacent addresses depending on burst length and
burst sequence. By asserting low on CS, CAS and WE with valid
column address, a write burst is initiated. The data inputs are
provided for the initial address in the same clock cycle as the
burst write command. The input buffer is deselected at the end
of the burst length, even though the internal writing can be com-
pleted yet. The writing can be completed by issuing a burst read
and DQM for blocking data inputs or burst write in the same or
another active bank. The burst stop command is valid at every
burst length. The write burst can also be terminated by using
DQM for blocking data and procreating the bank t

RDL

after the

last data input to be written into the active row. See DQM
OPERATION also.

DEVICE OPERATIONS (Continued)

- 17

Device Operation &

x32 SDRAM

Timing Diagram

Rev. 0.1 July. 2003

DQM OPERATION

The DQM is used to mask input and output operations. It works
similar to OE during read operation and inhibits writing during
write operation. The read latency is two cycles from DQM and
zero cycle for write, which means DQM masking occurs two
cycles later in read cycle and occurs in the same cycle during
write cycle. DQM operation is synchronous with the clock. The
DQM signal is important during burst interruptions of write with
read or precharge in the SDRAM. Due to asynchronous nature
of the internal write, the DQM operation is critical to avoid
unwanted or incomplete writes when the complete burst write is
not required. Please refer to DQM timing diagram also.

PRECHARGE

The precharge operation is performed on an active bank by
asserting low on CS, RAS, WE and A

/AP with valid BA

~ BA

of the bank to be precharged. The precharge command can be
asserted anytime after t

RAS

(min) is satisfied from the bank active

command in the desired bank. t

is defined as the minimum

number of clock cycles required to complete row precharge is
calculated by dividing t

with clock cycle time and rounding up

to the next higher integer. Care should be taken to make sure
that burst write is completed or DQM is used to inhibit writing
before precharge command is asserted. The maximum time any
bank can be active is specified by t

RAS

(max). Therefore, each

bank activate command. At the end of precharge, the bank
enters the idle state and is ready to be activated again. Entry to
Power down, Auto refresh, Self refresh and Mode register set
etc. is possible only when all banks are in idle state.

AUTO PRECHARGE

The precharge operation can also be performed by using auto
precharge. The SDRAM internally generates the timing to satisfy
t

RAS

(min) and "t

" for the programmed burst length and CAS

latency. The auto precharge command is issued at the same
time as burst read or burst write by asserting high on A

/AP. If

burst read or burst write by asserting high on A

/AP, the bank is

left active until a new command is asserted. Once auto
precahrge command is given, no new commands are possible to
that particular bank until the bank achieves idle state.

BOTH BANKS PRECHARGE

Both banks can be precharged at the same time by using Pre-
charge all command. Asserting low on CS, RAS, and WE with
high on A

/AP after all banks have satisfied t

RAS

(min) require-

ment, performs precharge on all banks. At the end of t

after

performing precharge to all the banks, both banks are in idle
state.

DEVICE OPERATIONS (Continued)

AUTO REFRESH

The storage cells of SDRAM need to be refreshed every 64ms
to maintain data. An auto refresh cycle accomplishes refresh of
a single row of storage cells. The internal counter increments
automatically on every auto refresh cycle to refresh all the rows.
An auto refresh command is issued by asserting low on CS,
RAS and CAS with high on CKE and WE. The auto refresh com-
mand can only be asserted with both banks being in idle state
and the device is not in power down mode (CKE is high in the
previous cycle). The time required to complete the auto refresh
operation is specified by t

RFC

(min). The minimum number of

clock cycles required can be calculated by driving t

RFC

with

clock cycle time and them rounding up to the next higher integer.
The auto refresh command must be followed by NOP's until the
auto refresh operation is completed. All banks will be in the idle
state at the end of auto refresh operation. The auto refresh is the
preferred refresh mode when the SDRAM is being used for nor-
mal data transactions. The auto refresh cycle can be performed
once in 15.6us or a burst of 4096 auto refresh cycles once in
64ms.

SELF REFRESH

The self refresh is another refresh mode available in the
SDRAM. The self refresh is the preferred refresh mode for data
retention and low power operation of SDRAM. In self refresh
mode, the SDRAM disables the internal clock and all the input
buffers except CKE. The refresh addressing and timing are
internally generated to reduce power consumption.
The self refresh mode is entered from all banks idle state by
asserting low on CS, RAS, CAS and CKE with high on WE.
Once the self refresh mode is entered, only CKE state being low
matters, all the other inputs including the clock are ignored in
order to remain in the self refresh mode.
The self refresh is exited by restarting the external clock and
then asserting high on CKE. This must be followed by NOP's for
a minimum time of t

RFC

before the SDRAM reaches idle state to

begin normal operation. If the system uses burst auto refresh
during normal operation, it is recommended to use burst 4096
auto refresh cycles immediately after exiting in self refresh
mode.

- 21

Device Operation &

x32 SDRAM

Timing Diagram

Rev. 0.1 July. 2003

*Note : 1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.

2. To inhibit invalid write, DQM should be issued.
3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge
interrupt but only another bank precharge of four banks operation.
4. For -55/60/70/80/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV"
. From the next generation, tRDL will be only 2CLK for every clock frequency.

5. Write Interrupted by Precharge & DQM

CLK

CMD

DQM

Masked by DQM

PRE

Note 3,4

Note 2

6. Precharge

CLK

CMD

PRE

1) Normal Write (BL=4)

tRDL
Note 1,4

2) Normal Read (BL=4)

CLK

CMD

DQ(CL2)

DQ(CL3)

PRE

*Note : 1. t

RDL

: Last data in to row precharge delay

2. Number of valid output data after row precharge : 1, 2 for CAS Latency = 2, 3 respectively.
3. The row active command of the precharge bank can be issued after t

from this point.

The new read/write command of other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
4. For -55/60/70/80/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV"
. From the next generation, tRDL will be only 2CLK for every clock frequency

7. Auto Precharge

CLK

CMD

1) Normal Write (BL=4)

Note 3,4
Auto Precharge Starts

2) Normal Read (BL=4)

CLK

CMD

DQ(CL2)

DQ(CL3)

Note 3
Auto Precharge Starts

Note 2

- 22

Device Operation &

x32 SDRAM

Timing Diagram

Rev. 0.1 July. 2003

*Note : 1. t

RDL

: 1 CLK

2. t

BDL

: 1 CLK ; Last data in to burst stop delay.

Read or write burst stop command is valid at every burst length.
3. Number of valid output data after row precharge or burst stop : 1, 2 for CAS latency= 2, 3 respectiviely.
4. PRE : All banks precharge if necessary.
MRS can be issued only at all banks precharge state.
5. For -55/60/70/80/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV"
. From the next generation, tRDL will be only 2CLK for every clock frequency

8. Burst Stop & Interrupted by Precharge

3) Read Interrupted by Precharge (BL=4)

CLK

CMD

DQ(CL2)

DQ(CL3)

PRE

9. MRS

CLK

PRE

1) Mode Register Set

4) Read Burst Stop (BL=4)

CLK

CMD

DQ(CL2)

DQ(CL3)

STOP

MRS

ACT

Note 4

tRP

2CLK

CMD

CLK

CMD

PRE

1) Normal Write (BL=4)

tRDL Note 1,5

CLK

CMD

STOP

2) Write Burst Stop (BL=8)

DQM

tBDL Note 2

Note 3

- 23

Device Operation &

x32 SDRAM

Timing Diagram

Rev. 0.1 July. 2003

*Note : 1. Active power down : one or more banks active state.

2. Precharge power down : all banks precharge state.
3. The auto refresh is the same as CBR refresh of conventional DRAM.
No precharge commands are required after auto refresh command.
During t

RFC

from auto refresh command, any other command can not be accepted.

4. Before executing auto/self refresh command, all banks must be idle state.
5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.
6. During self refresh mode, refresh interval and refresh operation are perfomed internally.
After self refresh entry, self refresh mode is kept while CKE is low.
During self refresh mode, all inputs expect CKE will be don't cared, and outputs will be in Hi-Z state.
For the time interval of t

RFC

from self refresh exit command, any other command can not be accepted.

Before/After self refresh mode, burst auto refresh cycle (4096 cycles) is recommended.

10. Clock Suspend Exit & Power Down Exit

CLK

CKE

CMD

1) Clock Suspend (=Active Power Down) Exit

tSS

CLK

CKE

CMD

2) Power Down (=Precharge Power Down) Exit

Note 1

Note 5

Internal

CLK

NOP

tSS

Note 2

Internal

CLK

11. Auto Refresh & Self Refresh

CLK

CMD

1) Auto Refresh

CKE

PRE

CMD

Note 4

tRP

tRFC

¡ó

CLK

CMD

2) Self Refresh

CKE

PRE

CMD

Note 4

tRP

tRFC

¡ó

Note 6

Note 3

ACT

¡ó

- 24

Device Operation &

x32 SDRAM

Timing Diagram

Rev. 0.1 July. 2003

12. About Burst Type Control

At MRS A

= "0". See the BURST SEQUENCE TABLE. (BL=4, 8)

BL=1, 2, 4, 8 and full page.

At MRS A

= "1". See the BURST SEQUENCE TABLE. (BL=4, 8)

BL=4, 8. At BL=1, 2 Interleave Counting = Sequential Counting

Every cycle Read/Write Command with random column address can realize Random
Column Access.
That is similar to Extended Data Out (EDO) Operation of conventional DRAM.

Basic

MODE

Random

MODE

Sequential Counting

Interleave Counting

Random column Access

CCD

= 1 CLK

13. About Burst Length Control

At MRS A

2,1,0

= "000".

At auto precharge, t

RAS

should not be violated.

At MRS A

2,1,0

= "001".

At auto precharge, t

RAS

should not be violated.

Before the end of burst, Row precharge command of the same bank stops read/write
burst with Row precharge.
t

RDL

= 2 with DQM, valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.

During read/write burst with auto precharge, RAS interrupt can not be issued.

Basic

MODE

Interrupt

MODE

RAS Interrupt

(Interrupted by Precharge)

At MRS A

2,1,0

= "010".

At MRS A

2,1,0

= "011".

At MRS A

2,1,0

= "111".

Wrap around mode(Infinite burst length) should be stopped by burst stop
Ras interrupt or CAS interrupt

4
8

Full Page

At MRS A

= "1".

Read burst =1, 2, 4, 8, full page write Burst =1
At auto precharge of write, t

RAS

should not be violated.

BDL

= 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively

Using burst stop command, any burst length control is possible.

Before the end of burst, new read/write stops read/write burst and starts new
read/write burst.
During read/write burst with auto precharge, CAS interrupt can not be issued.

BRSW

Burst Stop

CAS Interrupt

Random

MODE

Special

MODE

- 25

Device Operation &

x32 SDRAM

Timing Diagram

Rev. 0.1 July. 2003

X
X
X

CA, A

/AP

OP code

X
X
X

CA, A

/AP

CA, A

/AP

X
X
X
X

CA, A

/AP

CA, A

/AP

X
X
X
X

CA, A

/AP

CA, A

/AP

X
X
X
X

CA, A

/AP

RA, RA

X
X
X
X

CA, A

/AP

RA, RA

X
X
X
X

CA
RA

/AP

FUNCTION TRUTH TABLE (TABLE 1)

Current

State

RAS

CAS

ADDR

ACTION

Note

L
L
L
L
L
L
L

L
L
L
L
L

IDLE

Row

Active

Read

Write

Read with

Auto

Precharge

Write with

Auto

Precharge

Pre-

charging

NOP
NOP
ILLEGAL
ILLEGAL
Row (& Bank) Active ; Latch RA
NOP
Auto Refresh or Self Refresh
Mode Register Access
NOP
NOP
ILLEGAL
Begin Read ; latch CA ; determine AP
Begin Write ; latch CA ; determine AP
ILLEGAL
Precharge
ILLEGAL
NOP (Continue Burst to End --> Row Active)
NOP (Continue Burst to End --> Row Active)
Term burst --> Row active
Term burst, New Read, Determine AP
Term burst, New Write, Determine AP
ILLEGAL
Term burst, Precharge timing for Reads
ILLEGAL
NOP (Continue Burst to End --> Row Active)
NOP (Continue Burst to End --> Row Active)
Term burst --> Row active
Term burst, New read, Determine AP
Term burst, New Write, Determine AP
ILLEGAL
Term burst, precharge timing for Writes
ILLEGAL
NOP (Continue Burst to End --> Precharge)
NOP (Continue Burst to End --> Precharge)
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Continue Burst to End --> Precharge)
NOP (Continue Burst to End --> Precharge)
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOP --> Idle after t

NOP --> Idle after t

ILLEGAL
ILLEGAL
ILLEGAL
NOP --> Idle after t

X
X
X

BA
BA
BA

OP code

X
X
X

BA
BA
BA
BA

X
X
X
X

BA
BA
BA
BA

X
X
X
X

BA
BA
BA
BA

X
X
X
X

BA
BA

X
X
X
X

BA
BA

X
X
X
X

BA
BA
BA

X
H
H
H

L
L
L
L

X
H
H
H
H

L
L
L

X
H
H
H
H

L
L
L

X
H
H
H
H

L
L
L

X
H
H
H

L
L

X
H
H
H

L
L

X
H
H
H

L
L

X
H
H

H
H

L
L

X
H
H

L
L

H
H

X
H
H

L
L

H
H

X
H
H

L
L

H
H

X
H
H

H
H

X
H

X
X
H

X
X
X
X
H

X
H

2
2

4
5
5

3
2

3
3
2
3

2
2
2
4

- 26

Device Operation &

x32 SDRAM

Timing Diagram

Rev. 0.1 July. 2003

FUNCTION TRUTH TABLE (TABLE 1)

Current

State

RAS

CAS

ADDR

ACTION

Note

L
L
L
L
L
L

L
L
L
L

X
X
X
X

CA
RA

/AP

X
X
X
X
X
X
X
X
X
X
X

Row

Activating

Refreshing

ILLEGAL
NOP --> Row Active after t

RCD

NOP --> Row Active after t

RCD

ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOP --> Idle after t

RFC

NOP --> Idle after t

RFC

ILLEGAL
ILLEGAL
ILLEGAL
NOP --> Idle after 2 clocks
NOP --> Idle after 2 clocks
ILLEGAL
ILLEGAL
ILLEGAL

X
X
X
X

BA
BA
BA

X
X
X
X
X
X
X
X
X
X
X

X
H
H
H

L
L
L

X
H
H

L
L

X
H
H
H

X
H
H

H
H

X
H

X
H
H

X
X
H

X
H

X
X
X
X
X
X
X
H

X
X

2
2
2
2

Mode

Accessing

*Note : 1. All entries assume the CKE was active (High) during the precharge clcok and the current clock cycle.

2. Illegal to bank in specified state ; Function may be Iegal in the bank indicated by BA, depending on the
state of that bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA (and A

/AP).

5. Illegal if any bank is not idle.

Abbreviations : RA = Row Address BA = Bank Address
NOP = No Operation Command CA = Column Address AP = Auto Precharge

- 27

Device Operation &

x32 SDRAM

Timing Diagram

Rev. 0.1 July. 2003

FUNCTION TRUTH TABLE (TABLE 2)

Current

State

RAS

CAS

ADDR

ACTION

Note

X
H

L
L
L
L

X
X
H

L
L
L
L

X
X
H

L
L
L
L
L
L

X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

OP Code

X
X
X
X
X

Self

Refresh

INVALID
Exit Self Refresh --> Idle after t

RFC

(ABI)

Exit Self Refresh --> Idle after t

RFC

(ABI)

ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Self Refresh)
INVALID
Exit Power Down --> ABI
Exit Power Down --> ABI
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Low Power Mode)
Refer to Table 1
Enter Power Down
Enter Power Down
ILLEGAL
ILLEGAL
Row (& Bank) Active
Enter Self Refresh
Mode Register Access
NOP
Refer to Operations in Table 1
Begin Clock Suspend next cycle
Exit Clock Suspend next cycle
Maintain Clcok Suspend

X
X
H
H
H

X
X
X
H
H
H

L
L
L

X
X
X
X
X

X
X
H
H

X
X
X
X
H
H

L
L

X
X
X
X
X

X
X
H

X
X
X
X
X
H

X
H
H

X
X
X
X
X

6
6

7
7

8
8

9
9

All

Banks

Idle

*Note : 6. CKE low to high transition is asynchronous.

7. CKE low to high transition is asynchronous if restarts internal clock.
A minimum setup time 1CLK + t

must be satisfied before any command other than exit.

8. Power down and self refresh can be entered only from the both banks idle state.
9. Must be a legal command.

Abbreviations : ABI = All Banks Idle, RA = Row Address

CKE
(n-1)

L
L
L
L
L
L

H
H
H
H
H
H
H
H

H
H

L
L

X
H
H
H
H
H

L
L
L
L
L
L
L
L

CKE

All

Banks

Precharge

Power

Down

Any State

other than

Listed
above

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