K4S643233F-S(D)E/N/I/P
Rev. 1.5 Dec. 2002
CMOS SDRAM
2Mx32
Revision 1.5
December 2002
Mobile SDRAM
(VDD/VDDQ 3.0V/3.0V or 3.3V/3.3V)
90FBGA
K4S643233F-S(D)E/N/I/P
Rev. 1.5 Dec. 2002
CMOS SDRAM
The K4S643233F is 67,108,864 bits synchronous high data rate
Dynamic RAM organized as 4 x 524,288 words by 32 bits, fabri-
cated with SAMSUNG
s high performance CMOS technology.
Synchronous design allows precise cycle control with the use of
system clock. I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst lengths and
programmable latencies allow the same device to be useful for a
variety of high bandwidth and high performance memory system
applications.
3.0V & 3.3 power supply
.
LVCMOS compatible with multiplexed address.
Four banks operation.
MRS cycle with address key programs.
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
All inputs are sampled at the positive going edge of the system
clock .
Burst read single-bit write operation.
DQM for masking.
Auto & self refresh.
64ms refresh period (4K cycle).
Extended temperature operation (-25
C to 85
C).
Industrial temperature operation ( -40
C to 85
C).
90balls FBGA(-SXXX -Pb, -DXXX -Pb Free).
GENERAL DESCRIPTION
FEATURES
512K x 32Bit x 4 Banks SDRAM
FUNCTIONAL BLOCK DIAGRAM
*Samsung Electronics reserves the right to change products or specification without notice.
Bank Select
Data Input Register
512K x 32
512K x 32
S
e
n
s
e
A
M
P
O
u
t
p
u
t
B
u
f
f
e
r
I
/
O
C
o
n
t
r
o
l
Column Decoder
Latency & Burst Length
Programming Register
A
d
d
r
e
s
s
R
e
g
i
s
t
e
r
R
o
w
B
u
f
f
e
r
R
e
f
r
e
s
h
C
o
u
n
t
e
r
R
o
w
D
e
c
o
d
e
r
C
o
l
.
B
u
f
f
e
r
L
R
A
S
L
C
B
R
LCKE
LRAS
LCBR
LWE
LDQM
CLK
CKE
CS
RAS
CAS
WE
DQM
LWE
LDQM
DQi
CLK
ADD
LCAS
LWCBR
512K x 32
512K x 32
Timing Register
ORDERING INFORMATION
-S(D)E/N ; Normal/Low Power, Temp : -25
C ~ 85
C.
-S(D)I/P ; Normal/Low Power, Temp : -40
C ~ 85
C.
Note :
1. In case of 40MHz Frequency, CL1 can be supported.
Part No.
Max Freq.
Interface Package
K4S643233F-SE/N/I/P75
133MHz(CL=3)
105MHz(CL=2)
LVCMOS
90FBGA
Pb
K4S643233FSE/N/I/P1H
105MHz(CL=2)
K4S643233F-SE/N/I/P1L
105MHz(CL=3)
*1
K4S643233F-DE/N/I/P75
133MHz(CL=3)
105MHz(CL=2)
90FBGA
Pb Free
K4S643233F-DE/N/I/P1H
105MHz(CL=2)
K4S643233F-DE/N/I/P1L
105MHz(CL=3)
*1
K4S643233F-S(D)E/N/I/P
Rev. 1.5 Dec. 2002
CMOS SDRAM
90Ball(6x15) CSP
1
2
3
7
8
9
A
DQ26
DQ24
V
SS
V
D D
DQ23
DQ21
B
DQ28
V
DDQ
V
SSQ
V
DDQ
V
SSQ
DQ19
C
V
SSQ
DQ27
DQ25
DQ22
DQ20
V
DDQ
D
V
SSQ
DQ29
DQ30
DQ17
DQ18
V
DDQ
E
V
DDQ
DQ31
NC
NC
DQ16
V
SSQ
F
V
SS
DQM3
A3
A2
DQM2
V
D D
G
A4
A5
A6
A10
A0
A1
H
A7
A8
NC
NC
BA1
NC
J
CLK
CKE
A9
BA0
CS
RAS
K
DQM1
NC
NC
CAS
WE
DQM0
L
V
DDQ
DQ8
V
SS
V
D D
DQ7
V
SSQ
M
V
SSQ
DQ10
DQ9
DQ6
DQ5
V
DDQ
N
V
SSQ
DQ12
DQ14
DQ1
DQ3
V
DDQ
P
DQ11
V
DDQ
V
SSQ
V
DDQ
V
SSQ
DQ4
R
DQ13
DQ15
V
SS
V
D D
DQ0
DQ2
Pin Name
Pin Function
CLK
System Clock
CS
Chip Select
CKE
Clock Enable
A
0
~ A
10
Address
BA
0
~ BA
1
Bank Select Address
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
DQM
0
~
DQM
3
Data Input/Output Mask
DQ
0
~
31
Data Input/Output
V
DD
/V
SS
Power Supply/Ground
V
DDQ
/V
SSQ
Data Output Power/Ground
90-Ball FBGA Package Dimension and Pin Configuration
< Bottom View
*1
>
< Top View
*2
>
< Top View
*2
>
*2: Top View
Symbol
Min
Typ
Max
A
-
1.30
1.40
A
1
0.30
0.35
0.40
E
-
11.00
-
E
1
-
6.40
-
D
-
13.00
-
D
1
-
11.20
-
e
-
0.80
-
b
0.40
0.45
0.50
z
-
-
0.10
[Unit:mm]
5
2
1
6
3
4
8
9
7
F
E
D
C
B
J
H
G
A
e
D
D
/
2
D
1
E
1
E
E/2
A
A1
z
b
Substrate(4Layer)
#A1 Ball Origin Indicator
*1: Bottom View
M
L
K
R
P
N
K
4
S
6
4
3
2
3
3
F
-
X
X
X
X
S
A
M
S
U
N
G
W
e
e
k
K4S643233F-S(D)E/N/I/P
Rev. 1.5 Dec. 2002
CMOS SDRAM
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= -25
C to 85
C for Extended, -40
C to 85
C for Industrial)
Notes
:
1. V
IH
(max) = 5.3V AC. The overshoot voltage duration is
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
3ns.
3. Any input 0V
V
IN
V
DDQ
.
Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Dout is disabled, 0V
V
OUT
V
DDQ.
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply voltage
V
D D
2.7
3.0
3.6
V
V
DDQ
2.7
3.0
3.6
V
Input logic high voltage
V
I H
2.2
3.0
V
DDQ
+0.3
V
1
Input logic low voltage
V
IL
-0.3
0
0.5
V
2
Output logic high voltage
V
O H
2.4
-
-
V
I
O H
= -2mA
Output logic low voltage
V
OL
-
-
0.4
V
I
OL
= 2mA
Input leakage current
I
LI
-10
-
10
uA
3
ABSOLUTE MAXIMUM RATINGS
Notes
:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
V
I N
, V
OUT
-1.0 ~ 4.6
V
Voltage on V
D D
supply relative to Vss
V
DD
, V
DDQ
-1.0 ~ 4.6
V
Storage temperature
T
STG
-55 ~ +150
C
Power dissipation
P
D
1
W
Short circuit current
I
OS
50
mA
CAPACITANCE
(V
DD
= 3.0V & 3.3, T
A
= 23
C, f = 1MHz, V
REF
=0.9V
50
mV)
Pin
Symbol
Min
Max
Unit
Note
Clock
C
CLK
-
4.0
pF
RAS, CAS, WE, CS, CKE, DQM
0
~ DQM
3
C
IN
-
4.0
pF
Address(A
0
~ A
10,
BA
0
~ BA
1
)
C
ADD
-
4.0
pF
D Q
0
~ DQ
31
C
OUT
-
6.0
pF
K4S643233F-S(D)E/N/I/P
Rev. 1.5 Dec. 2002
CMOS SDRAM
DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= -25
C to 85
C for Extended, -40
C to 85
C for Industrial)
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S643233F-S(D)E/I**
4. K4S643233F-S(D)N/P**
5. Unless otherwise noted, input swing IeveI is CMOS(V
IH
/V
IL
=V
DDQ
/V
SSQ).
Parameter
Symbol
Test Condition
Version
Unit Note
-75
-1H
-1L
Operating Current
(One Bank Active)
I
CC1
Burst length = 1
t
RC
t
R C
(min)
I
O
= 0 mA
80
75
75
mA
1
Precharge Standby Current
in power-down mode
I
CC2
P
CKE
V
IL
(max), t
CC
= 10ns
0.5
mA
I
CC2
PS CKE & CLK
V
IL
(max), t
CC
=
0.5
Precharge Standby Current
in non power-down mode
I
C C 2
N
CKE
V
IH
(min), CS
V
I H
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
11
mA
I
CC2
NS
CKE
V
IH
(min), CLK
V
IL
(max), t
CC
=
Input signals are stable
8
Active Standby Current
in power-down mode
I
CC3
P
CKE
V
IL
(max), t
CC
= 10ns
5
mA
I
CC3
PS CKE & CLK
V
IL
(max), t
CC
=
5
Active Standby Current
in non power-down mode
(One Bank Active)
I
C C 3
N
CKE
V
IH
(min), CS
V
I H
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
22
mA
I
CC3
NS
CKE
V
IH
(min), CLK
V
IL
(max), t
CC
=
Input signals are stable
22
mA
Operating Current
I
CC4
I
O
= 0 mA ,Page burst
95
75
75
mA
1
Refresh Current
I
CC5
t
RC
t
RC
(min)
135
120
120
mA
2
Self Refresh Current
I
CC6
CKE
0.2V
-S(D)E/I
2
mA
3
-S(D)N/P
0.4
4
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