K4S643234E-SE/N
CMOS SDRAM
- 2 -
Rev. 1.8 April 2002
Revision 1.8 (April 19, 2002) -
Final
Erased TSOP specification.
Revision 1.7 (November 15, 2001) -
Final
Final specification for 2Mx32 SDRAM.
Revision 1.6 (October 10, 2001) -
Preliminary
Changed VDD and VDDQ range from 2.3V~3.3V to 2.3V~2.7V.
Deleted tCC 6ns part.
Changed Vtt from 1.05V to 0.5 x VDDQ.
Unification of tCH 3ns for -70 part and tCH 3ns for -80 part, tCH 3ns for -10 part.
Unification of tCL 3ns for -70 part and tCL 3ns for -80 part, tCL 3ns for -10 part.
Unification of tCL 1.75ns for -70 part and tCL 2ns for -80 part, tCL 2.5ns for -10 part.
Changed tCDL form 2clk to 1clk and tRDL for CL1 from 1clk to 2clk.
Revision 1.5 (August 7, 2001) -
Target
Addede CAS Latency 1
Revision 1.4(July 13, 2001)
Guaranteed 2.3V ~ 3.3V wide range
V
DD .
Revision 1.3 (April 6, 2001)
Reduced ICC current value
-Changed ICC6 value from 450um to 350um
-Changed ICC2P from 3mA to 1.2mA and ICC2PS from 2mA to1.2mA
-Changed ICC3P from 20mA to 10mA and ICC3PS from 20mA to 10mA
-Changed ICC3N from 55mA to 45mA and ICC3NS from 40mA to 30mA
-Changed ICC4 of K4S643234E-70 from 155mA to 130mA
-Changed ICC5 of K4S643234E-70 from 160mA to 145mA
Revision 1.2 (March 21, 2001)
Specified the current value as super low power for K4S643234E-80/10
Suppor ted 90Ball FBGA as well as 86-TSOP
Revision 1.1 (March 06, 2000)
Added K4S643234E-80/10 as a low curnent product.
Revision 1.0 (January 12, 2000)
Final spec
Revision 0.0 (December 20, 2000) - Preliminary Spec.
Initial draft
Revision History
K4S643234E-SE/N
CMOS SDRAM
- 3 -
Rev. 1.8 April 2002
The K4S643234E is 67,108,864 bits synchronous high data
rate Dynamic RAM organized as 4 x 524,288 words by 32 bits,
fabricated with SAMSUNG
s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock. I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length and programmable latencies allow the same device
to be useful for a variety of high bandwidth, high performance
memory system applications.
2.5V
power supply
.
LVCMOS compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
-. CAS latency (1 & 2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system
clock
Burst read single-bit write operation
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle).
Extended temperature range : (-25
C to 85
C)
GENERAL DESCRIPTION
FEATURES
512K x 32Bit x 4 Banks Synchronous DRAM
ORDERING INFORMATION
-SE/N : Extended temperature (-25
C to 85
C)
Part NO.
Max Freq.
Interface Package
K4S643234E-SE/N70
143MHz
LVCMOS 90 FBGA
K4S643234E-SE/N80
125MHz
K4S643234E-SE/N10
100MHz
FUNCTIONAL BLOCK DIAGRAM
Samsung Electronics reserves the right to
change products or specification without
notice.
*
Bank Select
Data Input Register
512K x 32
512K x 32
S
e
n
s
e
A
M
P
O
u
t
p
u
t
B
u
f
f
e
r
I
/
O
C
o
n
t
r
o
l
Column Decoder
Latency & Burst Length
Programming Register
A
d
d
r
e
s
s
R
e
g
i
s
t
e
r
R
o
w
B
u
f
f
e
r
R
e
f
r
e
s
h
C
o
u
n
t
e
r
R
o
w
D
e
c
o
d
e
r
C
o
l
.
B
u
f
f
e
r
L
R
A
S
L
C
B
R
LCKE
LRAS
LCBR
LWE
LDQM
CLK
CKE
CS
RAS
CAS
WE
DQM
LWE
LDQM
DQi
CLK
ADD
LCAS
LWCBR
512K x 32
512K x 32
Timing Register
K4S643234E-SE/N
CMOS SDRAM
- 5 -
Rev. 1.8 April 2002
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= -25 to 85
C)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply voltage
V
DD
, V
DDQ
2.3
2.5
2.7
V
Input logic high voltage
V
IH
0.8*V
DDQ
2.5
V
DDQ
+0.3
V
1
Input logic low voltage
V
IL
-0.3
0
0.7
V
2
Output logic high voltage
V
OH
0.9*V
DDQ
-
-
V
I
OH
= -1mA
Output logic low voltage
V
OL
-
-
0.4
V
I
OL
= 1mA
Input leakage current
I
LI
-10
-
10
uA
3
1. V
IH
(max) = 3.0V AC.The overshoot voltage duration is
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
3ns.
3. Any input 0V
V
IN
V
DDQ
,
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
Notes :
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
V
IN
, V
O U T
-0.5 ~ 3.6
V
Voltage on V
D D
supply relative to Vss
V
DD
, V
DDQ
-0.5 ~ 3.6
V
Storage temperature
T
STG
-55 ~ +150
C
Power dissipation
P
D
1
W
Short circuit current
I
OS
50
mA
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Note :
CAPACITANCE
(V
D D
= 2.5V, T
A
= 23
C, f = 1MHz, V
REF
= 1.4V
200
mV)
Pin
Symbol
Min
Max
Unit
Clock
C
CLK
-
4
pF
RAS, CAS, WE, CS, CKE, DQM
C
IN
-
4.5
pF
Address
C
A D D
-
4.5
pF
DQ
0
~ DQ
31
C
O U T
-
6.5
pF
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