K4S64323LF-S(D)N/U/P
Rev. 1.5 Dec 2002
CMOS SDRAM
2Mx32
Revision 1.5
December 2002
Mobile SDRAM
(VDD/VDDQ 2.5V/1.8V or 2.5V/2.5V)
90FBGA
K4S64323LF-S(D)N/U/P
Rev. 1.5 Dec 2002
CMOS SDRAM
The K4S64323LF is 67,108,864 bits synchronous high data rate
Dynamic RAM organized as 4 x 524,288 words by 32 bits, fabri-
cated with SAMSUNG
s high performance CMOS technology.
Synchronous design allows precise cycle control with the use of
system clock. I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst lengths and
programmable latencies allow the same device to be useful for a
variety of high bandwidth and high performance memory system
applications.
2.5V Power Supply
.
LVCMOS compatible with multiplexed address.
Four banks operation.
MRS cycle with address key programs.
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
All inputs are sampled at the positive going edge of the system
clock .
Burst read single-bit write operation.
DQM for masking.
Auto & self refresh.
64ms refresh period (4K cycle).
Extended temperature range (-25
C to 85
C).
Industrial Temperature range (-40
C to 85
C) for low power.
90balls FBGA( -SXXX -Pb, -DXXX -Pb Free).
GENERAL DESCRIPTION
FEATURES
512K x 32Bit x 4 Banks SDRAM
FUNCTIONAL BLOCK DIAGRAM
Samsung Electronics reserves the right to
change products or specification without
notice.
*
Bank Select
Data Input Register
512K x 32
512K x 32
S
e
n
s
e
A
M
P
O
u
t
p
u
t
B
u
f
f
e
r
I
/
O
C
o
n
t
r
o
l
Column Decoder
Latency & Burst Length
Programming Register
A
d
d
r
e
s
s
R
e
g
i
s
t
e
r
R
o
w
B
u
f
f
e
r
R
e
f
r
e
s
h
C
o
u
n
t
e
r
R
o
w
D
e
c
o
d
e
r
C
o
l
.
B
u
f
f
e
r
L
R
A
S
L
C
B
R
LCKE
LRAS
LCBR
LWE
LDQM
CLK
CKE
CS
RAS
CAS
WE
DQM
LWE
LDQM
DQi
CLK
ADD
LCAS
LWCBR
512K x 32
512K x 32
Timing Register
ORDERING INFORMATION
-S(D)N ; Low Power, Operating Temp : -25
C~85
C.
-S(D)U ; Super Low Power, Operating Temp : -25
C~85
C.
-S(D)P ; Low Power, Operating Temp : -40
C~85
C.
Notes :
1. In case of 55MHz Frequency, CL1 can be supported.
2. In case of 40MHz Frequency, CL1 can be supported.
3. In case of 33MHz Frequency, CL1 can be supported.
Part No.
Max Freq.
Interface Package
K4S64323LF-S(D)N/U/P75 133MHz(CL=3)
*1
105MHz(CL=2)
LVCMOS
90FBGA
Pb
(Pb Free)
K4S64323LF-S(D)N/U/P1H 105MHz(CL=2)
K4S64323LF-S(D)N/U/P1L 105MHz(CL=3)
*2
K4S64323LF-S(D)N/U/P15 66MHz(CL=2/3)
*3
K4S64323LF-S(D)N/U/P
Rev. 1.5 Dec 2002
CMOS SDRAM
90Ball(6x15) CSP
1
2
3
7
8
9
A
DQ26
DQ24
V
SS
V
D D
DQ23
DQ21
B
DQ28
V
DDQ
V
SSQ
V
DDQ
V
SSQ
DQ19
C
V
SSQ
DQ27
DQ25
DQ22
DQ20
V
DDQ
D
V
SSQ
DQ29
DQ30
DQ17
DQ18
V
DDQ
E
V
DDQ
DQ31
NC
NC
DQ16
V
SSQ
F
V
SS
DQM3
A3
A2
DQM2
V
D D
G
A4
A5
A6
A10
A0
A1
H
A7
A8
NC
NC
BA1
NC
J
CLK
CKE
A9
BA0
CS
RAS
K
DQM1
NC
NC
CAS
WE
DQM0
L
V
DDQ
DQ8
V
SS
V
D D
DQ7
V
SSQ
M
V
SSQ
DQ10
DQ9
DQ6
DQ5
V
DDQ
N
V
SSQ
DQ12
DQ14
DQ1
DQ3
V
DDQ
P
DQ11
V
DDQ
V
SSQ
V
DDQ
V
SSQ
DQ4
R
DQ13
DQ15
V
SS
V
D D
DQ0
DQ2
Pin Name
Pin Function
CLK
System Clock
CS
Chip Select
CKE
Clock Enable
A
0
~ A
10
Address
BA
0
~ BA
1
Bank Select Address
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
DQM
0
~
DQM
3
Data Input/Output Mask
DQ
0
~
31
Data Input/Output
V
DD
/V
SS
Power Supply/Ground
V
DDQ
/V
SSQ
Data Output Power/Ground
90-Ball FBGA Package Dimension and Pin Configuration
< Bottom View
*1
>
< Top View
*2
>
< Top View
*2
>
*2: Top View
Symbol
Min
Typ
Max
A
-
1.30
1.40
A
1
0.30
0.35
0.40
E
-
11.00
-
E
1
-
6.40
-
D
-
13.00
-
D
1
-
11.20
-
e
-
0.80
-
b
0.40
0.45
0.50
z
-
-
0.10
[Unit:mm]
5
2
1
6
3
4
8
9
7
F
E
D
C
B
J
H
G
A
e
D
D
/
2
D
1
E
1
E
E/2
A
A1
z
b
#A1 Ball Origin Indicator
*1: Bottom View
M
L
K
R
P
N
K
4
S
6
4
3
2
3
L
F
-
X
X
X
X
S
A
M
S
U
N
G
W
e
e
k
Substrate(4Layer)
K4S64323LF-S(D)N/U/P
Rev. 1.5 Dec 2002
CMOS SDRAM
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= -25
C to 85
C for Extended, -40
C to 85
C for Industrial)
Notes
:
1. V
IH
(max) = 3.0V AC.The overshoot voltage duration is
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
3ns.
3. Any input 0V
V
IN
V
DDQ
.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Dout is disabled, 0V
V
OUT
V
DDQ.
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply voltage
V
D D
2.3
2.5
2.7
V
V
DDQ
1.65
-
2.7
V
Input logic high voltage
V
I H
0.8 x V
DDQ
-
V
DDQ
+ 0.3
V
1
Input logic low voltage
V
IL
-0.3
0
0.3
V
2
Output logic high voltage
V
O H
V
DDQ
-0.2V
-
-
V
I
O H
= -0.1mA
Output logic low voltage
V
OL
-
-
0.2
V
I
OL
= 0.1mA
Input leakage current
I
LI
-10
-
10
uA
3
CAPACITANCE
(V
DD
= 2.5V, T
A
= 23
C, f = 1MHz, V
REF
=0.9V
50
mV)
Pin
Symbol
Min
Max
Unit
Note
Clock
C
CLK
-
4.0
pF
RAS, CAS, WE, CS, CKE, DQM
0
~ DQM
3
C
IN
-
4.0
pF
Address(A
0
~ A
10,
BA
0
~ BA
1
)
C
ADD
-
4.0
pF
D Q
0
~ DQ
31
C
OUT
-
6.0
pF
ABSOLUTE MAXIMUM RATINGS
Notes
:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
V
IN
, V
OUT
-1.0 ~ 3.6
V
Voltage on V
DD
supply relative to Vss
V
D D
, V
DDQ
-1.0 ~ 3.6
V
Storage temperature
T
STG
-55 ~ +150
C
Power dissipation
P
D
1
W
Short circuit current
I
OS
50
mA
K4S64323LF-S(D)N/U/P
Rev. 1.5 Dec 2002
CMOS SDRAM
DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= -25
C to 85
C for Extended, -40
C to 85
C for Industrial)
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S64323LF-S(D)N/P**
4. K4S64323LF-S(D)U**
5. Unless otherwise noted, input swing IeveI is CMOS(V
IH
/V
IL
=V
DDQ
/V
SSQ).
Parameter
Symbol
Test Condition
Version
Unit Note
-75
-1H
-1L
-15
Operating Current
(One Bank Active)
I
CC1
Burst length = 1
t
RC
t
R C
(min)
I
O
= 0 mA
70
70
65
60
mA
1
Precharge Standby Current
in power-down mode
I
CC2
P
CKE
V
IL
(max), t
CC
= 10ns
0.5
mA
I
CC2
PS CKE & CLK
V
IL
(max), t
CC
=
0.5
Precharge Standby Current
in non power-down mode
I
C C 2
N
CKE
V
IH
(min), CS
V
I H
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
10
mA
I
CC2
NS
CKE
V
IH
(min), CLK
V
IL
(max), t
CC
=
Input signals are stable
7
Active Standby Current
in power-down mode
I
CC3
P
CKE
V
IL
(max), t
CC
= 10ns
5
mA
I
CC3
PS CKE & CLK
V
IL
(max), t
CC
=
5
Active Standby Current
in non power-down mode
(One Bank Active)
I
C C 3
N
CKE
V
IH
(min), CS
V
I H
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
20
mA
I
CC3
NS
CKE
V
IH
(min), CLK
V
IL
(max), t
CC
=
Input signals are stable
20
mA
Operating Current
I
CC4
I
O
= 0 mA ,Page burst
85
70
70
60
mA
1
Refresh Current
I
CC5
t
RC
t
RC
(min)
115
110
100
80
mA
2
Self Refresh Current
I
CC6
CKE
0.2V
-S(D)N/P
350
uA
3
-S(D)U
230
4
K4S64323LF-S(D)N/U/P
Rev. 1.5 Dec 2002
CMOS SDRAM
VDDQ
500
500
Output
30pF
V
OH
(DC) = V
DDQ
-0.2V, I
O H
= -0.1mA
V
OL
(DC) = 0.2V, I
OL
= 0.1mA
Vtt=0.5 x VDDQ
50
Output
30pF
Z0=50
(Fig. 2) AC Output Load Circuit
(Fig. 1) DC Output Load Circuit
AC OPERATING TEST CONDITIONS
(V
DD
= 2.5V
0.2V, T
A
= -25
C to 85
C for Extended, -40
C to 85
C for Industrial)
Parameter
Value
Unit
AC input levels (Vih/Vil)
0.9 x V
DDQ
/ 0.2
V
Input timing measurement reference level
0.5 x V
DDQ
V
Input rise and fall time
tr/tf = 1/1
ns
Output timing measurement reference level
0.5 x V
DDQ
V
Output load condition
See Fig. 2
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. Minimum tRDL=2CLK and tDAL(=tRDL + tRP) is required to complete both of last data wite command(tRDL) and precharge
command(tRP). tRDL=1CLK can be supported only in the case under 100MHz with manual precharge mode.
4. All parts allow every cycle column address change.
5. In case of row precharge interrupt, auto precharge and read burst stop.
Parameter
Symbol
Version
Unit
Note
- 75
-1H
-1L
-15
Row active to row active delay
t
RRD
(min)
15
19
19
30
ns
1
RAS to CAS delay
t
RCD
(min)
19
19
24
30
ns
1
Row precharge time
t
RP
(min)
19
19
24
30
ns
1
Row active time
t
RAS
(min)
45
50
60
60
ns
1
t
RAS
(max)
100
us
Row cycle time
t
R C
(min)
65
70
84
90
ns
1
Last data in to row precharge
t
R D L
(min)
2
CLK
2,3
Last data in to Active delay
t
DAL
(min)
tRDL + tRP
-
3
Last data in to new col. address delay
t
C D L
(min)
1
CLK
2
Last data in to burst stop
t
BDL
(min)
1
CLK
2
Col. address to col. address delay
t
CCD
(min)
1
CLK
4
Number of valid output data
CAS latency=3
2
ea
5
CAS latency=2
1
CAS latency=1
-
0
K4S64323LF-S(D)N/U/P
Rev. 1.5 Dec 2002
CMOS SDRAM
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Parameter
Symbol
- 75
-1H
-1L
- 15
Unit Note
Min
Max
Min
Max
Min
Max
Min
Max
CLK cycle time
CAS latency=3
t
C C
7.5
1000
9.5
1000
9.5
1000
15
1000
ns
1
CAS latency=2
9.5
9.5
12
15
CAS latency=1
-
-
25
30
CLK to valid output delay
CAS latency=3
t
SAC
5.4
7
7
9
ns
1,2
CAS latency=2
7
7
8
9
CAS latency=1
-
-
20
24
Output data hold time
CAS latency=3
t
O H
2.5
2.5
2.5
2.5
ns
2
CAS latency=2
2.5
2.5
2.5
2.5
CAS latency=1
-
-
2.5
2.5
CLK high pulse width
t
C H
2.5
3
3
3.5
ns
3
CLK low pulse width
t
CL
2.5
3
3
3.5
ns
3
Input setup time
t
SS
2.0
2.5
2.5
3.5
ns
3
Input hold time
t
SH
1.0
1.5
1.5
2.0
ns
3
CLK to output in Low-Z
t
SLZ
1
1
1
1
ns
2
CLK to output in Hi-Z
CAS latency=3
t
SHZ
5.4
7
7
9
ns
CAS latency=2
7
7
8
9
CAS latency=1
-
-
20
24
Notes :
1. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life
is potentially at stake. Please contact to the memory marketing team in samsung electronics when considering the use of
a product contained herein for any specific purpose, such as medical, aerospace, nuclear, military, vehicular or undersea
repeater use.
K4S64323LF-S(D)N/U/P
Rev. 1.5 Dec 2002
CMOS SDRAM
SIMPLIFIED TRUTH TABLE
(V=Valid, X=Don
t Care, H=Logic High, L=Logic Low)
Note :
1. OP Code : Operand Code
A
0
~ A
10
& BA
0
~ BA
1
: Program keys. (@MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are the same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA
0
~ BA
1
: Bank select addresses.
If both BA
0
and BA
1
are "Low" at read, write, row active and precharge, bank A is selected.
If BA
0
is "Low" and BA
1
is "High" at read, write, row active and precharge, bank B is selected.
If BA
0
is "High" and BA
1
is "Low" at read, write, row active and precharge, bank C is selected.
If both BA
0
and BA
1
are "High" at read, write, row active and precharge, bank D is selected.
If A
10
/AP is "High" at row precharge, BA
0
and BA
1
are ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t
RP
after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency
is 0), but in read operation it makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2).
COMMAND
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
BA
0,1
A
10
/AP
A
9
~ A
0
Note
Register
Mode Register Set
H
X
L
L
L
L
X
OP CODE
1, 2
Refresh
Auto Refresh
H
H
L
L
L
H
X
X
3
Self
Refresh
Entry
L
3
Exit
L
H
L
H
H
H
X
X
3
H
X
X
X
3
Bank Active & Row Addr.
H
X
L
L
H
H
X
V
Row Address
Read &
Column Address
Auto Precharge Disable
H
X
L
H
L
H
X
V
L
Column
Address
(A
0
~ A
7
)
4
Auto Precharge Enable
H
4, 5
Write &
Column Address
Auto Precharge Disable
H
X
L
H
L
L
X
V
L
Column
Address
(A
0
~ A
7
)
4
Auto Precharge Enable
H
4, 5
Burst Stop
H
X
L
H
H
L
X
X
6
Precharge
Bank Selection
H
X
L
L
H
L
X
V
L
X
All Banks
X
H
Clock Suspend or
Active Power Down
Entry
H
L
H
X
X
X
X
X
L
V
V
V
Exit
L
H
X
X
X
X
X
Precharge Power Down Mode
Entry
H
L
H
X
X
X
X
X
L
H
H
H
Exit
L
H
H
X
X
X
X
L
V
V
V
DQM
H
X
V
X
7
No Operation Command
H
X
H
X
X
X
X
X
L
H
H
H
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