Page 1 of 28

Rev. 1.1 Aug. 2005

DDR2 SDRAM

1G A-die DDR2 SDRAM

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

1Gb A-die DDR2 SDRAM Specification

Version 1.1

August 2005

Page 3 of 28

Rev. 1.1 Aug. 2005

DDR2 SDRAM

1G A-die DDR2 SDRAM

Key Features

Speed

DDR2-667 5-5-5

DDR2-533 4-4-4

DDR2-400 3-3-3

Units

CAS Latency

tCK

tRCD(min)

tRP(min)

tRC(min)

Ordering Information

Note 1 : Speed bin is in order of CL-tRCD-tRP.
Note 2 : x4/x8 Package - including 8 dummy balls.

Organization

DDR2-667 5-5-5

DDR2-533 4-4-4

DDR2-400 3-3-3

Package

256Mx4

K4T1G044QA-ZCE6

K4T1G044QA-ZCD5

K4T1G044QA-ZCCC

68 FBGA

128Mx8

K4T1G084QA-ZCE6

K4T1G084QA-ZCD5

K4T1G084QA-ZCCC

68 FBGA

64Mx16

K4T1G164QA-ZCE6

K4T1G164QA-ZCD5

K4T1G164QA-ZCCC

84 FBGA

· JEDEC standard 1.8V ± 0.1V Power Supply
· VDDQ = 1.8V ± 0.1V

· 200 MHz f

for 400Mb/sec/pin, 267MHz f

for 533Mb/sec/

pin, 333MHz f

for 667Mb/sec/pin

· 8 Banks
· Posted CAS

· Programmable CAS Latency: 3, 4, 5
· Programmable Additive Latency: 0, 1 , 2 , 3 and 4

· Write Latency(WL) = Read Latency(RL) -1
· Burst Length: 4 , 8(Interleave/nibble sequential)

· Programmable Sequential / Interleave Burst Mode
· Bi-directional Differential Data-Strobe (Single-ended data-

strobe is an optional feature)

· Off-Chip Driver(OCD) Impedance Adjustment
· On Die Termination

· Special Function Support

-PASR(Partial Array Self Refresh)
-50ohm ODT
-High Temperature Self-Refresh rate enable

· Average Refresh Period 7.8us at lower than T

CASE

°C,

3.9us at 85

°C < T

CASE

< 95

°C

Package: 68ball FBGA - 256Mx4/128Mx8 , 84ball FBGA -
64Mx16

· All of Lead-free products are compliant for RoHS

The 1Gb DDR2 SDRAM is organized as a 32Mbit x 4 I/Os x 8
banks, 16Mbit x 8 I/Os x 8banks or 8Mbit x 16 I/Os x 8 banks
device. This synchronous device achieves high speed double-
data-rate transfer rates of up to 667Mb/sec/pin (DDR2-667) for
general applications.
The chip is designed to comply with the following key DDR2
SDRAM features such as posted CAS with additive latency, write
latency = read latency - 1, Off-Chip Driver(OCD) impedance
adjustment and On Die Termination.
All of the control and address inputs are synchronized with a pair
of externally supplied differential clocks. Inputs are latched at the
crosspoint of differential clocks (CK rising and CK falling). All I/Os
are synchronized with a pair of bidirectional strobes (DQS and
DQS) in a source synchronous fashion. The address bus is used
to convey row, column, and bank address information in a RAS/
CAS multiplexing style. For example, 1Gb(x4) device receive 14/
11/3 addressing.
The 1Gb DDR2 device operates with a single 1.8V ± 0.1V power
supply and 1.8V ± 0.1V VDDQ.
The 1Gb DDR2 device is available in 68ball FBGAs(x4/x8) and in
84ball FBGAs(x16).

Note: The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of oper-
ation.

Note : This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in "DDR2 SDRAM Device
Operation & Timing Diagram".

Page 4 of 28

Rev. 1.1 Aug. 2005

DDR2 SDRAM

1G A-die DDR2 SDRAM

Package Pinout/Mechanical Dimension & Addressing

Notes:
1. Pin E3 has identical
capacitance as pin E7.
2. VDDL and VSSDL are
power and ground for the
DLL.

x4 package pinout (Top View) : 68ball FBGA Package

(60balls + 8balls of dummy balls)

VDD

VSS

VSSQ

VDDQ

VSSQ

DQS

DQ0

VDDQ

DQ2

VSSQ

VSSDL

VDD

RAS

CAS

A11

A13

A12

VDD

A10/AP

VSS

VDDQ

VSSQ

DQ1

DQ3

VDDL

BA1

VREF

VSS

CKE

BA0

1 2 3 7 8 9

VDD

VSS

ODT

BA2

Ball Locations (x4)

: Populated Ball

+ : Depopulated Ball

Top View (See the balls through the Package)

A
B
C
D
E

+ + +

N
P
R

U
V

Package Pinout

Page 5 of 28

Rev. 1.1 Aug. 2005

DDR2 SDRAM

1G A-die DDR2 SDRAM

Notes:
1.

Pins F3 and E2 have
identical capacitance as
pins F7 and E8.

For a read, when enabled,
strobe pair RDQS &
RDQS are identical in
function and timing to
strobe pair DQS & DQS
and input masking
function is disabled.

The function of DM or
RDQS/RDQS are enabled
by EMRS command.

VDDL and VSSDL are
power and ground for the
DLL.

x8 package pinout (Top View) : 68ball FBGA Package

(60balls + 8balls of dummy balls)

VDD

NU/

VSS

DQ6

VSSQ

VDDQ

VSSQ

DQS

DQ7

DQ0

VDDQ

DQ2

VSSQ

DQ5

VSSDL

VDD

RAS

CAS

A11

A13

A12

VDD

A10/AP

VSS

VDDQ

VSSQ

DQ1

DQ3

DQ4

VDDL

BA1

VREF

VSS

CKE

BA0

1 2 3 7 8 9

VDD

VSS

ODT

BA2

Ball Locations (x8)

: Populated Ball

+ : Depopulated Ball

Top View (See the balls through the Package)

A
B
C
D
E

+ + +

N
P
R

U
V

DM/

RDQS

Page 6 of 28

Rev. 1.1 Aug. 2005

DDR2 SDRAM

1G A-die DDR2 SDRAM

Note :
1. VDDL and VSSDL are
power and ground for the
DLL.
2. In case of only 8 DQs out

of 16 DQs are used,
LDQS, LDQSB and
DQ0~7 must be used.

VDD

VSS

DQ14

VSSQ

UDM

VDDQ

VSSQ

UDQS

DQ15

DQ8

VDDQ

DQ10

VSSQ

DQ13

VSSQ

VDDQ

RAS

CAS

A11

A12

VDD

A10/AP

VSS

VDDQ

VSSQ

DQ9

DQ11

DQ12

VDD

BA1

VSS

CKE

BA0

1 2 3 7 8 9

VDD

VSS

ODT

BA2

Ball Locations (x16)

: Populated Ball

+ : Depopulated Ball

Top View (See the balls through the Package)

DQ6

VSSQ

LDM

VDDQ

VSSQ

LDQS

DQ7

DQ0

VDDQ

DQ2

VSSQ

DQ5

VSSDL

VDD

VDDQ

VSSQ

DQ1

DQ3

DQ4

VDDL

VREF

VSS

LDQS

+ + +

A
B
C
D

N
P
R

x16 package pinout (Top View) : 84ball FBGA Package

Page 9 of 28

Rev. 1.1 Aug. 2005

DDR2 SDRAM

1G A-die DDR2 SDRAM

Input/Output Functional Description

In this data sheet, "differential DQS signals" refers to any of the following with A10 = 0 of EMRS(1)

x4 DQS/DQS

x8 DQS/DQS

if EMRS(1)[A11] = 0

x8 DQS/DQS, RDQS/RDQS,

if EMRS(1)[A11] = 1

x16 LDQS/LDQS and UDQS/UDQS

"single-ended DQS signals" refers to any of the following with A10 = 1 of EMRS(1)

x4 DQS

x8 DQS

if EMRS(1) [A11] = 0

x8 DQS, RDQS,

if EMRS(1) [A11] = 1

x16 LDQS and UDQS

Symbol

Type

Function

CK, CK

Input

Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of
the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK
(both directions of crossing).

CKE

Input

Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and
output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or
Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self
refresh entry. CKE is asynchronous for self refresh exit. After V

REF

has become stable during the power on and ini-

tialization swquence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry
and exit, V

REF

must be maintained to this input. CKE must be maintained high throughout read and write accesses.

Input buffers, excluding CK, CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are
disabled during self refresh.

Input

Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on
systems with multiple Ranks. CS is considered part of the command code.

ODT

Input

On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When
enabled, ODT is only applied to each DQ, DQS, DQS, RDQS, RDQS, and DM signal for x4/x8 configurations. For
x16 configuration, ODT is applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM signal. The ODT pin
will be ignored if the Extended Mode Register Set(EMRS) is programmed to disable ODT.

RAS, CAS, WE

Input

Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.

Input

Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coin-
cident with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input
only, the DM loading matches the DQ and DQS loading. For x8 device, the function of DM or RDQS/RDQS is
enabled by EMRS command.

BA0 - BA2

Input

Bank Address Inputs: BA0, BA1 and BA2 define to which bank an Active, Read, Write or Precharge command is
being applied. Bank address also determines if the mode register or extended mode register is to be accessed dur-
ing a MRS or EMRS cycle.

A0 - A13

Input

Address Inputs: Provided the row address for Active commands and the column address and Auto Precharge bit
for Read/Write commands to select one location out of the memory array in the respective bank. A10 is sampled
during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks
(A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1 and BA2. The address inputs
also provide the op-code during Mode Register Set commands.

Input/Output Data Input/ Output: Bi-directional data bus.

DQS, (DQS)

(LDQS), (LDQS)

(UDQS), (UDQS)
(RDQS), (RDQS)

Input/Output

Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. For
the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS corresponds to the data on DQ8-DQ15. For the x8, an
RDQS option using DM pin can be enabled via the EMRS(1) to simplify read timing. The data strobes DQS, LDQS,
UDQS, and RDQS may be used in single ended mode or paired with optional complementary signals DQS, LDQS,
UDQS, and RDQS to provide differential pair signaling to the system during both reads and writes. An EMRS(1)
control bit enables or disables all complementary data strobe signals.

No Connect: No internal electrical connection is present.

DDQ

Supply

Power Supply: 1.8V +/- 0.1V, DQ Power Supply: 1.8V +/- 0.1V

SSQ

Supply

Ground, DQ Ground

DDL

Supply

DLL Power Supply: 1.8V +/- 0.1V

SSDL

Supply

DLL Ground

REF

Supply

Reference voltage

Page 10 of 28

Rev. 1.1 Aug. 2005

DDR2 SDRAM

1G A-die DDR2 SDRAM

1Gb Addressing

* Reference information: The following tables are address mapping information for other densities.

256Mb

512Mb

2Gb

4Gb

Configuration

256Mb x4

128Mb x 8

64Mb x16

# of Bank

Bank Address

BA0 ~ BA2

Auto precharge

/AP

Row Address

~ A

Column Address

~ A

Configuration

64Mb x4

32Mb x 8

16Mb x16

# of Bank

Bank Address

BA0,BA1

Auto precharge

/AP

Row Address

~ A

Column Address

~ A

Configuration

128Mb x4

64Mb x 8

32Mb x16

# of Bank

Bank Address

BA0,BA1

Auto precharge

A10/AP

Row Address

A0 ~ A13

A0 ~ A12

Column Address

A0 ~ A9,A11

A0 ~ A9

Configuration

512Mb x4

256Mb x 8

128Mb x16

# of Bank

Bank Address

BA0 ~ BA2

Auto precharge

A10/AP

Row Address

A0 ~ A14

A0 ~ A13

Column Address

A0 ~ A9,A11

A0 ~ A9

Configuration

1 Gb x4

512Mb x 8

256Mb x16

# of Bank

Bank Address

BA0 ~ BA2

Auto precharge

A10/AP

Row Address

A0 - A15

A0 - A14

Column Address/page size

A0 - A9,A11

A0 - A9

Page 11 of 28

Rev. 1.1 Aug. 2005

DDR2 SDRAM

1G A-die DDR2 SDRAM

Absolute Maximum DC Ratings

Note :
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2

standard.

AC & DC Operating Conditions

Recommended DC Operating Conditions (SSTL - 1.8)

Note : There is no specific device V

supply voltage requirement for SSTL-1.8 compliance. However under all conditions V

DDQ

must be less than or equal

to V

1. The value of V

REF

may be selected by the user to provide optimum noise margin in the system. Typically the value of V

REF

is expected to be about 0.5

x V

DDQ

of the transmitting device and V

REF

is expected to track variations in V

DDQ

2. Peak to peak AC noise on V

REF

may not exceed +/-2% V

REF

(DC).

3. V

of transmitting device must track V

REF

of receiving device.

4. AC parameters are measured with V

, V

DDQ

and V

DDL

tied together.

Symbol

Parameter

Rating

Units

Notes

Voltage on V

pin relative to V

- 1.0 V ~ 2.3 V

DDQ

Voltage on V

DDQ

pin relative to V

- 0.5 V ~ 2.3 V

DDL

Voltage on V

DDL

pin relative to V

- 0.5 V ~ 2.3 V

IN,

OUT

Voltage on any pin relative to V

- 0.5 V ~ 2.3 V

STG

Storage Temperature

-55 to +100

°C 1,

Symbol

Parameter

Rating

Units

Notes

Min.

Typ.

Max.

Supply Voltage

1.7

1.8

1.9

DDL

Supply Voltage for DLL

1.7

1.8

1.9

DDQ

Supply Voltage for Output

1.7

1.8

1.9

REF

Input Reference Voltage

0.49*V

DDQ

0.50*V

DDQ

0.51*V

DDQ

1,2

Termination Voltage

REF

-0.04

REF

+0.04

Page 12 of 28

Rev. 1.1 Aug. 2005

DDR2 SDRAM

1G A-die DDR2 SDRAM

Operating Temperature Condition

Note :
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2

standard.

2. At 85 - 95

°C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self

refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.

Input DC Logic Level

Input AC Logic Level

AC Input Test Conditions

Notes:
1. Input waveform timing is referenced to the input signal crossing through the V

IH/IL

(AC)

level applied to the device under test.

2. The input signal minimum slew rate is to be maintained over the range from V

REF

to V

(AC) min for rising edges and the range from V

REF

to V

(AC)

max for falling edges as shown in the below figure.

3. AC timings are referenced with input waveforms switching from V

(AC) to V

(AC) on the positive transitions and V

(AC) to V

(AC) on the negative

transitions.

Symbol

Parameter

Rating

Units

Notes

TOPER

Operating Temperature

0 to 95

°C 1,

Symbol

Parameter

Min.

Max.

Units

Notes

(DC)

DC input logic high

REF

+ 0.125

DDQ

+ 0.3

(DC)

DC input logic low

- 0.3

REF

- 0.125

Symbol

Parameter

DDR2-400, DDR2-533

DDR2-667

Units

Min.

Max.

Min.

Max.

(AC)

AC input logic high

REF

+ 0.250

REF

+ 0.200

(AC)

AC input logic low

REF

- 0.250

REF

- 0.200

Symbol

Condition

Value

Units

Notes

REF

Input reference voltage

0.5 * V

DDQ

SWING(MAX)

Input signal maximum peak to peak swing

1.0

SLEW

Input signal minimum slew rate

1.0

V/ns

2, 3

DDQ

(AC) min

(DC) min

REF

(DC) max

(AC) max

< AC Input Test Signal Waveform >

SWING(MAX)

delta TR

delta TF

REF

- V

(AC) max

delta TF

Falling Slew =

Rising Slew =

(AC) min - V

REF

delta TR

Page 13 of 28

Rev. 1.1 Aug. 2005

DDR2 SDRAM

1G A-die DDR2 SDRAM

Differential input AC logic Level

Notes :
1. V

(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or

UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to V

(AC) - V

(AC).

2. The typical value of V

(AC) is expected to be about 0.5 * V

DDQ

of the transmitting device and V

(AC) is expected to track variations in V

DDQ

. VIX(AC)

indicates the voltage at which differential input signals must cross.

Differential AC output parameters

Note :
1. The typical value of V

(AC) is expected to be about 0.5 * V

DDQ

of the transmitting device and V

(AC) is expected to track variations in V

DDQ

(AC) indicates the voltage at which differential output signals must cross.

Symbol

Parameter

Min.

Max.

Units

Notes

(AC)

AC differential input voltage

0.5

DDQ

+ 0.6

(AC)

AC differential cross point voltage

0.5 * V

DDQ

- 0.175

0.5 * V

DDQ

+ 0.175

Symbol

Parameter

Min.

Max.

Units

Note

(AC)

AC differential cross point voltage

0.5 * V

DDQ

- 0.125

0.5 * V

DDQ

+ 0.125

DDQ

Crossing point

SSQ

IX or

< Differential signal levels >

Page 14 of 28

Rev. 1.1 Aug. 2005

DDR2 SDRAM

1G A-die DDR2 SDRAM

OCD default characteristics

Notes:
1. Absolute Specifications (0°C

CASE

+95°C; V

= +1.8V ±0.1V, V

DDQ

= +1.8V ±0.1V)

2. Impedance measurement condition for output source dc current: V

DDQ

= 1.7V; V

OUT

= 1420mV; (V

OUT

-V

DDQ

)/Ioh must be less than 23.4 ohms for val-

ues of V

OUT

between V

DDQ

and V

DDQ

-280mV. Impedance measurement condition for output sink dc current: V

DDQ

= 1.7V; V

OUT

= 280mV; V

OUT

Iol must be less than 23.4 ohms for values of V

OUT

between 0V and 280mV.

3. Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage.
4. Slew rate measured from V

(AC) to V

(AC).

5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is guaran-

teed by design and characterization.

6. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process and represents only the DRAM uncertainty.

Output slew rate load :

7. DRAM output slew rate specification applies to 400Mb/sec/pin, 533Mb/sec/pin and 667Mb/sec/pin speed bins.
8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in tDQSQ and tQHS specification.

Description

Parameter

Min

Nom

Max

Unit

Notes

Output impedance

12.6

23.4

ohms

1,2

Output impedance step size for OCD calibration

1.5

ohms

Pull-up and pull-down mismatch

ohms

1,2,3

Output slew rate

Sout

1.5

V/ns

1,4,5,6,7,8

25 ohms

VTT

Output

(VOUT)

Reference
Point

Page 15 of 28

Rev. 1.1 Aug. 2005

DDR2 SDRAM

1G A-die DDR2 SDRAM

IDD Specification Parameters and Test Conditions

(IDD values are for full operating range of Voltage and Temperature, Notes 1 - 5)

Symbol

Proposed Conditions

Units

Notes

IDD0

Operating one bank active-precharge current;
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

IDD1

Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD =
tRCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address businputs are SWITCHING; Data pattern
is same as IDD4W

IDD2P

Precharge power-down current;
All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING

IDD2Q

Precharge quiet standby current;
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING

IDD2N

Precharge standby current;
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING

IDD3P

Active power-down current;
All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus
inputs are STABLE; Data bus inputs are FLOATING

Fast PDN Exit MRS(12) = 0mA

Slow PDN Exit MRS(12) = 1mA

IDD3N

Active standby current;
All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING

IDD4W

Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP
= tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus
inputs are SWITCHING

IDD4R

Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRAS-
max(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCH-
ING; Data pattern is same as IDD4W

IDD5B

Burst auto refresh current;
tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid com-
mands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING

IDD6

Self refresh current;
CK and CK\ at 0V; CKE

0.2V; Other control and address bus inputs are

FLOATING; Data bus inputs are FLOATING

Normal

Low Power

IDD7

Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC
= tRC(IDD), tRRD = tRRD(IDD), tFAW = tFAW(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS\ is HIGH between valid
commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the fol-
lowing page for detailed timing conditions

Page 16 of 28

Rev. 1.1 Aug. 2005

DDR2 SDRAM

1G A-die DDR2 SDRAM

Notes :
1. IDD specifications are tested after the device is properly initialized
2. Input slew rate is specified by AC Parametric Test Condition
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS\, RDQS, RDQS\, LDQS, LDQS\, UDQS, and UDQS\. IDD values must be met with all combinations of EMRS

bits 10 and 11.

5. Definitions for IDD

LOW is defined as Vin

VILAC(max)

HIGH is defined as Vin

VIHAC(min)

STABLE is defined as inputs stable at a HIGH or LOW level

FLOATING is defined as inputs at VREF = VDDQ/2

SWITCHING is defined as:

inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and

inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes.

For purposes of IDD testing, the following parameters are utilized

Detailed IDD7
The detailed timings are shown below for IDD7.
Legend: A = Active; RA = Read with Autoprecharge; D = Deselect

IDD7: Operating Current: All Bank Interleave Read operation
All banks are being interleaved at minimum tRC(IDD) without violating tRRD(IDD) and tFAW(IDD) using a burst length of 4. Control and address bus
inputs are STABLE during DESELECTs. IOUT = 0mA

Timing Patterns for 8bank devices x4/ x8
-DDR2-400 3/3/3 : A0 RA0 A1 RA1 A2 RA2 A3 RA3 A4 RA4 A5 RA5 A6 RA6 A7 RA7
-DDR2-533 4/4/4 : A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D
-DDR2-667 5/5/5 : A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D

Timing Patterns for 8bank devices x16
-DDR2-400 3/3/3 : A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D
-DDR2-533 4/4/4 : A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D
-DDR2-667 5/5/5 : A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D

DDR2-667

DDR2-533

DDR2-400

Units

Parameter

5-5-5

4-4-4

3-3-3

CL(IDD)

tCK

tRCD(IDD)

tRC(IDD)

tRRD(IDD)-x4/x8

7.5

tRRD(IDD)-x16

tCK(IDD)

3.75

tRASmin(IDD)

tRP(IDD)

tRFC(IDD)

127.5

Page 17 of 28

Rev. 1.1 Aug. 2005

DDR2 SDRAM

1G A-die DDR2 SDRAM

DDR2 SDRAM IDD Spec Table

Symbol

256Mx4(K4T1G044QA)

Unit

Notes

667@CL=5

533@CL=4

400@CL=3

CE6

LE6

CD5

LD5

CCC

LCC

IDD0

IDD1

100

IDD2P

IDD2Q

IDD2N

IDD3P-F

IDD3P-S

IDD3N

IDD4W

135

120

100

IDD4R

135

120

100

IDD5B

220

215

210

IDD6

IDD7

300

280

260

Symbol

128Mx8(K4T1G084QA)

Unit

Notes

667@CL=5

533@CL=4

400@CL=3

CE6

LE6

CD5

LD5

CCC

LCC

IDD0

IDD1

100

IDD2P

IDD2Q

IDD2N

IDD3P-F

IDD3P-S

IDD3N

IDD4W

155

130

115

IDD4R

155

130

115

IDD5B

220

215

210

IDD6

IDD7

300

280

260

Symbol

64Mx16(K4T1G164QA)

Unit

Notes

667@CL=5

533@CL=4

400@CL=3

CE6

LE6

CD5

LD5

CCC

LCC

IDD0

120

110

105

IDD1

140

130

125

IDD2P

IDD2Q

IDD2N

IDD3P-F

IDD3P-S

IDD3N

IDD4W

195

170

145

IDD4R

200

170

140

IDD5B

220

215

210

IDD6

IDD7

350

340

330

Page 18 of 28

Rev. 1.1 Aug. 2005

DDR2 SDRAM

1G A-die DDR2 SDRAM

Input/Output capacitance

Electrical Characteristics & AC Timing for DDR2-667/533/400

°C < T

CASE

< 95

°C; V

DDQ

= 1.8V + 0.1V; V

= 1.8V + 0.1V)

Refresh Parameters by Device Density

Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin

Parameter

Symbol

DDR2-400/533

DDR2-667

Units

Min

Max

Min

Max

Input capacitance, CK and CK

CCK

1.0

2.0

1.0

2.0

Input capacitance delta, CK and CK

CDCK

0.25

Input capacitance, all other input-only pins

1.0

2.0

1.0

2.0

Input capacitance delta, all other input-only pins

CDI

0.25

Input/output capacitance, DQ, DM, DQS, DQS

CIO

2.5

4.0

2.5

3.5

Input/output capacitance delta, DQ, DM, DQS, DQS

CDIO

0.5

Parameter

Symbol

256Mb

512Mb

1Gb

2Gb

4Gb

Units

Refresh to active/Refresh command time

tRFC

105

127.5

195

327.5

Average periodic refresh interval

tREFI

°C T

CASE

85°C

7.8

µs

°C < T

CASE

95°C

3.9

µs

Speed

DDR2-667(E6)

DDR2-533(D5)

DDR2-400(CC)

Units

Bin (CL - tRCD - tRP)

5 - 5- 5

4 - 4 - 4

3 - 3 - 3

Parameter

min

max

min

max

min

max

tCK, CL=3

tCK, CL=4

3.75

tCK, CL=5

3.75

tRCD

tRP

tRC

tRAS

70000

Page 19 of 28

Rev. 1.1 Aug. 2005

DDR2 SDRAM

1G A-die DDR2 SDRAM

Timing Parameters by Speed Grade

(Refer to notes for informations related to this table at the bottom)

Parameter

Symbol

DDR2-667

DDR2-533

DDR2-400

Units Notes

min

max

min

max

min

max

DQ output access time from CK/CK

tAC

-450

+450

-500

+500

-600

+600

DQS output access time from CK/CK

tDQSCK

-400

+400

-450

+450

-500

+500

CK high-level width

tCH

0.45

0.55

0.45

0.55

0.45

0.55

tCK

CK low-level width

tCL

0.45

0.55

0.45

0.55

0.45

0.55

tCK

CK half period

tHP

min(tCL, tCH)

20,21

Clock cycle time, CL=x

tCK

3000

8000

3750

8000

5000

8000

DQ and DM input hold time

tDH(base)

175

225

275

15,16,

17,20

DQ and DM input setup time

tDS(base)

100

150

15,16,

17,21

Control & Address input pulse width for each input tIPW

0.6

tCK

DQ and DM input pulse width for each input

tDIPW

0.35

tCK

Data-out high-impedance time from CK/CK

tHZ

tAC max

DQS low-impedance time from CK/CK

tLZ(DQS)

tAC min

tAC max

tAC min

tAC max

tAC min

tAC max

DQ low-impedance time from CK/CK

tLZ(DQ)

2*tAC min

tAC max

2* tACmin

tAC max

2* tACmin

tAC max

DQS-DQ skew for DQS and associated DQ signals tDQSQ

240

300

350

DQ hold skew factor

tQHS

340

400

450

DQ/DQS output hold time from DQS

tQH

tHP - tQHS

First DQS latching transition to associated clock
edge

tDQSS

-0.25

0.25

-0.25

0.25

-0.25

0.25

tCK

DQS input high pulse width

tDQSH

0.35

tCK

DQS input low pulse width

tDQSL

0.35

tCK

DQS falling edge to CK setup time

tDSS

0.2

tCK

DQS falling edge hold time from CK

tDSH

0.2

tCK

Mode register set command cycle time

tMRD

tCK

Write postamble

tWPST

0.4

0.6

0.4

0.6

0.4

0.6

tCK

Write preamble

tWPRE

0.35

tCK

Address and control input hold time

tIH(base)

275

375

475

14,16,

18,23

Address and control input setup time

tIS(base)

200

250

350

14,16,

18,22

Read preamble

tRPRE

0.9

1.1

0.9

1.1

0.9

1.1

tCK

Read postamble

tRPST

0.4

0.6

0.4

0.6

0.4

0.6

tCK

Active to active command period for 1KB page size

products

tRRD

7.5

Active to active command period for

2KB page size

products

tRRD

Four Activate Window for 1KB page size products

tFAW

37.5

Four Activate Window for 2KB page size products

tFAW

Page 20 of 28

Rev. 1.1 Aug. 2005

DDR2 SDRAM

1G A-die DDR2 SDRAM

Parameter

Symbol

DDR2-667

DDR2-533

DDR2-400

Units Notes

min

max

min

max

min

max

CAS to CAS command delay

tCCD

tCK

Write recovery time

tWR

Auto precharge write recovery + precharge time

tDAL

WR+tRP

tCK

Internal write to read command delay

tWTR

7.5

Internal read to precharge command delay

tRTP

7.5

Exit self refresh to a non-read command

tXSNR

tRFC + 10

Exit self refresh to a read command

tXSRD

200

tCK

Exit precharge power down to any non-read com-
mand

tXP

tCK

Exit active power down to read command

tXARD

tCK

Exit active power down to read command
(slow exit, lower power)

tXARDS

7 - AL

6 - AL

tCK

9, 10

CKE minimum pulse width
(high and low pulse width)

CKE

tCK

ODT turn-on delay

AOND

tCK

ODT turn-on

AON

tAC(min)

tAC(max)+0.

tAC(min)

tAC(max)+1

tAC(min)

tAC(max)+1

13, 25

ODT turn-on(Power-Down mode)

AONPD

tAC(min)+2

2tCK+tAC(m

ax)+1

tAC(min)+2

2tCK+tAC(m

ax)+1

tAC(min)+2

2tCK+tAC

(max)+1

ODT turn-off delay

AOFD

2.5

tCK

ODT turn-off

AOF

tAC(min)

tAC(max)+

0.6

tAC(min)

tAC(max)+ 0.6

tAC(min)

tAC(max)+ 0.6

ODT turn-off (Power-Down mode)

AOFPD

tAC(min)+2

2.5tCK+tAC(

max)+1

tAC(min)+2

2.5tCK+

tAC(max)+1

tAC(min)+2

2.5tCK+

tAC(max)+1

ODT to power down entry latency

tANPD

tCK

ODT power down exit latency

tAXPD

tCK

OCD drive mode output delay

tOIT

Minimum time clocks remains ON after CKE asyn-
chronously drops LOW

tDelay

tIS+tCK +tIH

Page 21 of 28

Rev. 1.1 Aug. 2005

DDR2 SDRAM

1G A-die DDR2 SDRAM

General notes, which may apply for all AC parameters

1. Slew Rate Measurement Levels

a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended signals. For differential signals

(e.g. DQS - DQS) output slew rate is measured between DQS - DQS = -500 mV and DQS - DQS = +500mV. Output slew rate is guaranteed by design,
but is not necessarily tested on each device.

b. Input slew rate for single ended signals is measured from dc-level to ac-level: from VIL(dc) to VIH(ac) for rising edges and from VIH(dc) and VIL(ac)

for falling edges.

For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = -250 mV to CK - CK = +500 mV (250mV to -500 mV for

falling edges).

c. VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between DQS and DQS for differential

strobe.

2. DDR2 SDRAM AC timing reference load

Following figure represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise

representation of the typical system environment or a depiction of the actual load presented by a production tester. System designers will use IBIS or
other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (gen-
erally a coaxial transmission line terminated at the tester electronics).

The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage level for differential sig-
nals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS) signal.

3. DDR2 SDRAM output slew rate test load

Output slew rate is characterized under the test conditions as shown in the following figure.

VDDQ

DUT

DQS
DQS

RDQS
RDQS

Output

= V

DDQ

Timing

reference

point

VDDQ

DUT

DQS, DQS

RDQS, RDQS

Output

= V

DDQ

Test point

Page 22 of 28

Rev. 1.1 Aug. 2005

DDR2 SDRAM

1G A-die DDR2 SDRAM

4. Differential data strobe

DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS "Enable DQS" mode

bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode
dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode,
these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by
design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied exter-
nally to VSS through a 20 ohm to 10 K ohm resisor to insure proper operation.

5. AC timings are for linear signal transitions.

6. These parameters guarantee device behavior, but they are not necessarily tested on each device. They may be guaranteed by device design or tester
correlation.

7. All voltages are referenced to VSS.

8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply voltage levels, but the related
specifications and device operation are guaranteed for the full voltage range specified.

WPRE

WPST

DQSH

DQSL

DQS

DMin

DQS/

DMin

DQS

(ac)

(dc)

CK/CK

DQS/DQS

DQS

RPST

RPRE

DQSQmax

Page 23 of 28

Rev. 1.1 Aug. 2005

DDR2 SDRAM

1G A-die DDR2 SDRAM

Specific Notes for dedicated AC parameters

9. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be used for fast active power down exit timing.
tXARDS is expected to be used for slow active power down exit timing.
10. AL = Additive Latency

11. This is a minimum requirement. Minimum read to precharge timing is AL + BL/2 providing the tRTP and tRAS(min) have been satisfied.

12. A minimum of two clocks (2 * tCK) is required irrespective of operating frequency

13. Timings are guaranteed with command/address input slew rate of 1.0 V/ns.

14. These parameters guarantee device behavior, but they are not necessarily tested on each device. They may be guaranteed by device design or tester

correlation.

15. Timings are guaranteed with data, mask, and (DQS/RDQS in singled ended mode) input slew rate of 1.0 V/ns.

16. Timings are guaranteed with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals with a differential slew rate of 2.0 V/ns

in differential strobe mode and a slew rate of 1V/ns in single ended mode.

17. tDS and tDH derating Values

For all input signals the total tDS (setup time) and tDH(hold time) required is calculated by adding the datasheet tDS(base) and tDH(base) value to the

delta tDS and delta tDH derating value respectively. Example: tDS(total setup time)= tDS(base) + delta tDS.

tDS, tDH Derating Values of DDR2-400, DDR2-533 (ALL units in `ps', Note 1 applies to entire Table)

DQS,DQS Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4V/ns

1.2V/ns

1.0V/ns

0.8V/ns

tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH

Siew

rate

V/ns

2.0

125

1.5

1.0

0.9

-11

-14

-11

-14

-2

0.8

-25

-31

-13

-19

-1

-7

0.7

-31

-42

-19

-30

-7

-18

-6

0.6

-43

-59

-31

-47

-19

-35

-7

-23

-11

0.5

-74

-89

-62

-77

-50

-65

-38

-53

0.4

-127

-140

-115

-128

-103

-116

tDS, tDH Derating Values for DDR2-667, DDR2-800 (ALL units in `ps', Note 1 applies to entire Table)

DQS,DQS Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4V/ns

1.2V/ns

1.0V/ns

0.8V/ns

tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH

Slew

rate

V/ns

2.0

100

1.5

1.0

0.9

-5

-14

-5

-14

-2

0.8

-13

-31

-1

-19

-7

0.7

-10

-42

-30

-18

-6

0.6

-10

-59

-47

-35

-23

-11

0.5

-24

-89

-12

-77

-65

-53

0.4

-52

-140

-40

-128

-28

-116

Page 24 of 28

Rev. 1.1 Aug. 2005

DDR2 SDRAM

1G A-die DDR2 SDRAM

18. tIS and tIH (input setup and hold) derating.

For all input signals the total tIS (setup time) and tIH(hold time) required is calculated by adding the datasheet tIS(base) and tIH(base) value to the delta

tIS and delta tIH derating value respectively. Example: tIS(total setup time)= tIS(base) + delta tIS.

tIS, tIH Derating Values for DDR2-400, DDR2-533

CK, CK Differential Slew Rate

2.0 V/ns

1.5 V/ns

1.0 V/ns

Units

Notes

tIS

tIH

tIS

tIH

tIS

tIH

Command/

Address Slew

rate(V/ns)

4.0

+187

+94

+217

+124

+247

+154

3.5

+179

+89

+209

+119

+239

+149

3.0

+167

+83

+197

+113

+227

+143

2.5

+150

+75

+180

+105

+210

+135

2.0

+125

+45

+155

+75

+185

+105

1.5

+83

+21

+113

+51

+143

+81

1.0

+30

+60

0.9

-11

-14

+19

+16

+49

+46

0.8

-25

-31

-1

+35

+29

0.7

-43

-54

-13

-24

+17

0.6

-67

-83

-37

-53

-7

-23

0.5

-110

-125

-80

-95

-50

-65

0.4

-175

-188

-145

-158

-115

-128

0.3

-285

-292

-255

-262

-225

-232

0.25

-350

-375

-320

-345

-290

-315

0.2

-525

-500

-495

-470

-465

-440

0.15

-800

-708

-770

-678

-740

-648

tIS and tIH Derating Values for DDR2-667, DDR2-800

CK, CK Differential Slew Rate

2.0 V/ns

1.5 V/ns

1.0 V/ns

Units

Notes

tIS

tIH

tIS

tIH

tIS

tIH

Command/

Address Slew

rate(V/ns)

4.0

+150

+94

+180

+124

+210

+154

3.5

+143

+89

+173

+119

+203

+149

3.0

+133

+83

+163

+113

+193

+143

2.5

+120

+75

+150

+105

+180

+135

2.0

+100

+45

+130

+75

+160

+105

1.5

+67

+21

+97

+51

+127

+81

1.0

+30

+60

0.9

-5

-14

+25

+16

+55

+46

0.8

-13

-31

+17

-1

+47

+29

0.7

-22

-54

-24

+38

0.6

-34

-83

-4

-53

+26

-23

0.5

-60

-125

-30

-95

-65

0.4

-100

-188

-70

-158

-40

-128

0.3

-168

-292

-138

-262

-108

-232

0.25

-200

-375

-170

-345

-140

-315

0.2

-325

-500

-295

-470

-265

-440

0.15

-517

-708

-487

-678

-457

-648

0.1

-1000

-1125

-970

-1095

-940

-1065

Page 25 of 28

Rev. 1.1 Aug. 2005

DDR2 SDRAM

1G A-die DDR2 SDRAM

19. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance
(bus turnaround) will degrade accordingly.

20. MIN ( tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this

value can be

greater than the minimum specification limits for tCL and tCH). For example, tCL and tCH are = 50% of the period, less

the half period jitter ( tJIT(HP))

of the clock source, and less the half period jitter due to crosstalk ( tJIT(crosstalk)) into the clock traces.

21. tQH = tHP tQHS, where:

tHP = minimum half clock period for any given cycle and is defined by clock high or clock low ( tCH, tCL).
tQHS accounts for:

1) The pulse duration distortion of on-chip clock circuits; and
2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately,

due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers.

22. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate
mismatch between DQS / DQS and associated DQ in any given cycle.

23. tDAL = WR + RU{tRP(ns)/tCK(ns)}, where RU stands for round up.

tWR refers to the tWR parameter stored in the MRS. For tRP, if the result of the division is not already an integer, round up to the next highest integer.
tCK refers to the application clock period.
Example: For DDR533 at tCK = 3.75ns with tWR programmed to 4 clocks.

tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.

24. The clock frequency is allowed to change during selfrefresh mode or precharge power-down mode. In case of clock frequency change during pre-
charge power-down, a specific procedure is required as described in DDR2 device operation

25. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.

ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND.

26. ODT turn off time min is when the device starts to turn off ODT resistance.

ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.

27. tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which
specifies when the device output is no longer driving (tHZ), or begins driving (tLZ). Following figure shows a method to calculate the point when device is
no longer driving (tHZ), or begins driving (tLZ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical
as long as the calculation is consistent.

28. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST),
or begins driving (tRPRE). Following figure shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving
(tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent.

These notes are referenced in the "Timing parameters by speed grade" tables for DDR2-400/533 and DDR2-667.

Page 26 of 28

Rev. 1.1 Aug. 2005

DDR2 SDRAM

1G A-die DDR2 SDRAM

29. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the V

IH(ac)

level to the differ-

ential data strobe crosspoint for a rising signal, and from the input signal crossing at the V

IL(ac)

level to the differential data strobe crosspoint for a falling

signal applied to the device under test.

30. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the V

IH(dc)

level to the differ-

ential data strobe crosspoint for a rising signal and V

IL(dc)

to the differential data strobe crosspoint for a falling signal applied to the device under test.

tHZ

tRPST end point

VOH + x mV

VOH + 2x mV

VOL + 2x mV
VOL + x mV

tLZ

tRPRE begin point

VTT + 2x mV

VTT + x mV

VTT - x mV
VTT - 2x mV

tLZ,tRPRE begin point = 2*T1-T2

tHZ,tRPST end point = 2*T1-T2

tDS

DDQ

IH(ac)

min

IH(dc)

min

REF(dc)

IL(dc)

max

IL(ac)

max

DQS

tDH

tDS

tDH

Differential Input waveform timing

Page 27 of 28

Rev. 1.1 Aug. 2005

DDR2 SDRAM

1G A-die DDR2 SDRAM

31. Input waveform timing is referenced from the input signal crossing at the V

IH(ac)

level for a rising signal and V

IL(ac)

for a falling signal applied to the

device under test.

32. Input waverorm timing is referenced from the input signal crossing at the V

IL(dc)

) level for a rising signal and V

(dc) for a falling signal applied to the

device under test.

33. tWTR is at lease two clocks (2 * tCK) independent of operation frequency.

34. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(ac) level to the
single-ended data strobe crossing VIH/L(dc) at the start of its transition for a rising signal, and from the input signal crossing at the VIL(ac) level to the sin-
gle-ended data strobe crossing VIH/L(dc) at the start of its transition for a falling signal applied to the device under test. The DQS signal must be mono-
tonic between Vil(dc)max and Vih(dc)min.

35. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(dc) level to the
single-ended data strobe crossing VIH/L(ac) at the end of its transition for a rising signal, and from the input signal crossing at the VIL(dc) level to the sin-
gle-ended data strobe crossing VIH/L(ac) at the end of its transition for a falling signal applied to the device under test. The DQS signal must be mono-
tonic between Vil(dc)max and Vih(dc)min.

36. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire
time it takes to achieve the 3 clocks of registeration. Thus, after any CKE transition, CKE may not change from its valid level during the time period of tIS
+ 2*tCK + tIH.

tIS

DDQ

IH(ac)

min

IH(dc)

min

REF(dc)

IL(dc)

max

IL(ac)

max

tIH

tIS

tIH

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: K4T1G164QA

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: K4T1G164QA