/home/web/htmldatasheet/RUSSIAN/html/samsung/190410

Page 2 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

Contents

1. Key Feature

2. Package Pinout/Mechnical Dimension & Addressing

2.1 Package Pintout & Mechnical Dimension
2.2 Input/Output Function Description
2.3 Addressing

3. Functional Description

3.1 Simplified State Diagram

3.2 Basic Functionality

3.2.1 Power-Up and Initialization
3.2.2 Programming the Mode Register

3.2.2.1 Mode Register Set(MRS)
3.2.2.2 Extended Mode Register Set(EMRS)
3.2.2.3 OCD Impedance Adjustment-Protocol
3.2.2.4 ODT (On-die termination)

3.2.3 Bank Activate Command
3.2.4 Read and write Access Modes

3.2.4.1 Posted CAS
3.2.4.2 4 bit or 8 bit Burst Mode operation
3.2.4.3 Burst Read opeartion
3.2.4.4 Burst write operation
3.2.4.5 Write data mask

3.2.5 Precharge operation
3.2.6 Auto-Precharge operation
3.2.7 Refresh
3.2.8 Self Refresh
3.2.9 Power Down mode

4. Command Truth Table
5. Absolute Maximum Rating
6. AC & DC Operating Conditions & Specifications

Page 3 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

Revision History

Version 0.0 (Feb, 2002)

- Initial Release

Version 0.1 (Mar, 2002)

- Corrected the typo
- Add FBGA package dimension
- Delete SS800 AC parameter table
- Changed the CAS Latency & Additive Latency

CAS Latency : removed CL=2(Optional) and changed CL=5(Optional) to CL=5 & Added CL=6(Optional)
Additive Latency : Changed AL=4(Optional) to AL=4 & Added AL=5

- Delete tHZ min
- tIH/tIS for DDR2-533 : min 500ps(from TBD)
- tRRD : differentiate 1KB & 2KB page size as 7.5ns & 10ns each
- tWTR : Changed to analog value(400Mbps : 10ns, 533Mbps + : 7.5ns)

Version 0.11 (April, 2002)

- Corrected typo
- Changed Additive Latency definition as below

Old : AL=0(Default), 1,2,3,4 and 5
New : AL=0,1,2,3 and 4

- Added Comment of Max. Package dimension

Maximum Package Height : 21mm
Maximum Package Center to Center spacing : 12.8mm

Version 0.12 (May 2002)

- BL = 8 and corresponding modification
- Added reads interupted by a read and writes interrupted by a write section

Version 0.13 (September, 2002)

- tRTP concept and example timing diagrams are added
- Power down mode session is updated to describe CKE function more clearly
- Command and CKE truth table formats have been changed. No function change
- Self refresh session is updated. Instead of tXP, tXSNR and tXSRD are used. Improvement from previous
version.

- A12 of EMRS(1), Qff function is added as an optional feature.

Version 0.14 (October, 2002)

- Corrected typos

- Added VDLL(Voltage for DLL) in absolute maximum ratings.
- Removed DDR2-667, ss800 AC parameter table.

Version 0.8 (November, 2002)

- Added a description about OCD default mode.
- tRRD is changed from number of clock to "ns", 7.5ns for 1KB page, 10ns for 2KB page size products repec-
tively.
- Added speed bin table and corresponding tRCD, tRP and tRC
- Added differential signal spec (definition and basic timing diagram, V

, V

)

- Power up and initialization sequence is more clearly described.
- Added ODT timing at power down mode.
- Added IDD Specification Parameters and Test Conditions.

Page 5 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

Part Number Information

Note:

* DDR2-400 3-3-3

speed bin is covered by DDR2-533 4-4-4 speed bin

** Speed bin is in order of CL-tRCD-tRP

Organization

DDR2-400 4-4-4**

DDR2-533 5-4-4**

*DDR2-533 4-4-4**

128Mx4

K4T51043QM-GCD4

K4T51043QM-GCE5

K4T51043QM-GCD5

K4T51043QM-GLD4

K4T51043QM-GLE5

K4T51043QM-GLD5

64Mx8

K4T51083QM-GCD4

K4T51083QM-GCE5

K4T51083QM-GCD5

K4T51083QM-GLD4

K4T51083QM-GLE5

K4T51083QM-GLD5

32Mx16

K4T51163QM-GCD4

K4T51163QM-GCE5

K4T51163QM-GCD5

K4T51163QM-GLD4

K4T51163QM-GLE5

K4T51163QM-GLD5

G : BGA

D4 : DDR2-400 4-4-4
D5 : DDR2-533 4-4-4
E5 : DDR2-533 5-4-4

C : (Commercial, Normal)
L : (Commercial, Low)

04 : x4
08 : x8
16 : x16

51 : 512M 8K/64ms

T : DDR2 SDRAM

M : 1st Generation
A : 2nd Generation
B : 3rd Generation
C : 4th Generation
D : 5th Generation
E : 6th Generation

K 4 T XX XX X X X - X X

Memory

DRAM

Small Classification

Density and Refresh

Temperature & Power

Package

Organization

Version

Interface (VDD & VDDQ)

1. SAMSUNG Memory : K
2. DRAM : 4
3. Small Classification

4. Density & Refresh

5. Organization

8. Version

9. Package

10. Temperature & Power

11. Speed

3 : 4 Bank
4 : 8 Bank

6. Bank

1 2 3 4 5 6 7 8 9 10 11

Q: SSTL-18(1.8V, 1.8V)

7. Interface (VDD & VDDQ)

Speed

Bank

Page 6 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

1.Key Features

· JEDEC standard 1.8V ± 0.1V Power Supply

· VDDQ = 1.8V ± 0.1V

· 200 MHz f

for 400Mb/sec/pin & 267MHz f

for 533Mb/sec/pin

· 4 Bank

· Posted CAS

· Programmable CAS Latency: 3, 4, 5

· Programmable Additive Latency: 0, 1 , 2 , 3 and 4

· Write Latency(WL) = Read Latency(RL) -1

· Burst Length: 4 , 8(Interleave/nibble sequential)

· Programmable Sequential / Interleave Burst Mode

· Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)

· Off-Chip Driver(OCD) Impedance Adjustment

· On Die Termination

· Refresh and Self Refresh

Refesh Period 7.8us (8192 refresh cycles/64ms)

· Package: 60ball FBGA - 128Mx4/64Mx8 , 84ball FBGA - 32Mx16

Speed

DDR2-533

4 - 4 - 4

DDR2-533

5 - 4- 4

DDR2-400

4 - 4 - 4

Units

CAS Latency

tCK

tRCD(min)

tRP(min)

tRC(min)

Page 7 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

Description

The 512Mb DDR2 SDRAM chip is organized as either 32Mbit x 4 I/O x 4 banks or 16Mbit x 8 I/O x 4banks or
8Mbit x 16I/O x 4 banks device. This synchronous device achieve high speed double-data-rate transfer rates
of up to 533Mb/sec/pin (DDR2-533) for general applications.
The chip is designed to comply with the following key DDR2 SDRAM features: (1) posted CAS with additive
latency, (2) write latency = read latency -1, (3) Off-Chip Driver(OCD) impedance adjustment, (4) On Die Ter-
mination.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks.
Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized
with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fashion. A fourteen bit address
bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style. For
example, 512Mb(x4) device receive 14/11/2 addressing.
The 512Mb DDR2 devices operate with a single 1.8V ± 0.1V power supply and 1.8V ± 0.1V VDDQ.
The 512Mb DDR2 devices are available in 60ball FBGAs(x4/8) and in 84ball FBGAs(x16). Refresh and Self
Refresh operations of 8192 refresh cycles per 64ms are supported. (Refresh Period 7.8us)

Note: The functionality described and the timing specifications included in this data sheet are for the DLL
Enabled mode of operation.

Page 8 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

2. Package Pinout/Mechnical Dimension & Addressing

2.1 Package Pinout

x4 package pinout (Top View) : 60ball FBGA Package

Notes:
B1, B9, D1, D9 = NC for x4 organization.
Pins B3 has identical capacitance as pins B7.
VDDL and VSSDL are power and ground for the DLL. It is recommended that they are isolated on the device from
VDD, VDDQ, VSS, and VSSQ.

VDD

VSS

VSSQ

VDDQ

VSSQ

DQS

DQ0

VDDQ

DQ2

VSSQ

VSSDL

VDD

RAS

CAS

A11

A13

A12

VDD

A10

VSS

VDDQ

VSSQ

DQ1

DQ3

VDDL

BA1

VREF

VSS

CKE

BA0

1 2 3 7 8 9

VDD

VSS

ODT

+
+
+
+
+
+
+
+
+

+
+

Ball Locations (x4)

: Populated Ball

+ : Depopulated Ball

Top View (See the balls through the Package)

Page 9 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

Notes:
1.

Pins B3 and A2 have identical capacitance as pins B7 and A8.

For a read, when enabled, strobe pair RDQS & RDQS are identical in function and timing to strobe pair DQS
& DQS and input masking function is disabled.

The function of DM or RDQS/RDQS are enabled by EMRS command.

VDDL and VSSDL are power and ground for the DLL. It is recommended that they are isolated on the device
from VDD, VDDQ, VSS, and VSSQ.

x8 package pinout (Top View) : 60ball FBGA Package

VDD

NU/

VSS

DQ6

VSSQ

VDDQ

VSSQ

DQS

DQ7

DQ0

VDDQ

DQ2

VSSQ

DQ5

VSSDL

VDD

RAS

CAS

A11

A13

A12

VDD

A10

VSS

VDDQ

VSSQ

DQ1

DQ3

DQ4

VDDL

BA1

VREF

VSS

CKE

BA0

1 2 3 7 8 9

VDD

VSS

DM/

RDQS

ODT

+
+
+
+
+
+
+
+
+

Ball Locations (x8)

: Populated Ball

+ : Depopulated Ball

Top View (See the balls through the Package)

Page 10 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

VDD

VSS

LDQ6

VSSQ

LDM

VDDQ

VSSQ

LDQS

LDQ7

LDQ0

VDDQ

LDQ2

VSSQ

LDQ5

VSSDL

VDD

RAS

CAS

A11

A12

VDD

A10

VSS

VDDQ

VSSQ

LDQ1

LDQ3

LDQ4

VDDL

BA1

VREF

VSS

CKE

BA0

1 2 3 7 8 9

VDD

VSS

VDD

VSS

UDQ6

VSSQ

UDM

VDDQ

VSSQ

UDQ1

UDQ3

UDQ4

VDDQ

VSSQ

UDQS

UDQ7

UDQ0

VDDQ

UDQ2

VSSQ

UDQ5

ODT

Notes:
VDDL and VSSDL are power and ground for the DLL. lt is recommended that they are isolated on the device
from VDD, VDDQ, VSS, and VSSQ.

x16 package pinout (Top View) : 84ball FBGA Package

+
+
+
+
+
+

+
+

+
+
+
+
+
+

+
+
+

+
+
+
+
+
+

+
+
+

: Populated Ball

+ : Depopulated Ball

Top View

Ball Locations (x16)

(See the balls through the Package)

Page 13 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

2.2 Input/Output Functional Description

Symbol

Type

Function

CK, CK

Input

Clock: CK and CK are differential clock inputs. All address and control input signals are sampled
on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is refer-
enced to the crossings of CK and CK (both directions of crossing).

CKE

Input

Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device
input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self
Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is syn-
chronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self
refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers,
excluding CK, CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE,
are disabled during self refresh.

Input

Chip Select: All commands are masked when CS is registered HIGH. CS provides for external
Rank selection on systems with multiple Ranks. CS is considered part of the command code.

ODT

Input

On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2
SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS, RDQS, RDQS, and DM
signal for x4x8 configurations. For x16 configuration ODT is applied to each DQ, UDQS/UDQS,
LDQS/LDQS, UDM, and LDM signal. The ODT pin will be ignored if the Extended Mode Register
(EMRS) is programmed to disable ODT.

RAS, CAS, WE

Input

Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.

Input

Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH coincident with that input data during a Write access. DM is sampled on both
edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS load-
ing. For x8 device, the function of DM or RDQS/RDQS is enabled by EMRS command.

BA0 - BA2

Input

Bank Address Inputs: BA0 and BA1 for 256 and 512Mb, BA0 - BA2 define to which bank an
Active, Read, Write or Precharge command is being applied. Bank address also determines if the
mode register or extended mode register is to be accessed during a MRS or EMRS cycle.

A0 - A15

Input

Address Inputs: Provided the row address for Active commands and the column address and
Auto Precharge bit for Read/Write commands to select one location out of the memory array in the
respective bank. A10 is sampled during a Precharge command to determine whether the Pre-
charge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be pre-
charged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during
Mode Register Set commands.

Input/Output Data Input/ Output: Bi-directional data bus.

DQS, (DQS)

(LDQS), (LDQS)

(UDQS), (UDQS)
(RDQS), (RDQS)

Input/Output

Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in
write data. For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS corresponds to the
data on DQ8-DQ15. For the x8, an RDQS option using DM pin can be enabled via the EMRS(1) to
simplify read timing. The data strobes DQS, LDQS, UDQS, and RDQS may be used in single
ended mode or paired with optional complementary signals DQS, LDQS, UDQS, and RDQS to
provide differential pair signaling to the system during both reads and writes. An EMRS(1) control
bit enables or disables all complementary data strobe signals.

No Connect: No internal electrical connection is present.

DDQ

Supply

DQ Power Supply: 1.8V +/- 0.1V

SSQ

Supply

DQ Ground

DDL

Supply

DLL Power Supply: 1.8V +/- 0.1V

SSDL

Supply

DLL Ground

Supply

Power Supply: 1.8V +/- 0.1V

Supply

Ground

REF

Supply

Reference voltage

In this data sheet, "differential DQS signals" refers to any of the following with A10 = 0 of EMRS(1)

x4 DQS/DQS

x8 DQS/DQS

if EMRS(1)[A11] = 0

x8 DQS/DQS, RDQS/RDQS,

if EMRS(1)[A11] = 1

x16 LDQS/LDQS and UDQS/UDQS

"single-ended DQS signals" refers to any of the following with A10 = 1 of EMRS(1)

x4 DQS

x8 DQS

if EMRS(1) [A11] = 0

x8 DQS, RDQS,

if EMRS(1) [A11] = 1

x16 LDQS and UDQS

Page 14 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

2.3 512Mb Addressing

* Reference information: The following tables are address mapping information for other densities.

256Mb

1Gb

2Gb

4Gb

Configuration

128Mb x4

64Mb x 8

32Mb x16

# of Bank

Bank Address

BA0,BA1

Auto precharge

/AP

Row Address

~ A

Column Address

~ A

Configuration

64Mb x4

32Mb x 8

16Mb x16

# of Bank

Bank Address

BA0,BA1

Auto precharge

/AP

Row Address

~ A

Column Address

~ A

Configuration

256Mb x4

128Mb x 8

64Mb x16

# of Bank

Bank Address

BA0 ~ BA2

Auto precharge

/AP

Row Address

~ A

Column Address

~ A

Configuration

512Mb x4

256Mb x 8

128Mb x16

# of Bank

Bank Address

BA0 ~ BA2

Auto precharge

/AP

Row Address

~ A

Column Address

~ A

Configuration

1 Gb x4

512Mb x 8

256Mb x16

# of Bank

Bank Address

BA0 ~ BA2

Auto precharge

/AP

Row Address

tbd

Column Address/page size

tbd

Page 15 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

Self

Idle

Setting

EMRS

Bank

Precharging

Power

Writing

ACT

RDA

Read

SRF

REF

CKEL

MRS

CKEH

CKEL

Write

Automatic Sequence

Command Sequence

RDA

WRA

Read

PR, PRA

Refreshing

Down

Power

Down

Active

with

RDA

Reading

with

WRA

Active

Precharge

Reading

Writing

PR(A) = Precharge (All)

MRS = (Extended) Mode Register Set
SRF = Enter Self Refresh
REF = Refresh

CKEL = CKE low, enter Power Down
CKEH = CKE high, exit Power Down, exit Self Refresh
ACT = Activate
WR(A) = Write (with Autoprecharge)
RD(A) = Read (with Autoprecharge)

Note: Use caution with this diagram. It is indented to provide a floorplan of the possible state transitions

3.1 Simplified State Diagram

3. Functional Description

All banks

precharged

Activating

CKEH

Read

Write

CKEL

MRS

CKEL

Sequence

Initialization

OCD

calibration

CKEL

Autoprecharge

PR, PRA

and the commands to control them, not all details. In particular situations involving more than one bank,

enabling/disabling on-die termination, Power Down enty/exit - among other things - are not captured
in full detail.

Page 16 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

3.2 Basic Functionality

Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and

continue for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of

an Active command, which is then followed by a Read or Write command. The address bits registered coinci-

dent with the active command are used to select the bank and row to be accessed (BA0, BA1 select the bank;

A0-A13 select the row). The address bits registered coincident with the Read or Write command are used to

select the starting column location for the burst access and to determine if the auto precharge command is to

be issued.

Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed infor-

mation covering device initialization, register definition, command descriptions and device operation.

3.2.1 Power up and Initialization

DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other
than those specified may result in undefined operation.

Power-up and Initialization Sequence

The following sequence is required for POWER UP and Initialization.

1. Apply power and attempt to maintain CKE below 0.2*VDDQ and ODT

at a low state (all other inputs

may be undefined.)

- VDD, VDDL and VDDQ are driven from a single power converter output, AND
- VTT is limited to 0.95 V max, AND
- Vref tracks VDDQ/2.

- Apply VDD before or at the same time as VDDL.
- Apply VDDL before or at the same time as VDDQ.
- Apply VDDQ before or at the same time as VTT & Vref.

at least one of these two sets of conditions must be met.

2. Start clock and maintain stable condition.
3. For the minimum of 200

s after stable power and clock(CK, CK), then apply NOP or deselect & take CKE

high.

4. Wait minimum of 400ns then issue precharge all command. NOP or deselect applied during 400ns

period.

5. Issue EMRS(2) command. (To issue EMRS(2) command, provide "Low" to BA0, "High" to BA1.)
6. Issue EMRS(3) command. (To issue EMRS(3) command, provide "High" to BA0 and BA1.)
7. Issue EMRS to enable DLL. (To issue "DLL Enable" command, provide "Low" to A0, "High" to BA0 and

"Low" to BA1 and A12.)

8. Issue a Mode Register Set command for "DLL reset".

(To issue DLL reset command, provide "High" to A8 and "Low" to BA0-1)

9. Issue precharge all command.

10. Issue 2 or more auto-refresh commands.

11. Issue a mode register set command with low to A8 to initialize device operation. (i.e. to program operating

parameters without resetting the DLL.

12. At least 200 clocks after step 8, execute OCD Calibration ( Off Chip Driver impedance adjustment ).

If OCD calibration is not used, EMRS OCD Default command (A9=A8= A7=1) followed by EMRS OCD

Page 17 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

Calibration Mode Exit command (A9=A8=A7=0) must be issued with other operating parameters of
EMRS.

13. The DDR2 SDRAM is now ready for normal operation.

*1) To guarantee ODT off, VREF must be valid and a low level must be applied to the ODT pin.

3.2.2 Programming the Mode Register

For application flexibility, burst length, burst type, CAS latency, DLL reset function, write recovery time(tWR)

are user defined variables and must be programmed with a Mode Register Set (MRS) command. Addition-

ally, DLL disable function, driver impedance, additive CAS latency, ODT(On Die Termination), single-ended

strobe, and OCD(off chip driver impedance adjustment) are also user defined variables and must be pro-

grammed with an Extended Mode Register Set (EMRS) command. Contents of the Mode Register(MR) or

Extended Mode Registers(EMR(#)) can be altered by re-executing the MRS and EMRS Commands. If the

user chooses to modify only a subset of the MRS or EMRS variables, all variables must be redefined when

the MRS or EMRS commands are issued.

MRS, EMRS and Reset DLL do not affect array contents, which means reinitialization including those can be

executed any time after power-up without affecting array contents.

Initialization Sequence after Power Up

/CK

CKE

Command

PRE
ALL

EMRS

MRS

REF

MRS

EMRS

ANY
CMD

DLL
ENABLE

DLL
RESET

OCD
Default

OCD
CAL. MODE
EXIT

Follow OCD
Flowchart

400ns

tRFC

tRP

tMRD

tOIT

min. 200 Cycle

NOP

ODT

tCL

tCH

tIS

Page 18 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

3.2.2.1 DDR2 SDRAM Mode Register Set (MRS)

The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls

CAS latency, burst length, burst sequence, test mode, DLL reset, tWR and various vendor specific options to

make DDR2 SDRAM useful for various applications. The default value of the mode register is not defined,

therefore the mode register must be written after power-up for proper operation. The mode register is written

by asserting low on CS, RAS, CAS, WE, BA0 and BA1, while controlling the state of address pins A0 ~ A15.

The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the mode reg-

ister. The mode register set command cycle time (tMRD) is required to complete the write operation to the

mode register. The mode register contents can be changed using the same command and clock cycle

requirements during normal operation as long as all banks are in the precharge state. The mode register is

divided into various fields depending on functionality. Burst length is defined by A0 ~ A2 with options of 4 and

8 bit burst lengths. The burst length decodes are compatible with DDR SDRAM. Burst address sequence type

is defined by A3, CAS latency is defined by A4 ~ A6. The DDR2 doesn't support half clock latency mode. A7

is used for test mode. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Write recov-

ery time tWR is defined by A9 ~ A11. Refer to the table for specific codes.

Address Field

CAS Latency

Latency

Reserved

mode

Normal

Test

Burst Type

Sequential

Interleave

DLL Reset

Yes

Mode Register

CAS Latency

DLL

Write recovery for autoprecharge

WR(cycles)

Reserved

Burst Length

Burst Length

*1 : A13 is reserved for future use and must be programmed to 0 when setting the mode register.

BA2 and A14 are not used for 512Mb, but used for 1Gb and 2Gb DDR2 SDRAMs. A15 is reserved for future

usage.

*2 : WR(write recovery for autoprecharge) min is determined by tCK max and WR max is determined by tCK min.

WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up a non-integer value to

the next integer (WR[cycles] = tWR(ns)/tCK(ns)). The mode register must be programmed to this value. This is

also used with tRP to determine tDAL.

BA1

BA0

MRS mode

MRS

EMRS(1)

EMRS(2): Reserved

EMRS(3): Reserved

R2-400

DR2-533

DDR

2-667

R2-800

Active power
down exit time

Fast exit(use t

XARD

)

Slow exit(use t

XARDS

)

Page 19 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

3.2.2.2 DDR2 SDRAM Extended Mode Register Set

EMRS(1)

The extended mode register(1) stores the data for enabling or disabling the DLL, output driver strength, ODT

value selection and additive latency. The default value of the extended mode register is not defined, therefore

the extended mode register must be written after power-up for proper operation. The extended mode register

is written by asserting low on CS, RAS, CAS, WE and high on BA0, while controlling the states of address

pins A0 ~ A13. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into

the extended mode register. The mode register set command cycle time (tMRD) must be satisfied to com-

plete the write operation to the extended mode register. Mode register contents can be changed using the

same command and clock cycle requirements during normal operation as long as all banks are in the pre-

charge state. A0 is used for DLL enable or disable. A1 is used for enabling a half strength data-output driver.

A3~A5 determines the additive latency, A2 and A6 are used for ODT value selection, A7~A9 are used for

OCD control, A10 is used for DQS# disable and A11 is used for RDQS enable.

DLL Enable/Disable

The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and

upon returning to normal operation after having the DLL disabled. The DLL is automatically disabled when

entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time

the DLL is enabled (and subsequently reset), 200 clock cycles must occur before a Read command can be

issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for syn-

chronization to occur may result in a violation of the tAC or tDQSCK parameters.

Page 20 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

*1 : A13 is reserved for future use and must be programmed to 0 when setting the mode register.

BA2 and A14 are not used for 512Mb, but used for 1Gb and 2Gb DDR2 SDRAMs. A15 is reserved for future

usage.

Address Field

RDQS

Extended Mode Register

DLL

D.I.C

DLL Enable

Enable

Disable

Additive latency

Additive Latency

Reserved

a: When Adjust mode is issued, AL from previously set value must be applied.
b: After setting to default, OCD mode needs to be exited by setting A9-A7 to
000. Refer to the following 3.2.2.3 section for detailed information

A9 A8 A7

OCD Calibration Program

0 OCD Calibration mode exit; maintain setting

1 Drive(1)

0 Drive(0)

0 Adjust mode

1 OCD Calibration default

OCD program

DQS

Rtt

Output Driver

Impedence Control

Driver

Size

Normal 100%

Weak

60%

A10

DQS

Enable

Disable

* If RDQS is enabled, the

DM function is disabled. RDQS
is active for reads and don't
care for writes.

A11

RDQS Enable

Disable

Enable

A2 R

(

NOMINAL

)

ODT Disabled

75 ohm

150 ohm

Reserved

BA1

BA0

MRS mode

MRS

EMRS(1)

EMRS(2): Reserved

EMRS(3): Reserved

EMRS(1) Programming

Qoff

Qoff (Optional)

a. Outputs disabled - DQs, DQSs, DQSs,

RDQS, RDQS. This feature is used in
conjunction with dimm IDD meaurements when
IDDQ is not desired to be included.

Output buffer enabled

Output buffer disabled

A11

(RDQS Enable)

A10

(DQS Enable)

Strobe Function Matrix

RDQS/DM

RDQS

DQS

0 (Disable)

0 (Enable)

Hi-z

DQS

0 (Disable)

1 (Disable)

Hi-z

DQS

Hi-z

1 (Enable)

0 (Enable)

RDQS

DQS

1 (Enable)

1 (Disable)

RDQS

Hi-z

DQS

Hi-z

Page 21 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

Address Field

Extended Mode Register(2)

2 ~

*1 : EMRS(2) is reserved for future use and all bits except BA0 and BA1 must be programmed to 0 when setting

the mode register during initialization.

*2 : BA2 and A14 are not used for 512Mb, but used for 1Gb and 2Gb DDR2 SDRAMs. A15 is reserved for future

usage.

EMRS(2) Programming: Reserved

Address Field

Extended Mode Register(3)

*1 : EMRS(3) is reserved for future use and all bits except BA0 and BA1 must be programmed to 0 when setting

the mode register during initialization.

*2 : BA2 and A14 are not used for 512Mb, but used for 1Gb and 2Gb DDR2 SDRAMs. A15 is reserved for future

usage.

EMRS(3) Programming: Reserved

0 *

2 ~

0 *

Page 22 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

3.2.2.3 Off-Chip Driver (OCD) Impedance Adjustment

DDR2 SDRAM supports driver calibration feature and the flow chart below is an example of sequence. Every
calibration mode command should be followed by "OCD calibration mode exit" before any other command

being issued.

MRS should be set before entering OCD impedance adjustment and ODT (On Die Termian-

tion) should be carefully controlled depending on system environment.

Start

EMRS: Drive(1)

DQ & DQS High; DQS Low

Test

EMRS :

Enter Adjust Mode

BL=4 code input to all DQs

Inc, Dec, or NOP

EMRS: Drive(0)

DQ & DQS Low; DQS High

Test

EMRS :

Enter Adjust Mode

BL=4 code input to all DQs

Inc, Dec, or NOP

EMRS: OCD calibration mode exit

End

ALL OK

Need Calibration

EMRS: OCD calibration mode exit

MRS shoud be set before entering OCD impedance adjustment and ODT should

be carefully controlled depending on system environment

Page 23 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

Extended Mode Register Set for OCD impedance adjustment

OCD impedance adjustment can be done using the following EMRS mode. In drive mode all outputs

are driven out by DDR2 SDRAM and drive of RDQS is depedent on EMRS bit enabling RDQS operation. In
Drive(1) mode, all DQ, DQS (and RDQS) signals are driven high and all DQS signals are driven low. In
drive(0) mode, all DQ, DQS (and RDQS) signals are driven low and all DQS signals are driven high. In adjust
mode, BL = 4 of operation code data must be used. In case of OCD calibration default, output driver charac-
teristics have a nominal impedance value of 18 ohms during nominal temperature and voltage conditions.
Output driver characteristics for OCD calibration default are specified in section 6. OCD applies only to nor-
mal full strength output drive setting defined by EMRS(1) and if half strength is set, OCD default output driver
characteristics are not applicable. When OCD calibration adjust mode is used, OCD default output driver
characteristics are not applicable. After OCD calibration is completed or driver strength is set to default,
subsequent EMRS commands not intended to adjust OCD characteristics must specify A9-A7 as '000' in
order to maintain the default or calibrated value.

Off- Chip-Driver program

OCD impedance adjust

To adjust output driver impedance, controllers must issue the ADJUST EMRS command along with a 4bit
burst code to DDR2 SDRAM as in the folowing table. For this operation, Burst Length has to be set to BL = 4
via MRS command before activating OCD and controllers must drive this burst code to all DQs at the same
time. DT0 in the following table means all DQ bits at bit time 0, DT1 at bit time 1, and so forth. The driver out-
put impedance is adjusted for all DDR2 SDRAM DQs simultaneously and after OCD calibration, all DQs of a
given DDR2 SDRAM will be adjusted to the same driver strength setting. The maximum step count for adjust-
ment is 16 and when the limit is reached, further increment or decrement code has no effect. The default set-
ting may be any step within the 16 step range. When Adjust mode command is issued, AL from previously set
value must be applied

Off- Chip-Driver Program

Operation

OCD calibration mode exit

Drive(1) DQ, DQS, (RDQS) high and DQS low

Drive(0) DQ, DQS, (RDQS) low and DQS high

Adjust mode

OCD calibration default

4bit burst code inputs to all DQs

Operation

Pull-up driver strength

Pull-down driver strength

NOP (No operation)

Increase by 1 step

NOP

Decrease by 1 step

NOP

Increase by 1 step

NOP

Decrease by 1 step

Increase by 1 step

Decrease by 1 step

Increase by 1 step

Page 24 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

For proper operation of adjust mode, WL = RL - 1 = AL + CL - 1 clocks and tDS/tDH should be met as the fol-
lowing timing diagram. For input data pattern for adjustment, DT0 - DT3 is a fixed order and "not affected by
MRS addressing mode (ie. sequential or interleave).

Drive Mode

Drive mode, both Drive(1) and Drive(0), is used for controllers to measure DDR2 SDRAM Driver impedance.
In this mode, all outputs are driven out tOIT after "enter drive mode" command and all output drivers are
turned-off tOIT after "OCD calibration mode exit" command as the following timing diagram.

Increase by 1 step

Decrease by 1 step

Other Combinations

Reserved

NOP

EMRS

CMD

DQS_in

DQ_in

tDS tDH

OCD adjust mode

OCD calibration mode exit

EMRS

NOP

DQS

EMRS

NOP

EMRS

CMD

DQS

Enter Drive mode

OCD calibration mode exit

tOIT

Hi-Z

DQs high for Drive(1)

DQS high & DQS low for Drive(1), DQS low & DQS high for Drive(0)

Hi-Z

DQs low for Drive(0)

tOIT

DQS

Page 25 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

3.2.2.4 ODT (On Die Termination)

On Die Termination (ODT) is a feature that allows a DRAM to turn on/off termination resistance for each DQ,
DQS/DQS, RDQS/RDQS, and DM signal for x4/x8 configurations via the ODT control pin. For x16 configu-
ration ODT is applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM signal via the ODT control
pin. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM
controller to independently turn on/off termination resistance for any or all DRAM devices.
The ODT function is supported for ACTIVE and STANDBY modes, and turned off and not supported in SELF
REFRESH mode.

Functional Representation of ODT

ODT DC Electrical Characteristics

Note 1: Test condition for Rtt measurements

Measurement Definition for Rtt(eff):

Apply V

(ac) and V

(ac) to test pin separately, then measure current I(V

(ac)) and I(

(ac)) respectively. V

(ac)

, and VDDQ values defined in SSTL_18

Measurement Definition for VM:

Measure voltage (V

) at test pin (midpoint) with no load.

Parameter/Condition

Symbol

Min

Nom

Max

Units

Notes

Rtt effective impedance value for EMRS(A6,A2)=0,1; 75 ohm

Rtt1(eff)

ohm

Rtt effective impedance value for EMRS(A6,A2)=1,0; 150 ohm

Rtt2(eff)

120

150

180

ohm

Rtt mismatch tolerance between any pull-up/pull-down pair

Rtt(mis)

-3.75

+3.75

Input

DRAM

Rval2

Rval1

sw1

sw2

Selection between sw1 or sw2 is determined by "Rtt (nominal)" in EMRS

Termination included on all DQs, DM, DQS, DQS, RDQS, and RDQS pins.

Switch sw1 or sw2 is enabled by ODT pin.

Target Rtt (ohm) = (Rval1) / 2 or (Rval2) / 2

Input

Buffer

Rtt(eff) =

(ac)

) - I(

(ac)

)

delta VM =

2 x Vm

VDDQ

x 100%

- 1

Page 29 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

3.2.3 Bank Activate Command

The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge
of the clock. The bank addresses BA0 and BA1, are used to select the desired bank. The row address A0
through A13 is used to determine which row to activate in the selected bank. The Bank Activate command
must be applied before any Read or Write operation can be executed. Immediately after the bank active
command, the DDR2 SDRAM can accept a read or write command on the following clock cycle. If a R/W
command is issued to a bank that has not satisfied the tRCDmin specification, then additive latency must be
programmed into the device to delay when the R/W command is internally issued to the device. The additive
latency value must be chosen to assure tRCDmin is satisfied. Additive latencies of 0, 1, 2, 3, 4 are sup-
ported. Once a bank has been activated it must be precharged before another Bank Activate command can
be applied to the same bank. The bank active and precharge times are defined as tRAS and tRP, respec-
tively. The minimum time interval between successive Bank Activate commands to the same bank is deter-
mined by the RAS cycle time of the device (t

). The minimum time interval between Bank Activate

commands is t

RRD

Bank Activate Command Cycle: tRCD = 3, AL = 2, tRP = 3, tRRD = 2, tCCD = 2

ADDRESS

CK / CK

Tn+1

Tn+2

Tn+3

COMMAND

Bank A

Row Addr.

Bank A

Activate

Bank A

Col. Addr.

. . . . . . . . . .

Internal RAS-CAS delay (>=

RCDmin

)

: "H" or "L"

RAS Cycle time (

>= t

)

additive latency delay (

)

Read A

Post CAS

Bank B

Row Addr.

Bank B

Activate

Bank B

Col. Addr.

Read B

Post CAS

Bank A

Precharge

Bank B

Addr.

Bank B

Precharge

Bank A

Row Addr.

Active

Bank A

RAS - RAS delay time (

>= t

RRD

)

Read Begins

RCD =1

Addr.

Bank Active

(>= t

RAS

)

Bank Precharge time (

>= t

)

CAS-CAS delay time (

CCD

)

Page 30 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

3.2.4 Read and Write Access Modes

After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS
high, CS and CAS low at the clock's rising edge. WE must also be defined at this time to determine whether
the access cycle is a read operation (WE high) or a write operation (WE low).

The DDR2 SDRAM provides a fast column access operation. A single Read or Write Command will initiate a
serial read or write operation on successive clock cycles. The boundary of the burst cycle is strictly restricted
to specific segments of the page length. For example, the 32Mbit x 4 I/O x 4 Bank chip has a page length of
2048 bits (defined by CA0-CA9, CA11). The page length of 2048 is divided into 512 or 256 uniquely addres-
sable boundary segments depending on burst length, 512 for 4 bit burst, 256 for 8 bit burst respectively. A 4-
bit or 8 bit burst operation will occur entirely within one of the 512 or 256 groups beginning with the column
address supplied to the device during the Read or Write Command (CA0-CA9, CA11). The second, third and
fourth access will also occur within this group segment, however, the burst order is a function of the starting
address, and the burst sequence.

A new burst access must not interrupt the previous 4 bit burst operation in case of BL = 4 setting. However,
in case of BL = 8 setting, two cases of interrupt by a new burst access are allowed, one reads interrupted by
a read, the other writes interrupted by a write with 4 bit burst boundry respectively. The minimum CAS to
CAS delay is defined by tCCD, and is a minimum of 2 clocks for read or write cycles.

Page 31 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

3.2.4.1 Posted CAS

Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in
DDR2 SDRAM. In this operation, the DDR2 SDRAM allows a CAS read or write command to be issued
immediately after the RAS bank activate command (or any time during the RAS-CAS-delay time, tRCD,
period). The command is held for the time of the Additive Latency (AL) before it is issued inside the device.
The Read Latency (RL) is controlled by the sum of AL and the CAS latency (CL). Therefore if a user chooses
to issue a R/W command before the tRCDmin, then AL (greater than 0) must be written into the EMR(1). The
Write Latency (WL) is always defined as RL - 1 (read latency -1) where read latency is defined as the sum of
additive latency plus CAS latency (RL=AL+CL).

Read or Write operations using AL allow seamless bursts (refer to

semaless operation timing diagram examples in Read burst and Wirte burst section)

Examples of posted CAS operation

Example 1 Read followed by a write to the same bank

[AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4]

Example 2 Read followed by a write to the same bank

[AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2]

Active

A-Bank

Read

A-Bank

Write

A-Bank

Dout0

Dout1

Dout2

Dout3

Din0

Din1

Din2

Din3

CK/CK

CMD

DQS/DQS

AL = 2

-1

> = tRCD

CL = 3

> = tRAC

WL = RL -1 = 4

RL = AL + CL = 5

Active

A-Bank

Read

A-Bank

Write

A-Bank

Dout0

Dout1

Dout2

Dout3

Din0

Din1

Din2

Din3

AL = 0

> = tRCD

CL = 3

> = tRAC

WL = RL -1 = 2

RL = AL + CL = 3

-1

CK/CK

CMD

DQS/DQS

Page 32 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

3.2.4.2 Burst Mode Operation

Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from
memory locations (read cycle). The parameters that define how the burst mode will operate are burst
sequence and burst length. DDR2 SDRAM supports 4 bit burst and 8 bit burst modes only. For 8 bit burst
mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for
ease of implementation. The burst type, either sequential or interleaved, is programmable and defined by the
address bit 3 (A3) of the MRS, which is similar to the DDR SDRAM operation. Seamless burst read or write
operations are supported. Unlike DDR devices, interruption of a burst read or write cycle during BL = 4 mode
operation is prohibited. However in case of BL = 8 mode, interruption of a burst read or write operation is lim-
ited to two cases, reads interrupted by a read, or writes interrupted by a write. Therefore the Burst Stop com-
mand is not supported on DDR2 SDRAM devices.

Burst Length and Sequence

Note: Page length is a function of I/O organization and column addressing

Burst Length

Starting Address (A2 A1 A0)

Sequential Addressing (decimal)

Interleave Addressing (decimal)

0 0 0

0, 1, 2, 3

0 0 1

1, 2, 3, 0

1, 0, 3, 2

0 1 0

2, 3, 0, 1

0 1 1

3, 0, 1, 2

3, 2, 1, 0

0 0 0

0, 1, 2, 3, 4, 5, 6, 7

0 0 1

1, 2, 3, 0, 5, 6, 7, 4

1, 0, 3, 2, 5, 4, 7, 6

0 1 0

2, 3, 0, 1, 6, 7, 4, 5

0 1 1

3, 0, 1, 2, 7, 4, 5, 6

3, 2, 1, 0, 7, 6, 5, 4

1 0 0

4, 5, 6, 7, 0, 1, 2, 3

1 0 1

5, 6, 7, 4, 1, 2, 3, 0

5, 4, 7, 6, 1, 0, 3, 2

1 1 0

6, 7, 4, 5, 2, 3, 0, 1

1 1 1

7, 4, 5, 6, 3, 0, 1, 2

7, 6, 5, 4, 3, 2, 1, 0

Page 33 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

3.2.4.3 Burst Read Command

The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising

edge of the clock. The address inputs determine the starting column address for the burst. The delay from the

start of the command to when the data from the first cell appears on the outputs is equal to the value of the

read latency (RL). The data strobe output (DQS) is driven low 1 clock cycle before valid data (DQ) is driven

onto the data bus. The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each

subsequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner.

The RL is equal to an additive latency (AL) plus CAS latency (CL). The CL is defined by the Mode Register

Set (MRS), similar to the existing SDR and DDR SDRAMs. The AL is defined by the Extended Mode Register

Set (1)(EMRS(1)).

DDR2 SDRAM pin timings are specified for either single ended mode or differen-tial mode depending on

the setting of the EMRS "Enable DQS" mode bit; timing advantages of differential mode are realized in sys-
tem design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single
ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at V

REF

In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its com-
plement, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that
when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied
externally to VSS through a 20 ohm to 10 Kohm resis-tor to insure proper operation.

DQS

RPST

RPRE

DQSQmax

Data output (read) timing

Burst Read Operation: RL = 5 (AL = 2, CL = 3, BL = 4)

CMD

NOP

DQs

NOP

CK/CK

DOUT A

READ A

Posted CAS

AL = 2

CL =3

RL = 5

DQS

=< t

DQSCK

Page 34 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

Burst Read Operation: RL = 3 (AL = 0 and CL = 3, BL = 8)

Burst Read followed by Burst Write: RL = 5, WL = (RL-1) = 4, BL = 4

The minimum time from the burst read command to the burst write command is defined by a read-to-write-
turn-around-time, which is 4 clocks in case of BL = 4 operation, 6 clocks in case of BL = 8 operation.

CMD

NOP

DQs

NOP

CK/CK

DOUT A

READ A

CAS

CL =3

RL = 3

DQS

=< t

DQSCK

DOUT A

CMD

Post CAS

NOP

DQ's

NOP

CK/CK

Tn-1

Tn+1

Tn+2

Tn+3

Tn+4

Tn+5

DOUT A

DQS

DIN A

READ A

WL = RL - 1 = 4

RL =5

Post CAS

WRITE A

RTW

(Read to Write turn around time)

NOP

Page 36 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

Reads Intrrupted by a Read

Burst read can only be interrupted by another read with 4 bit burst boundary. Any other case of read interrupt

is not allowed.

Read Burst Interrupt Timing Example: (CL=3, AL=0, RL=3, BL=8)

Note

1. Read burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited.
2. Read burst of 8 can only be interrupted by another Read command. Read burst interruption by Write

command or Precharge command is prohibited.

3. Read burst interrupt must occur exactly two clocks after previous Read command. Any other Read burst

interrupt timings are prohibited.

4. Read burst interruption is allowed to any bank inside DRAM.
5. Read burst with Auto Precharge enabled is not allowed to interrupt.
6. Read burst interruption is allowed by another Read with Auto Precharge command.
7. All command timings are referenced to burst length set in the mode register. They are not referenced to

actual burst. For example, Minimum Read to Precharge timing is AL + BL/2 where BL is the burst length
set in the mode register and not the actual burst (which is shorter because of interrupt).

CK/CK

CMD

DQS/DQS

DQs

Read B

Read A

NOP

Page 37 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

3.2.4.4 Burst Write Operation

The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising
edge of the clock. The address inputs determine the starting column address. Write latency (WL) is defined
by a read latency (RL) minus one and is equal to (AL + CL -1). A data strobe signal (DQS) should be driven
low (preamble) one clock prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins
at the first rising edge of the DQS following the preamble. The tDQSS specification must be satisfied for write
cycles. The subsequent burst bit data are issued on successive edges of the DQS until the burst length is
completed, which is 4 or 8 bit burst. When the burst has finished, any additional data supplied to the DQ pins
will be ignored. The DQ Signal is ignored after the burst write operation is complete. The time from the com-
pletion of the burst write to bank precharge is the write recovery time (WR).
DDR2 SDRAM pin timings are specified for either single ended mode or differen-tial mode depending on the
setting of the EMRS "Enable DQS" mode bit; timing advantages of differential mode are realized in system
design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single
ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at V

REF

Burst Write Operation: RL = 5, WL = 4, tWR = 3 (AL=2, CL=3), BL = 4

WPRE

WPST

DQSH

DQSL

DQS

DMin

DQS

Data input (write) timing

DMin

CMD

NOP

DQs

NOP

CK/CK

WRITE A

Posted CAS

WL = RL - 1 = 4

DQS

< = t

DQSS

> = WR

DIN A

Precharge

Completion of
the Burst Write

Page 38 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

Burst Write Operation: RL = 3, WL = 2, tWR = 2 (AL=0, CL=3), BL = 4

Burst Write followed by Burst Read: RL = 5 (AL=2, CL=3), WL = 4, tWTR = 2, BL = 4

The minimum number of clock from the burst write command to the burst read command is [CL - 1 + BL/2 +
tWTR]. This tWTR is not a write recovery time (tWR) but the time required to transfer the 4bit write data from
the input buffer into sense amplifiers in the array. tWTR is defined in AC spec table of this data sheet.

CMD

NOP

Precharge

NOP

DQs

NOP

CK/CK

WRITE A

CAS

WL = RL - 1 = 2

DQS

< = t

DQSS

> = WR

DIN A

Bank A

Completion of
the Burst Write

Activate

> = tRP

CMD

NOP

CK/CK

DOUT A

NOP

DQS

DIN

WL = RL - 1 = 4

Post CAS

READ A

NOP

RL =5

AL = 2

CL = 3

NOP

Write to Read = CL - 1 + BL/2 + tWTR

> = tWTR

Page 40 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

Writes intrrupted by a write

Burst write can only be interrupted by another write with 4 bit burst boundary. Any other case of write interrupt

is not allowed.

Write Burst Interrupt Timing Example: (CL=3, AL=0, RL=3, WL=2, BL=8)

Notes:

1. Write burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited.
2. Write burst of 8 can only be interrupted by another Write command. Write burst interruption by Read

command or Precharge command is prohibited.

3. Write burst interrupt must occur exactly two clocks after previous Write command. Any other Write burst

interrupt timings are prohibited.

4. Write burst interruption is allowed to any bank inside DRAM.
5. Write burst with Auto Precharge enabled is not allowed to interrupt.
6. Write burst interruption is allowed by another Write with Auto Precharge command.
7. All command timings are referenced to burst length set in the mode register. They are not referenced to

actual burst. For example, minimum Write to Precharge timing is WL+BL/2+tWR where tWR starts with
the rising clock after the un-interrupted burst end and not from the end of actual burst end.

CK/CK

CMD

DQS/DQS

DQs

NOP

Write B

Write A

Page 42 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

3.2.5 Precharge Command

The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Com-
mand is triggered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Pre-
charge Command can be used to precharge each bank independently or all banks simultaneously. Three
address bits A10, BA0 and BA1 are used to define which bank to precharge when the command is issued.

Bank Selection for Precharge by Address Bits

Burst Read Operation Followed by Precharge

Minium Read to precharge command spacing to the same bank = AL + BL/2 clocks
For the earliest possible precharge, the precharge command may be issued on the rising edge which is
"Additive latency(AL) + BL/2 clocks" after a Read command. A new bank active (command) may be issued to
the same bank after the RAS precharge time (t

). A precharge command cannot be issued until t

RAS

is sat-

isfied.
The minimum Read to Precharge spacing has also to satisfy a minimum analog time from the rising clock
egde that initiates the last 4-bit prefetch of a Read to Precharge command. This time is called tRTP (Read to
Precharge). For BL = 4 this is the time from the actual read (AL after the Read command) to Precharge com-
mand. For BL = 8 this is the time from AL + 2 clocks after the Read to the Precharge command.

A10

BA0

BA1

Precharged Bank(s)

LOW

Bank 0 only

LOW

HIGH

Bank 1 only

LOW

HIGH

LOW

Bank 2 only

LOW

HIGH

Bank 3 only

HIGH

DON'T CARE

All Banks 0 ~ 3

Page 43 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

Example 1: Burst Read Operation Followed by Precharge:
RL = 4, AL = 1, CL = 3, BL = 4, t

RTP

<= 2 clocks

Example 2: Burst Read Operation Followed by Precharge:
RL = 4, AL = 1, CL = 3, BL = 8, t

RTP

<= 2 clocks

CMD

NOP

Precharge

NOP

DQ's

NOP

CK/CK

DOUT A

READ A

Post CAS

RL =4

DQS

Active

Bank A

> = t

NOP

CL =3

NOP

> = t

RAS

T 8

AL + BL/2 clks

AL = 1

CL = 3

> = t

RTP

CMD

NOP

DQ's

NOP

CK/CK

DOUT A

READ A

Post CAS

RL =4

DQS

Precharge A

NOP

T 8

AL + BL/2 clks

AL = 1

CL = 3

> = t

RTP

DOUT A

first 4-bit prefetch

second 4-bit prefetch

NOP

Page 46 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

Burst Write followed by Precharge

Minium Write to Precharge Command spacing to the same bank = WL + BL/2 clks + tWR

For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the Precharge
Command can be issued. This delay is known as a write recovery time (tWR) referenced from the completion
of the burst write to the precharge command. No Precharge command should be issued prior to the tWR delay.

Example 1: Burst Write followed by Precharge: WL = (RL-1) =3, BL=4

Example 2: Burst Write followed by Precharge: WL = (RL-1) = 4, BL=4

CMD

NOP

DQs

NOP

CK/CK

T 8

DIN A

WRITE A

Posted CAS

WL = 3

DQS

> = t

Precharge A

Completion of the Burst Write

CMD

NOP

DQs

NOP

CK/CK

T 9

DIN A

WRITE A

Posted CAS

WL = 4

DQS

> = t

Precharge A

Completion of the Burst Write

Page 47 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

3.2.6 Auto-Precharge Operation

Before a new row in an active bank can be opened, the active bank must be precharged using either the Pre-
charge Command or the auto-precharge function. When a Read or a Write Command is given to the DDR2
SDRAM, the CAS timing accepts one extra address, column address A10, to allow the active bank to auto-
matically begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is low
when the READ or WRITE Command is issued, then normal Read or Write burst operation is executed and
the bank remains active at the completion of the burst sequence. If A10 is high when the Read or Write Com-
mand is issued, then the auto-precharge function is engaged. During auto-precharge, a Read Command will
execute as normal with the exception that the active bank will begin to precharge on the rising edge which is
CAS latency (CL) clock cycles before the end of the read burst.

Auto-precharge also be implemented during Write commands. The precharge operation engaged by the Auto
precharge command will not begin until the last data of the burst write sequence is properly stored in the
memory array.

This feature allows the precharge operation to be partially or completely hidden during burst read cycles
(dependent upon CAS latency) thus improving system performance for random data access. The RAS lock-
out circuit internally delays the Precharge operation until the array restore operation has been completed
(tRAS satisfied) so that the auto precharge command may be issued with any read or write command.

Burst Read with Auto Precharge

If A10 is high when a Read Command is issued, the Read with Auto-Precharge function is engaged. The
DDR2 SDRAM starts an auto Precharge operation on the rising edge which is (AL + BL/2) cycles later than
the read with AP command if tRAS(min) and tRTP are satisfied.

If tRAS(min) is not satisfied at the edge, the start point of auto-precharge operation will be delayed until
tRAS(min) is satisfied.

If tRTP(min) is not satisfied at the edge, the start point of auto-precharge operation will be delayed until
tRTP(min) is satisfied.
In case the internal precharge is pushed out by tRTP, tRP starts at the point where the internal precharge
happens (not at the next rising clock edge after this event). So for BL = 4 the minimum time from Read_AP to
the next Activate command becomes AL + (tRTP + tRP)* (see example 2) for BL = 8 the time from Read_AP
to the next Activate is AL + 2 + (tRTP + tRP)*, where "*" means: "rouded up to the next integer". In any event
internal precharge does not start earlier than two clocks after the last 4-bit prefetch.

A new bank activate (command) may be issued to the same bank if the following two conditions are satisfied
simultaneously.
(1) The RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins.

(2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.

Page 48 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

Example 1: Burst Read Operation with Auto Precharge:
RL = 4, AL = 1, CL = 3, BL = 8, t

RTP

<= 2 clocks

Example 2: Burst Read Operation with Auto Precharge:
RL = 4, AL = 1, CL = 3, BL = 4, t

RTP

> 2 clocks

CMD

NOP

DQ's

NOP

CK/CK

DOUT A

READ A

Post CAS

RL =4

DQS

T 8

AL + BL/2 clks

AL = 1

CL = 3

> = t

RTP

DOUT A

first 4-bit prefetch

second 4-bit prefetch

NOP

RTP

NOP

Precharge begins here

Activate

Bank A

> = t

Autoprecharge

CMD

NOP

DQ's

NOP

CK/CK

DOUT A

READ A

Post CAS

RL =4

DQS

T 8

> = AL + tRTP + tRP

AL = 1

CL = 3

4-bit prefetch

NOP

RTP

NOP

Precharge begins here

Activate

Bank A

Autoprecharge

Page 49 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

Example 3: Burst Read with Auto Precharge Followed by an activation to the Same

Bank(tRC Limit):

RL = 5 (AL = 2, CL = 3, internal tRCD = 3, BL = 4, t

RTP

<= 2 clocks)

Example 4: Burst Read with Auto Precharge Followed by an Activation to the Same

Bank(tRP Limit):

RL = 5 (AL = 2, CL = 3, internal tRCD = 3, BL = 4, t

RTP

<= 2 clocks)

CMD

NOP

DQ's

NOP

CK/CK

DOUT A

READ A

Post CAS

AL = 2

CL =3

RL = 5

DQS

Activate

Bank A

> = t

A10 = 1

Auto Precharge Begins

CL =3

> = t

NOP

> = tRas(min)

CMD

NOP

DQ's

NOP

CK/CK

DOUT A

READ A

Post CAS

AL = 2

CL =3

RL = 5

DQS

Activate

Bank A

> = t

A10 = 1

Auto Precharge Begins

CL =3

> = t

NOP

> = tRas(min)

Page 50 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

Burst Write with Auto-Precharge

If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is engaged. The
DDR2 SDRAM automatically begins precharge operation after the completion of the burst write plus write
recovery time (tWR). The bank undergoing auto-precharge from the completion of the write burst may be
reactivated if the following two conditions are satisfied.

(1) The data-in to bank activate delay time (WR + tRP) has been satisfied.

(2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.

Burst Write with Auto-Precharge (tRC Limit): WL = 2, tWR =2, tRP=3, BL=4

Burst Write with Auto-Precharge (tWR + tRP): WL = 4, tWR =2, tRP=3, BL=4

CMD

NOP

Bank A

DQs

NOP

CK/CK

DIN A

WRA BankA

Post CAS

WL =RL - 1 = 2

DQS/DQS

A10 = 1

Auto Precharge Begins

NOP

> =

Completion of the Burst Write

Active

> = t

CMD

NOP

Bank A

DQs

NOP

CK/CK

T12

DIN A

WRA Bank A

Post CAS

WL =RL - 1 = 4

DQS/DQS

A10 = 1

Auto Precharge Begins

NOP

> =

Completion of the Burst Write

Active

> = t

Page 51 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

3.2.7 Refresh Command

When CS, RAS and CAS are held low and WE high at the rising edge of the clock, the chip enters the

Refresh mode (REF). All banks of the DDR2 SDRAM must be precharged and idle for a minimum of the Pre-

charge time (tRP) before the Refresh command (REF) can be applied. An address counter, internal to the

device, supplies the bank address during the refresh cycle. No control of the external address bus is required

once this cycle has started.

When the refresh cycle has completed, all banks of the DDR2 SDRAM will be in the precharged (idle) state. A

delay between the Refresh command (REF) and the next Activate command or subsequent Refresh com-

mand must be greater than or equal to the Refresh cycle time (tRFC).

To allow for improved efficiency in scheduling andswitching between tasks, some flexibility in the absolute

refresh interval is provided. A maximum of eight Refresh commands can be posted to any given DDR2

SDRAM, meaning that the maximum absolute interval between any Refresh command and the next Refresh

command is 9 * tREFI.

CMD

NOP

CBR

NOP

ANY

CK/CK

T15

Precharge

CKE

NOP

> = t

RFC

> = t

RFC

High

Page 52 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

3.2.8 Self Refresh Operation

The DDR2 SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh
Command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock.

ODT must be turned off before issuing Self Refresh command, by either driving ODT pin low or using EMRS

command. Once the Command is registered, CKE must be held low to keep the device in Self Refresh mode.
When the DDR2 SDRAM has entered Self Refresh mode all of the external signals

except CKE, are "don't

care". The clock is internally disabled during Self Refresh Operation to save power. The user may change the
external clock frequency or halt the external clock one clock after Self-Refresh entry is registered, however,

the clock must be restarted and stable before the device can exit Self Refresh operation. Once Self Refresh
Exit command is registered, a delay equal or longer than the tXSNR or tXSRD must be satisfied before a

valid command can be issued to the device. CKE must remain high for the entire Self Refresh exit period
tXSRD for proper operation. NOP or deselect commands must be registered on each positive clock edge dur-

ing the Self Refresh exit interval. ODT should also be turned off during tXSRD.

- Device must be in the "All banks idle" state prior to entering Self Refresh mode.
- ODT must be turned off tAOFD before entering Self Refresh mode, and can be turned on again

when tXSRD timing is satisfied.

- tXSRD is applied for a Read or a Read with autoprecharge command

- tXSNR is applied for any command except a Read or a Read with autoprecharge command.

CMD

CKE

ODT

Self

Refresh

NOP

tAOFD

> = tXSNR

> = tXSRD

tRP*

Valid

tCK

tCH tCL

tIS

tIS tIH

NOP

Page 53 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

3.2.9 Power-Down

Power-down is synchronously entered when CKE is registered low (along with Nop or Deselect command). CKE

is not allowed to go low while mode register or extended mode register command time, or read or write operation

is in progress. CKE is allowed to go low while any of other operations such as row activation, precharge or auto-

precharge, or auto-refresh is in progress, but power-down IDD spec will not be applied until finishing those opera-

tions. Timing diagrams are shown in the following pages with details for entry into power down.

The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset after exiting

power-down mode for proper read operation.

If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down

occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-

down deactivates the input and output buffers, excluding CK, CK, ODT and CKE. Also the DLL is disabled upon

entering precharge power-down or slow exit active power-down, but the DLL is kept enabled during fast exit

active power-down. In power-down mode, CKE low and a stable clock signal must be maintained at the inputs of

the DDR2 SDRAM, and ODT should be in a valid state but all other input signals are "Don't Care". CKE low must

be maintained until tCKE has been satisfied. Power-down duration is limited by 9 times tREFI of the device.

The power-down state is synchronously exited when CKE is registered high (along with a Nop or Deselect com-

mand). CKE high must be maintained until tCKE has been satisfied. A valid, executable command can be applied

with power-down exit latency, tXP, tXARD, or tXARDS, after CKE goes high. Power-down exit latency is defined

at AC spec table of this data sheet.

Basic Power Down Entry and Exit timing diagram

CK/CK

CKE

Command

VALID

NOP

VALID

Don't Care

NOP

XP,

XARD,

Enter Power-Down mode

CKE

XARDS

VALID

Exit Power-Down mode

CKE

VALID

Page 54 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

CMD

CKE

DQS

CMD

CKE

DQS

CMD

CKE

DQS

CMD

CKE

DQS

RDA

BL=8

PRE

AL + BL/2

with tRTP = 7.5ns

& tRAS min satisfied

AL + BL/2

with tRTP = 7.5ns

& tRAS min satisfied

Read to power down entry

Read with Autoprecharge to power down entry

Start internal precharge

AL + CL

CKE should be kept high until the end of burst operation.

AL + CL

BL=4

CKE should be kept high

until the end of burst operation.

AL + CL

Tx+2

Tx+3

Tx+4

Tx+5

Tx+6

Tx+1

Tx+7

Tx+8

Tx+9

CKE should be kept high until the end of burst operation.

until the end of burst operation.

BL=4

BL=8

Read operation starts with a read command and

Tx+2

Tx+3

Tx+4

Tx+5

Tx+6

Tx+1

Tx+7

Tx+8

Tx+9

Tx+2

Tx+3

Tx+4

Tx+5

Tx+6

Tx+1

Tx+7

Tx+8

Tx+9

Tx+2

Tx+3

Tx+4

Tx+5

Tx+6

Tx+1

Tx+7

Tx+8

Tx+9

DQS

Page 58 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

Input Clock Frequency Change during Precharge Power Down

DDR2 SDRAM input clock frequency can be changed under following condition:

DDR2 SDRAM is in precharged power down mode. ODT must be turned off and CKE must be at logic LOW level.
A minimum of 2 clocks must be waited after CKE goes LOW before clock frequency may change. SDRAM input
clock frequency is allowed to change only within minimum and maximum operating frequency specified for the
particular speed grade. During input clock frequency change, ODT and CKE must be held at stable LOW levels.
Once input clock frequency is changed, stable new clocks must be provided to DRAM before precharge power
down may be exited and DLL must be RESET via EMRS after precharge power down exit. Depending on new
clock frequency an additional MRS command may need to be issued to appropriately set the WR, CL etc.. During
DLL re-lock period, ODT must remain off. After the DLL lock time, the DRAM is ready to operate with new clock
frequency.

CKE

Tx+1

Ty+1

Ty+2

Valid

DLL

NOP

200 Clocks

Frequency Change

Ty+3

NOP

RESET

tRP

Clock Frequency Change in Precharge Power Down Mode

tXP

Occurs here

tAOFD

Stable new clock
before power down exit

ODT is off during
DLL RESET

Minmum 2 clocks

required before
changing frequency

ODT

CMD

Ty+4

Page 60 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

4. Command Truth Table.

4.1 Command truth table.

Function

CKE

RAS CAS

BA0
BA1
BA2

A15-A11 A10

A9 - A0

Notes

Cycle

Current

Cycle

(Extended) Mode Register Set

OP Code

1,2

Refresh (REF)

Self Refresh Entry

Self Refresh Exit

1,7

Single Bank Precharge

1,2

Precharge all Banks

Bank Activate

Row Address

1,2

Write

Column

1,2,3,

Write with Auto Precharge

Column

1,2,3,

Read

Column

1,2,3

Read with Auto-Precharge

Column

1,2,3

No Operation

Device Deselect

Power Down Entry

1,4

Power Down Exit

1,4

1. All DDR2 SDRAM commands are defined by states of CS, RAS, CAS , WE and CKE at the rising edge of the clock.
2. Bank addesses BA0, BA1, BA2 (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode

3. Burst reads or writes at BL=4 cannot be terminated or interrupted. See sections "Reads interrupted by a Read" and "Writes inter-

rupted by a Write" in section 2.2.4 for details.

4. The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh

requirements outlined in section 2.2.7.

5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. See

section 2.2.2.4.

6. "X" means "H or L (but a defined logic level)".
7. Self refresh exit is asynchronous.

Page 61 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

4.2 Clock Enable (CKE) Truth Table for Synchronous Transitions

Current State

CKE

Command (N)

RAS, CAS, WE, CS

Action (N)

Notes

Previous Cycle

(N-1)

Current Cycle

(N)

Power Down

Maintain Power-Down

11, 13, 15

DESELECT or NOP

Power Down Exit

4, 8, 11,13

Self Refresh

Maintain Self Refresh

11, 15

DESELECT or NOP

Self Refresh Exit

4, 5,9

Bank(s) Active

DESELECT or NOP

Active Power Down Entry

4,8,10,11,13

All Banks Idle

DESELECT or NOP

Precharge Power Down Entry

4, 8, 10,11,13

REFRESH

Self Refresh Entry

6, 9, 11,13

Refer to the Command Truth Table

Notes:

1. CKE (N) is the logic state of CKE at clock edge N; CKE (N1) was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge N.
3. COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N).
4. All states and sequences not shown are illegal or reserved unless explicitely described elsewhere in this document.
5. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the t

XSNR

period.

Read commands may be issued only after t

XSRD

(200 clocks) is satisfied.

6. Self Refresh mode can only be entered from the All Banks Idle state.
7. Must be a legal command as defined in the Command Truth Table.
8. Valid commands for Power Down Entry and Exit are NOP and DESELECT only.
9. Valid commands for Self Refresh Exit are NOP and DESELECT only.

10. Power Down and Self Refresh can not be entered while Read or Write operations, (Extended) Mode Register Set operations or

Precharge operations are in progress. See section 2.2.9 "Power Down" and 3.2.8 "Self Refresh Command" for a detailed list of
restrictions.

11. Minimum CKE high time is three clocks.; minimum CKE low time is three clocks.

12. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. See

section 2.2.2.4.

13. The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the refresh

requirements outlined in section 2.2.7.

14. CKE must be maintained high while the SDRAM is in OCD calibration mode .
15. "X" means "don't care (including floating around VREF)" in Self Refresh and Power Down. However ODT must be driven high or

low in Power Down if the ODT fucntion is enabled (Bit A2 or A6 set to "1" in EMRS(1) ).

4.3 DM Truth Table

Name (Functional)

DQs

Note

Write enable

Valid

Write inhibit

1. Used to mask write data, provided coinsident with the corresponding data

Page 62 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

5. Absolute Maximum DC Ratings

6. AC & DC Operating Conditions
Recommended DC Operating Conditions (SSTL - 1.8)

Symbol

Parameter Rating

Units

Notes

VDD

Voltage on VDD pin relative to Vss

- 1.0 V ~ 2.3 V

VDDQ

Voltage on VDDQ pin relative to Vss

- 0.5 V ~ 2.3 V

VDDL

Voltage on VDDL pin relative to Vss

- 0.5 V ~ 2.3 V

OUT

Voltage on any pin relative to Vss

- 0.5 V ~ 2.3 V

STG

Storage Temperature

-55 to +100

C 1

Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-
ability.

Symbol

Parameter

Rating

Units

Notes

Min.

Typ. Max.

VDD

Supply Voltage

1.7

1.8

1.9

VDDL

Supply Voltage for DLL

1.7

1.8

1.9

VDDQ

Supply Voltage for Output

1.7

1.8

1.9

VREF

Input Reference Voltage

0.49*VDDQ

0.50*VDDQ

0.51*VDDQ

1.2

VTT

Termination Voltage

REF

-0.04

REF

+0.04

There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must
be less than or equal to VDD.

1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is

expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.

2. Peak to peak ac noise on VREF may not exceed +/-2% VREF (dc).
3. VTT of transmitting device must track VREF of receiving device.
4. VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together.

Page 63 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

Input DC Logic Level

Input AC Logic Level

AC Input Test Conditions

Notes:

Input waveform timing is referenced to the input signal crossing through the V

REF

level applied to the device under test.

The input signal minimum slew rate is to be maintained over the range from V

IL(dc)

max to V

IH(ac)

min for rising edges and the

range from V

IH(dc)

min to V

IL(ac)

max for falling edges as shown in the below figure.

AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to
VIL(ac) on the negative transitions.

Symbol

Parameter

Min.

Max.

Units

Notes

(dc)

dc input logic high

REF

+ 0.125

DDQ

+ 0.3

(dc)

dc input logic low

- 0.3

REF

- 0.125

Symbol

Parameter

Min.

Max.

Units

Notes

(ac)

ac input logic high

REF

+ 0.250

(ac)

ac input logic low

REF

- 0.250

Symbol

Condition

Value

Units

Notes

REF

Input reference voltage

0.5 * V

DDQ

SWING(MAX)

Input signal maximum peak to peak swing

1.0

SLEW

Input signal minimum slew rate

1.0

V/ns

2, 3

DDQ

IH(ac)

min

IH(dc)

min

REF

IL(dc)

max

IL(ac)

max

< AC Input Test Signal Waveform >

SWING(MAX)

delta TR

delta TF

Start of Falling Edge Input Timing

Start of Rising Edge Input Timing

IH(dc)

min - V

IL(ac)

max

delta TF

Falling Slew =

Rising Slew =

IH(ac)

min - V

IL(dc)

max

delta TR

Page 64 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

Differential input AC logic Level

1. V

IN(DC)

specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS, LDQS, UDQS and

UDQS.
2. V

ID(DC

) specifies the input differential voltage |V

-V

| required for switching, where V

is the true input (such as CK, DQS, LDQS

or UDQS) level and V

is the complementary input (such as CK, DQS, LDQS or UDQS) level. The minimum value is equal to V

IH(DC)

- V

IL(DC)

Notes:

1. V

ID(AC)

specifies the input differential voltage |V

-V

| required for switching, where V

is the true input signal (such as CK, DQS,

LDQS or UDQS) and V

is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to V

IH(AC)

- V

IL(AC)

2. The typical value of V

IX(AC)

is expected to be about 0.5 * VDDQ of the transmitting device and V

IX(AC)

is expected to track variations in

VDDQ . V

IX(AC)

indicates the voltage at whitch differential input signals must cross.

Differential AC output parameters

Notes:
1. The typical value of V

OX(AC)

is expected to be about 0.5 * V DDQ of the transmitting device and V

OX(AC

) is expected to track variations

in VDDQ . V

OX(AC)

indicates the voltage at whitch differential output signals must cross.

Symbol

Parameter

Min.

Max.

Units

Notes

(ac)

ac differential input voltage

0.5

DDQ

+ 0.6

(ac)

ac differential cross point voltage

0.5 * VDDQ - 0.175

0.5 * VDDQ + 0.175

Symbol

Parameter

Min.

Max.

Units

Notes

(ac)

ac differential cross point voltage

0.5 * VDDQ - 0.125

0.5 * VDDQ + 0.125

DDQ

Crossing point

SSQ

IX or

< Differential signal levels >

Page 65 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

Input Signal Overshoot/Undershoot Specification

AC Overshoot/Undershoot Specification for Address and Control Pins A0-A15, BA0-BA2, CS, RAS,

CAS, WE, CKE, ODT

Parameter

Specification

DDR2-400

DDR2-533

DDR2-667

Maximum peak amplitude allowed for overshoot area (See Figure 1):

0.9V

Maximum peak amplitude allowed for undershoot area (See Figure 1):

0.9V

Maximum overshoot area above VDD (See Figure1).

0.75 V-ns

0.56 V-ns

0.45 V-ns

Maximum undershoot area below VSS (See Figure 1).

0.75 V-ns

0.56 V-ns

0.45 V-ns

AC Overshoot/Undershoot Specification for Clock, Data, Strobe, and Mask Pins DQ, DQS, DM, CK,

Parameter

Specification

DDR2-400

DDR2-533

DDR2-667

Maximum peak amplitude allowed for overshoot area (See Figure 2):

0.9V

Maximum peak amplitude allowed for undershoot area (See Figure 2):

0.9V

Maximum overshoot area above VDDQ (See Figure 2).

0.38 V-ns

0.28 V-ns

0.23 V-ns

Maximum undershoot area below VSSQ (See Figure 2).

0.38 V-ns

0.28 V-ns

0.23 V-ns

Overshoot Area

Maximum Amplitude

Undershoot Area

Maximum Amplitude

Volts

(V)

AC Overshoot and Undershoot Definition for Address and Control Pins

Time (ns)

Overshoot Area

Maximum Amplitude

DDQ

Undershoot Area

Maximum Amplitude

SSQ

Volts

(V)

AC Overshoot and Undershoot Definition for Clock, Data, Strobe, and Mask Pins

Time (ns)

Page 67 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

Output Buffer Levels

Output AC Test Conditions

Output DC Current Drive

OCD defalut characteristics

Note 1: Absolute Specifications (0°C

CASE

+tbd°C; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V)

Note 2: Impedance measurement condition for output source dc current: VDDQ = 1.7V; VOUT = 1420mV;

(VOUT-VDDQ)/Ioh must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ-280mV.
Impedance measurement condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol
must be less than 23.4 ohms for values of VOUT between 0V and 280mV.

Note 3: Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and

voltage.

Note 4: Slew rate measured from vil(ac) to vih(ac).
Note 5: The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew

rate as measured from AC to AC. This is guaranteed by design and characterization.

Symbol

Parameter

SSTL_18 Class II

Units

Notes

Minimum Required Output Pull-up under AC Test Load

+ 0.603

Maximum Required Output Pull-down under AC Test Load

- 0.603

OTR

Output Timing Measurement Reference Level

0.5 * V

DDQ

1. The VDDQ of the device under test is referenced.

Symbol

Parameter

SSTl_18 Class II

Units

Notes

OH(dc)

Output Minimum Source DC Current

- 13.4

1, 3, 4

OL(dc)

Output Minimum Sink DC Current

13.4

2, 3, 4

DDQ

= 1.7 V; V

OUT

= 1420 mV. (V

OUT

- V

DDQ

)/I

must be less than 21 ohm for values of V

OUT

between V

DDQ

and V

DDQ

- 280

mV.

DDQ

= 1.7 V; V

OUT

= 280 mV. V

OUT

must be less than 21 ohm for values of V

OUT

between 0 V and 280 mV.

The dc value of V

REF

applied to the receiving device is set to V

The values of I

OH(dc)

and I

OL(dc)

are based on the conditions given in Notes 1 and 2. They are used to test device drive current

capability to ensure V

min plus a noise margin and V

max minus a noise margin are delivered to an SSTL_18 receiver. The

actual current values are derived by shifting the desired driver operating point (see Section 3.3) along a 21 ohm load line to define
a convenient driver current for measurement.

Description

Parameter

Min

Nom

Max

Unit

Notes

Output impedance

12.6

23.4

ohms

1,2

Pull-up and pull-

down mismatch

ohms

1,2,3

Output slew rate

tbd

V/ns

1,4,5

Page 68 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

Table 1. Full Strength Default Pulldown Driver Characteristics

Figure 1. DDR2 Default Pulldown Characteristics for Full Strength Driver

Pulldow n Current (mA)

Voltage (V) Minimum (23.4 Ohms)

Nominal Default

Low (18 ohms)

Nominal Default

High (18 ohms)

Maximum (12.6 Ohms)

0.2

8.5

11.3

11.8

15.9

0.3

12.1

16.5

16.8

23.8

0.4

14.7

21.2

22.1

31.8

0.5

16.4

25.0

27.6

39.7

0.6

17.8

28.3

32.4

47.7

0.7

18.6

30.9

36.9

55.0

0.8

19.0

33.0

40.9

62.3

0.9

19.3

34.5

44.6

69.4

1.0

19.7

35.5

47.7

75.3

1.1

19.9

36.1

50.4

80.5

1.2

20.0

36.6

52.6

84.6

1.3

20.1

36.9

54.2

87.7

1.4

20.2

37.1

55.9

90.8

1.5

20.3

37.4

57.1

92.9

1.6

20.4

37.6

58.4

94.9

1.7

20.6

37.7

59.6

97.0

1.8

37.9

60.9

99.1

1.9

101.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

VOUT to VSSQ (V)

100

120

Pulldown current (mA)

Maximum

Nominal

Default

High

Nominal

Default

Low

Minimum

Page 69 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

Table 2. Full Strength Default Pullup Driver Characteristics

Figure 2. DDR2 Default Pullup Characteristics for Full Strength Output Driver

Pullup Current (mA)

Voltage (V) Minimum (23.4 Ohms) Nominal Default

Low (18 ohms)

Nominal Default

High (18 ohms)

Maximum (12.6 Ohms)

0.2

-8.5

-11.1

-11.8

-15.9

0.3

-12.1

-16.0

-17.0

-23.8

0.4

-14.7

-20.3

-22.2

-31.8

0.5

-16.4

-24.0

-27.5

-39.7

0.6

-17.8

-27.2

-32.4

-47.7

0.7

-18.6

-29.8

-36.9

-55.0

0.8

-19.0

-31.9

-40.8

-62.3

0.9

-19.3

-33.4

-44.5

-69.4

1.0

-19.7

-34.6

-47.7

-75.3

1.1

-19.9

-35.5

-50.4

-80.5

1.2

-20.0

-36.2

-52.5

-84.6

1.3

-20.1

-36.8

-54.2

-87.7

1.4

-20.2

-37.2

-55.9

-90.8

1.5

-20.3

-37.7

-57.1

-92.9

1.6

-20.4

-38.0

-58.4

-94.9

1.7

-20.6

-38.4

-59.6

-97.0

1.8

-38.6

-60.8

-99.1

1.9

-101.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

VDDQ to VOUT (V)

-120

-100

-80

-60

-40

-20

Pullup current (mA)

Minimum

Nominal

Default

Low

Nominal

Default

High

Maximum

Page 70 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

DDR2 SDRAM Default Output Driver VI Characteristics

DDR2 SDRAM output driver characteristics are defined for full strength default operation as selected by
the EMRS1 bits A7-A9 = `111'. Figures 1 and 2 show the driver characteristics graphically, and tables 1 and
2 show the same data in tabular format suitable for input into simulation tools. The driver characteristics
evaluation conditions are:
Nominal Default 25

C (T case), VDDQ = 1.8 V, typical process

Minimum TBD

C (T case), VDDQ = 1.7 V, slowslow process

Maximum 0

C (T case), VDDQ = 1.9 V, fastfast process

Default Output Driver Characteristic Curves Notes:

1) The full variation in driver current from minimum to maximum process, temperature, and voltage will
lie within the outer bounding lines of the VI curve of figures 1 and 2.
2) It is recommended that the "typical" IBIS VI curve lie within the inner bounding lines of the VI curves
of figures 1 and 2.

Table 3. Full Strength Calibrated Pulldown Driver Characteristics

Table 4. Full Strength Calibrated Pullup Driver Characteristics

DDR2 SDRAM Calibrated Output Driver VI Characteristics

DDR2 SDRAM output driver characteristics are defined for full strength calibrated operation as selected by
the procedure outlined in section 2.2.2.3, Off-Chip Driver (OCD) Impedance Adjustment. Tables 3 and 4
show the data in tabular format suitable for input into simulation tools. The nominal points represent a
device at exactly 18 ohms. The nominal low and nominal high values represent the range that can be
achieved with a maximum 1.5 ohm step size with no calibration error at the exact nominal conditions only
(i.e. perfect calibration procedure, 1.5 ohm maximum step size guaranteed by specification). Real system
calibration error needs to be added to these values. It must be understood that these V-I curves as repre-
sented here or in supplier IBIS models need to be adjusted to a wider range as a result of any system cali-
bration error. Since this is a system specific phenomena, it cannot be quantified here. The values in the
calibrated tables represent just the DRAM portion of uncertainty while looking at one DQ only. If the cali

Calibrated Pulldow n Current (mA)

Voltage (V)

Nominal Minimum

(21 ohms)

Nominal Low (18.75

ohms)

Nominal (18 ohms)

Nominal High (17.25

ohms)

Nominal Maximum (15

ohms)

0.2

9.5

10.7

11.5

11.8

13.3

0.3

14.3

16.0

16.6

17.4

20.0

0.4

18.7

21.0

21.6

23.0

27.0

Calibrated Pullup Current (mA)

Voltage (V)

Nominal Minimum

(21 ohms)

Nominal Low (18.75

ohms)

Nominal (18 ohms)

Nominal High (17.25

ohms)

Nominal Maximum (15

ohms)

0.2

-9.5

-10.7

-11.4

-11.8

-13.3

0.3

-14.3

-16.0

-16.5

-17.4

-20.0

0.4

-18.7

-21.0

-21.2

-23.0

-27.0

Page 71 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

bration procedure is used, it is possible to cause the device to operate outside the bounds of the default
device characteristics tables and figures. In such a situation, the timing parameters in the specification can-
not be guaranteed. It is solely up to the system application to ensure that the device is calibrated between the
minimum and maximum default values at all times. If this can't be guaranteed by the system calibration pro-
cedure, re-calibration policy, and uncertainty with DQ to DQ variation, then it is recommended that only the
default values be used. The nominal maximum and minimum values represent the change in impedance
from nominal low and high as a result of voltage and temperature change from the nominal condition to the
maximum and minimum conditions. If calibrated at an extreme condition, the amount of variation could be as
much as from the nominal minimum to the nominal maximum or vice versa. The driver characteristics evalu-
ation conditions are:
Nominal 25

C (T case), VDDQ = 1.8 V, typical process

Nominal Low and Nominal High 25

C (T case), VDDQ = 1.8 V, any process

Nominal Minimum TBD

C (T case), VDDQ = 1.7 V, any process

Nominal Maximum 0

C (T case), VDDQ = 1.9 V, any process

Page 72 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

IDD Specification Parameters and Test Conditions

(IDD values are for full operating range of Voltage and Temperature, Notes 1 - 5)

Sym-
bol

Proposed Conditions

DDR2-

400

(CL=4)

DDR2-

533

(CL=4)

DDR2-

533

(CL=5)

Units

Notes

IDD0

Operating one bank active-precharge current;
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD);
CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING

TBD

IDD1

Operating one bank active-read-precharge current;
IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD =
tRCD(IDD);
CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W

TBD

IDD2P

Precharge power-down current;
All banks idle;
tCK = tCK(IDD);
CKE is LOW;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING

TBD

IDD2Q

Precharge quiet standby current;
All banks idle;
tCK = tCK(IDD);
CKE is HIGH, CS\ is HIGH;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING

TBD

IDD2N

Precharge standby current;
All banks idle;
tCK = tCK(IDD);
CKE is HIGH, CS\ is HIGH;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING

TBD

IDD3P

Active power-down current;
All banks open;
tCK = tCK(IDD);
CKE is LOW;
Other control and address bus inputs are STA-
BLE;
Data bus inputs are FLOATING

Fast PDN Exit
MRS(12) = 0mA

TBD

Slow PDN Exit
MRS(12) = 1mA

TBD

IDD3N

Active standby current;
All banks open;
tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD);
CKE is HIGH, CS\ is HIGH between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING

TBD

Page 73 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

Note:
1. IDD specifications are tested after the device is properly initialized
2. Input slew rate is specified by AC Parametric Test Condition
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS\, RDQS, RDQS\, LDQS, LDQS\, UDQS, and UDQS\. IDD values must be met with all combi-

nations of EMRS bits 10 and 11.

5. Definitions for IDD

LOW is defined as Vin

VILAC(max)

HIGH is defined as Vin

VIHAC(min)

STABLE is defined as inputs stable at a HIGH or LOW level

FLOATING is defined as inputs at VREF = VDDQ/2

SWITCHING is defined as:

inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control

signals, and

inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including

masks or strobes.

IDD4W

Operating burst write current;
All banks open, Continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD);
CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING

TBD

IDD4R

Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD);
CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W

TBD

IDD5B

Burst auto refresh current;
tCK = tCK(IDD);
Refresh command at every tRFC(IDD) interval;
CKE is HIGH, CS\ is HIGH between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING

TBD

IDD6

Self refresh current;
CK and CK\ at 0V;
CKE

0.2V;

Other control and address bus inputs are
FLOATING;
Data bus inputs are FLOATING

Normal

TBD

Low Power

TBD

IDD7

Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD);
tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD =
1*tCK(IDD);
CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4R;
- Refer to the following page for detailed timing conditions

TBD

Page 74 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

For purposes of IDD testing, the following parameters are to be utilized

Detailed IDD7
The detailed timings are shown below for IDD7. Changes will be required if timing parameter changes are made to the specification.
Legend: A = Active; RA = Read with Autoprecharge; D = Deselect

IDD7: Operating Current: All Bank Interleave Read operation
All banks are being interleaved at minimum tRC(IDD) without violating tRRD(IDD) using a burst length of 4. Control and address bus
inputs are STABLE during DESELECTs. IOUT = 0mA

Timing Patterns for 4 bank devices x4/ x8/ x16
-DDR2-400 4/4/4
A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D D

-DDR2-533 5/4/4
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D

-DDR2-533 4/4/4
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D

Timing Patterns for 8 bank devices x4/x8
-DDR2-400 and DDR2-533 all bins
A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D

Timing Patterns for 8 bank devices x16
-DDR2-400 all bins
A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D

-DDR2-533 all bins
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D

DDR2-533

DDR2-400

Parameter

4-4-4

5-4-4

4-4-4

Units

CL(IDD)

tCK

tRCD(IDD)

tRC(IDD)

tRRD(IDD)-x4/x8

7.5

tRRD(IDD)-x16

tCK(IDD)

3.75

tRASmin(IDD)

tRP(IDD)

tRFC(IDD)-512Mb

105

Page 75 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

Input/Output Capacitance

Electrical Characteristics & AC Timing for DDR2-400/DDR2-533

C < T

CASE

< TBD

C; V

DDQ

= 1.8V + 0.1V; V

= 1.8V + 0.1V)

Refresh Parameters by Device Density

Speed Bins and CL, tRCD, tRP and tRC for Corresponding Bin

Timing Parameters by Speed Grade

(Refer to notes for informations related to this table at the bottom)

Parameter

Symbol

Min

Max

Units

Input capacitance, CK and CK

CCK

1.5

2.5

Input capacitance delta, CK and CK

CDCK

0.25

Input capacitance, all other input-only pins

1.5

2.5

Input capacitance delta, all other input-only pins

CDI

0.25

Input/output capacitance, DQ, DM, DQS, DQS

CIO

3.0

4.0

Input/output capacitance delta, DQ, DM, DQS, DQS

CDIO

0.5

Parameter

Symbol

256Mb

512Mb

1Gb

2Gb

4Gb

Units

Auto refresh to active/auto refresh command time

tRFC

105

127.5

195

tbd

Average periodic refresh interval

tREFI

7.8

Speed

DDR2-533(D5)

DDR2-533(E5)

DDR2-400(D4)

Units

Bin (CL - tRCD - tRP)

4 - 4 - 4

5 - 4- 4

4 - 4 - 4

Parameter

min

max

min

max

min

max

tCK, CL=3

tCK, CL=4

3.75

tCK, CL=5

3.75

tRCD

tRP

tRC

Parameter

Symbol

DDR2-400

DDR2-533

Unit
s

Notes

min

max

min

max

DQ output access time from
CK/CK

tAC

-600

+600

-500

+500

DQS output access time from
CK/CK

tDQSCK

-500

+500

-450

+450

Page 76 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

CK high-level width

tCH

0.45

0.55

0.45

0.55

tCK

CK low-level width

tCL

0.45

0.55

0.45

0.55

tCK

CK half period

tHP

min(tCL,tCH)

19,20

Clock cycle time, CL=x

tCK

5000

8000

3750

8000

DQ and DM input hold time

tDH

400

350

14,15,

DQ and DM input setup time

tDS

400

350

14,15,

Control & Address input pulse
width for each input

tIPW

0.6

tCK

DQ and DM input pulse width for
each input

tDIPW

0.35

tCK

Data-out high-impedance time
from CK/CK

tHZ

tAC max

Data-out low-impedance time from
CK/CK

tLZ

tAC min

tAC max

tAC min

tAC max

DQS-DQ skew for DQS and
associated DQ signals

tDQSQ

350

300

DQ hold skew factor

tQHS

450

400

DQ/DQS output hold time from
DQS

tQH

tHP - tQHS

Write command to first DQS
latching transition

tDQSS

WL - 0.25

WL + 0.25

WL - 0.25

WL + 0.25

tCK

DQS input high pulse width

tDQSH

0.35

tCK

DQS input low pulse width

tDQSL

0.35

tCK

DQS falling edge to CK setup time

tDSS

0.2

tCK

DQS falling edge hold time from CK

tDSH

0.2

tCK

Mode register set command cycle
time

tMRD

tCK

Write preamble setup time

tWPRES

Write postamble

tWPST

0.4

0.6

0.4

0.6

tCK

Write preamble

tWPRE

0.4

tCK

Address and control input hold
time

tIH

600

500

13,15,

Address and control input setup
time

tIS

600

500

13,15,

Read preamble

tRPRE

0.9

1.1

0.9

1.1

tCK

Read postamble

tRPST

0.4

0.6

0.4

0.6

tCK

Active to precharge command

tRAS

70000

Page 77 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

General notes, which may apply for all AC parameters

1. Slew Rate Measurement Levels

Active to active command period
for 1KB page size

products

tRRD

7.5

Active to active command period
for

2KB page size products

tRRD

CAS to CAS command delay

tCCD

tCK

Write recovery time

tWR

Auto precharge write recovery +
precharge time

tDAL

tWR+tRP*

tCK

Internal write to read command
delay

tWTR

7.5

Internal read to precharge
command delay

tRTP

7.5

Exit self refresh to a non-read
command

tXSNR

tRFC + 10

Exit self refresh to a read
command

tXSRD

200

tCK

Exit precharge power down to any
non-read command

tXP

tCK

Exit active power down to read
command

tXARD

tCK

Exit active power down to read
command
(Slow exit, Lower power)

tXARDS

6 - AL

tCK

9, 10

CKE minimum pulse width
(high and low pulse width)

CKE

tCK

ODT turn-on delay

AOND

tCK

ODT turn-on

AON

tAC(min)

tAC(max)+1

tAC(min)

tAC(max)+1

ODT turn-on(Power-Down mode)

AONPD

tAC(min)+2

2tCK+tAC(m

ax)+1

tAC(min)+2

2tCK+tAC(

max)+1

ODT turn-off delay

AOFD

2.5

tCK

ODT turn-off

AOF

tAC(min)

tAC(max)+ 0.6

tAC(min)

tAC(max)+

0.6

ODT turn-off (Power-Down mode)

AOFPD

tAC(min)+2

2.5tCK+tAC(

max)+1

tAC(min)+2

2.5tCK+tAC

(max)+1

ODT to power down entry latency

tANPD

tCK

ODT power down exit latency

tAXPD

tCK

OCD drive mode output delay

tOIT

Minimum time clocks remains ON
after CKE asynchronously drops
LOW

tDelay

tIS+tCK+tIH

Page 78 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for

single ended signals. For differential signals (e.g. DQS - DQS) output slew rate is measured between

DQS - DQS = -500 mV and DQS - DQS = +500mV. Output slew rate is guaranteed by design, but is not
necessarily tested on each device.

b. Input slew rate for single ended signals is measured from dc-level to ac-level: from VREF - 125 mV to

VREF + 250 mV for rising edges and from VREF + 125 mV and VREF - 250 mV for falling edges.

For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = -250 mV to
CK - CK = +500 mV

(250mV to -500 mV for falling egdes).

c. VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or

between DQS and DQS for differential strobe.

2. DDR2 SDRAM AC timing reference load

Figure AA represents the timing reference load used in defining the relevant timing parameters of the part.

It is not intended to be either a precise representation of the typical system environment nor a depiction of the
actual load presented by a production tester. System designers will use IBIS or other simulation tools to cor-
relate the timing reference load to a system environment. Manufacturers will correlate to their production test
conditions (generally a coaxial transmission line terminated at the tester electronics).

The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output tim-
ing reference voltage level for differential signals is the crosspoint of the true (e.g. DQS) and the complement
(e.g. DQS) signal.

3. DDR2 SDRAM output slew rate test load

Output slew rate is characterized under the test conditions as shown in Figure.

4. Differential data strobe

DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS

"Enable DQS" mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM
pin timings are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling
edges of DQS crossing at VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its
complement, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that when differential data
strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to VSS through a 20

ohm

to 10 K ohm

VDDQ

DUT

DQS
DQS

RDQS
RDQS

Output

= V

DDQ

Timing

reference

point

Figure AA : AC Timing Reference Load

VDDQ

DUT

DQS, DQS

RDQS, RDQS

Output

= V

DDQ

Test point

Slew Rate Test Load

Page 79 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

resisor to insure proper operation.

5. AC timings are for linear signal transitions. See System Derating for other signal transitions.

6. These parameters guarantee device behavior, but they are not necessarily tested on each device. They

may be guaranteed by device design or tester correlation.

7. All voltages referenced to VSS.

8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal refer-
ence/supply voltage levels, but the related specifications and device operation are guaranteed for the full volt-
age range specified.

Specific Notes for dedicated AC parameters

9. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be

used for fast active power down exit timing. tXARDS is expected to be used for slow active power down exit
timing where a lower power value is defined by each vendor data sheet.
10. AL = Additive Latency

11. This is a minimum requirement. Minimum read to precharge timing is AL + BL/2 providing the tRTP and

tRAS(min) have been satisfied.

WPRE

WPST

DQSH

DQSL

DQS

DMin

DQS/

Figure XX -- Data input (write) timing

DMin

DQS

CK/CK

DQS/DQS

DQS

RPST

RPRE

DQSQmax

Figure YY-- Data output (read) timing

Page 80 of 80

512Mb M-die DDR2 SDRAM

Preliminary

Rev. 0.92 (Jun. 2003)

12. A minimum of two clocks (2 * tCK) is required irrespective of operating frequency

13. Timings are guaranteed with command/address input slew rate of 1.0 V/ns. See System Derating for

other slew rate values.

14. Timings are guaranteed with data, mask, and (DQS/RDQS in singled ended mode) input slew rate of 1.0

V/ns. See System Derating for other slew rate values.

15. Timings are guaranteed with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS

signals with a differential slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1V/ns in single

ended mode. See System Derating for other slew rate values.

16. tDS and tDH (data setup and hold) derating

tbd

17. tIS and tIH (input setup and hold) derating

tbd

18. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for
this parameter, but system performance (bus turnaround) will degrade accordingly.

19. MIN ( t CL, t CH) refers to the smaller of the actual clock low time and the actual clock high time as pro-
vided to the device (i.e. this value can be greater than the minimum specification limits for t CL and t CH). For
example, t CL and t CH are = 50% of the period, less the half period jitter ( t JIT(HP)) of the clock source, and
less the half period jitter due to crosstalk ( t JIT(crosstalk)) into the clock traces.

20. t QH = t HP t QHS, where:

tHP = minimum half clock period for any given cycle and is defined by clock high or clock low ( tCH, tCL).
tQHS accounts for:

1) The pulse duration distortion of on-chip clock circuits; and
2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the

next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-

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