K6E0808C1C-C
CMOS SRAM
PRELIMINARY
Rev 4.0
- 1 -
February 1998
Document Title
32Kx8 Bit High Speed Static RAM(5V Operating), Evolutionary Pin out.
Revision History
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Rev No.
Rev. 0.0
Rev. 1.0
Rev. 2.0
Rev. 3.0
Rev. 4.0
Remark
Preliminary
Final
Final
Final
Final
History
Initial release with Preliminary.
Release to final Data Sheet.
1. Delete Preliminary
Update A.C parameters
2.1. Updated A.C parameters
2.2. Add V
OH1
=3.95V with the test condition as Vcc=5V
5% at 25
C
3.1. Add 28-TSOP1 Package.
3.2. Add L-version.
3.3. Add Data Rentention Characteristics.
4.1. Delete DIP Package.
4.2. Delete L-version.
4.3. Delete Data Retention Characteristics and Waveform.
Items
Previous spec.
(12/15/20ns part)
Updated spec.
(12/15/20ns part)
t
OE
- / 8/10ns
- / 7 /9 ns
t
CW
- /12/ - ns
- /11/ - ns
t
HZ
8/10/10ns
6/ 7/10ns
t
OHZ
- / 8 / - ns
- / 7 / - ns
t
DW
- / 9 / - ns
- / 8 / - ns
Draft Data
Apr. 1st, 1994
May 14th,1994
Oct. 4th, 1994
Feb. 22th, 1996
Feb. 25th, 1998
K6E0808C1C-C
CMOS SRAM
PRELIMINARY
Rev 4.0
- 2 -
February 1998
PIN FUNCTION
Pin Name
Pin Function
A
0
- A
14
Address Inputs
WE
Write Enable
CS
Chip Select
OE
Output Enable
I/O
1
~ I/O
8
Data Inputs/Outputs
V
CC
Power(+5.0V)
V
SS
Ground
32K x 8 Bit High-Speed CMOS Static RAM
The K6E0808C1C is a 262,144-bit high-speed Static Random
Access Memory organized as 32,768 words by 8 bits. The
K6E0808C1C uses 8 common input and output lines and has
an output enable pin which operates faster than address access
time at read cycle. The device is fabricated using SAMSUNG
s
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The K6E0808C1C is packaged
in a 300mil 28-pin plastic SOJ or TSOP1 forward.
GENERAL DESCRIPTION
FEATURES
Fast Access Time 12, 15, 20ns(Max.)
Low Power Dissipation
Standby (TTL) : 40mA(Max.)
(CMOS) : 2mA(Max.)
Operating K6E0808C1C-12 : 165mA(Max.)
K6E0808C1C-15 : 150mA(Max.)
K6E0808C1C-20 : 140mA(Max.)
Single 5.0V
10% Power Supply
TTL Compatible Inputs and Outputs
I/O Compatible with 3.3V Device
Fully Static Operation
- No Clock or Refresh required
Three State Outputs
Standard Pin Configuration
K6E0808C1C-J : 28-SOJ-300
K6E0808C1C-T : 28-TSOP1-0813. 4F
Clk Gen.
A
3
I/O
1
~I/O
8
CS
WE
OE
PIN CONFIGURATION
(Top View)
FUNCTIONAL BLOCK DIAGRAM
A
4
A
5
A
6
A
7
A
8
A
12
A
13
A
14
R
o
w
S
e
l
e
c
t
Data
Cont.
A
0
A
1
A
2
A
9
A
10
A
11
CLK
Gen.
Pre-Charge-Circuit
Memory Array
512 Rows
64x8 Columns
SOJ
TSOP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OE
A
11
A
9
A
8
A
13
WE
Vcc
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
10
CS
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
Vss
I/O
3
I/O
2
I/O
1
A
0
A
1
A
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
1
I/O
2
I/O
3
Vss
Vcc
WE
A
13
A
8
A
9
A
11
OE
A
10
CS
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
Column Select
I/O Circuit
K6E0808C1C-C
CMOS SRAM
PRELIMINARY
Rev 4.0
- 3 -
February 1998
ABSOLUTE MAXIMUM RATINGS*
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Parameter
Symbol
Rating
Unit
Voltage on Any Pin Relative to V
SS
V
IN
,
V
OUT
-0.5 to 7.0
V
Voltage on V
CC
Supply Relative to V
SS
V
CC
-0.5 to 7.0
V
Power Dissipation
P
D
1.0
W
Storage Temperature
T
STG
-65 to 150
C
Operating Temperature
T
A
0 to 70
C
RECOMMENDED DC OPERATING CONDITIONS
(T
A
=0 to 70
C)
* V
IL
(Min) = -2.0(Pulse Width
10ns) for I
20mA
** V
IH
(Max) = V
CC
+2.0V(Pulse Width
10ns) for I
20mA
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
V
CC
4.5
5.0
5.5
V
Ground
V
SS
0
0
0
V
Input High Voltage
V
IH
2.2
-
V
CC
+0.5**
V
Input Low Voltage
V
IL
-0.5*
-
0.8
V
DC AND OPERATING CHARACTERISTICS
(T
A
=0 to 70
C,V
CC
=5.0V
10% unless otherwise specified)
* V
CC
=5.0V
5%, Temp.=25
C
Parameter
Symbol
Test Conditions
Min
Max
Unit
Input Leakage Current
I
LI
V
IN
= V
SS
to
V
CC
-2
2
A
Output Leakage Current
I
LO
CS=V
IH
or OE=V
IH
or WE=V
IL
V
OUT
= V
SS
to
V
CC
-2
2
A
Operating Current
I
CC
Min. Cycle, 100% Duty
CS=V
IL,
V
IN
= V
IH
or
V
IL,
I
OUT
=0mA
12ns
-
165
mA
15ns
-
150
20ns
-
140
Standby Current
I
SB
Min. Cycle, CS=V
IH
-
40
mA
I
SB1
f=0MHz, CS
V
CC
-0.2V,
V
IN
V
CC
-0.2V or
V
IN
0.2V
-
2
mA
Output Low Voltage Level
V
OL
I
OL
=8mA
-
0.4
V
Output High Voltage Level
V
OH
I
OH
=-4mA
2.4
-
V
V
OH1*
I
OH1
=0.1mA
-
3.95
V
CAPACITANCE*
(T
A
=25
C, f=1.0MHz)
* Capacitance is sampled and not 100% tested.
Item
Symbol
Test Conditions
MIN
Max
Unit
Input/Output Capacitance
C
I/O
V
I/O
=0V
-
8
pF
Input Capacitance
C
IN
V
IN
=0V
-
7
pF
K6E0808C1C-C
CMOS SRAM
PRELIMINARY
Rev 4.0
- 4 -
February 1998
TEST CONDITIONS
Parameter
Value
Input Pulse Levels
0V to 3V
Input Rise and Fall Times
3ns
Input and Output timing Reference Levels
1.5V
Output Loads
See below
AC CHARACTERISTICS
(T
A
=0
to 70
C, V
CC
=5.0V
10%, unless otherwise noted.)
Output Loads(A)
Output Loads(B)
D
OUT
5pF*
480
255
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
+5.0V
READ CYCLE
Parameter
Symbol
K6E0808C1C-12
K6E0808C1C-15
K6E0808C1C-20
Unit
Min
Max
Min
Max
Min
Max
Read Cycle Time
t
RC
12
-
15
-
20
-
ns
Address Access Time
t
AA
-
12
-
15
-
20
ns
Chip Select to Output
t
CO
-
12
-
15
-
20
ns
Output Enable to Valid Output
t
OE
-
6
-
7
-
9
ns
Chip Enable to Low-Z Output
t
LZ
3
-
3
-
3
-
ns
Output Enable to Low-Z Output
t
OLZ
0
-
0
-
0
-
ns
Chip Disable to High-Z Output
t
HZ
0
6
0
7
0
10
ns
Output Disable to High-Z Output
t
OHZ
0
6
0
7
0
10
ns
Output Hold from Address Change
t
OH
3
-
3
-
3
-
ns
Chip Selection to Power Up Time
t
PU
0
-
0
-
0
-
ns
Chip Selection to Power DownTime
t
PD
-
12
-
15
-
20
ns
D
OUT
30pF*
480
255
+5V
* Including Scope and Jig Capacitance
K6E0808C1C-C
CMOS SRAM
PRELIMINARY
Rev 4.0
- 5 -
February 1998
WRITE CYCLE
Parameter
Symbol
K6E0808C1C-12
K6E0808C1C-15
K6E0808C1C-20
Unit
Min
Max
Min
Max
Min
Max
Write Cycle Time
t
WC
12
-
15
-
20
-
ns
Chip Select to End of Write
t
CW
9
-
11
-
13
-
ns
Address Setup Time
t
AS
0
-
0
-
0
-
ns
Address Valid to End of Write
t
AW
9
-
12
-
13
-
ns
Write Pulse Width(OE High)
t
WP
9
-
12
-
13
-
ns
Write Pulse Width(OE Low)
t
WP1
12
-
15
-
20
-
ns
Write Recovery Time
t
WR
0
-
0
-
0
-
ns
Write to Output High-Z
t
WHZ
0
6
0
8
0
8
ns
Data to Write Time Overlap
t
DW
7
-
8
-
10
-
ns
Data Hold from Write Time
t
DH
0
-
0
-
0
-
ns
End Write to Output Low-Z
t
OW
0
-
0
-
0
-
ns
Address
Data Out
Previous Valid Data
Valid Data
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS=OE=V
IL
, WE=V
IH
)
t
AA
t
RC
t
OH
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
CS
Address
OE
Data out
t
AA
t
OLZ
t
LZ(4,5)
t
OH
t
OHZ
t
RC
t
OE
t
CO
t
PU
t
PD
Valid Data
t
HZ(3,4,5)
50%
50%
V
CC
Current
I
CC
I
SB
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