CMOS SRAM
K6F1008R2A Family
Revision 1.0
July 1999
- 1 -
Document Title
128Kx8 bit Super Low Power and Low Voltage CMOS Static RAM
Revision History
Revision No.
0.0
1.0
Remark
Advance
Final
History
Design target
Finalize
- Change Operating Voltage Range 1.7~2.2V to 1.65~2.2V.
Draft Data
November 3, 1998
July 16, 1999
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices.
CMOS SRAM
K6F1008R2A Family
Revision 1.0
July 1999
- 2 -
128Kx8 bit Super Low Power and Low Voltage CMOS Static RAM
GENERAL DESCRIPTION
The K6F1008R2A families are fabricated by SAMSUNG
s
advanced full CMOS process technology. The families support
industrial temperature range and have various package types
for user flexibility of system design. The families also support
low data retention voltage for battery back-up operation with low
data retention current.
FEATURES
Process Technology: Full CMOS
Organization: 128K x8 bit
Power Supply Voltage: 1.65~2.2V
Low Data Retention Voltage: 1.0V(Min)
Three state output status and TTL Compatible
Package Type: 32-TSOP1-0813.4F
48-FBGA-6.00x7.00
Name
Function
Name
Function
CS
1
,CS
2
Chip Select Inputs
I/O
1
~I/O
8
Data Inputs/Outputs
OE
Output Enable Input
Vcc
Power
WE
Write Enable Input
Vss
Ground
A
0
~A
16
Address Inputs
N.C.
No Connection
FUNCTIONAL BLOCK DIAGRAM
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
Precharge circuit.
Memory array
1024 rows
128
8 columns
I/O Circuit
Column select
Clk gen.
Row
select
I/O
1
Data
cont
Data
cont
I/O
8
CS
1
WE
OE
CS
2
Control
logic
PRODUCT FAMILY
1. The parameter is measured with 30pF test load.
Product Family
Operating Temperature
Vcc Range
Speed
Power Dissipation
PKG Type
Standby
(I
SB1
, Typ.)
Operating
(I
CC1
, Max)
K6F1008R2A-I
Industrial(-40~85
C)
1.65~2.2V
70
1)
/100ns
0.5
A
2mA
32-sTSOP1-0813.4F
48-FBGA-6.00x7.00
PIN DESCRIPTION
A11
A9
A8
A13
WE
CS2
A15
VCC
N.C
A16
A14
A12
A7
A6
A5
A4
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
32-sTSOP
Type1-Forward
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
0
A
1
CS
2
A
3
A
6
A
8
I/O
5
A
2
WE
A
4
A
7
I/O
1
I/O
6
NC
A
5
I/O
2
V
SS
V
CC
V
CC
V
SS
I/O
7
NC
NC
I/O
3
I/O
8
OE
CS
1
A
16
A
15
I/O
4
A
9
A
10
A
11
A
12
A
13
A
14
1
2
3
4
5
6
A
B
C
D
E
F
G
H
48-FBGA - TOP VIEW
CMOS SRAM
K6F1008R2A Family
Revision 1.0
July 1999
- 3 -
PRODUCT LIST
Industrial Temperature Products(-40~85
C)
Part Name
Function
K6F1008R2A-YI70
K6F1008R2A-YI10
K6F1008R2A-FI70
K6F1008R2A-FI10
32-sTSOP1 F, 70ns, 1.8//2.0V
32-sTSOP1 F, 100ns, 1.8//2.0V
48-FBGA, 70ns, 1.8//2.0V
48-FBGA, 100ns, 1.8/2.0V
FUNCTIONAL DESCRIPTION
1. X means don
t care (Must be high or low states)
CS
1
CS
2
OE
WE
I/O
Mode
Power
H
X
1)
X
1)
X
1)
High-Z
Deselected
Standby
X
1)
L
X
1)
X
1)
High-Z
Deselected
Standby
L
H
H
H
High-Z
Output Disabled
Active
L
H
L
H
Dout
Read
Active
L
H
X
1)
L
Din
Write
Active
ABSOLUTE MAXIMUM RATINGS
1)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Item
Symbol
Ratings
Unit
Voltage on any pin relative to Vss
V
IN
,V
OUT
-0.2 to 3.0V
V
Voltage on Vcc supply relative to Vss
V
CC
-0.2 to 3.6V
V
Power Dissipation
P
D
1.0
W
Storage temperature
T
STG
-55 to 150
C
Operating Temperature
T
A
-40 to 85
C
CMOS SRAM
K6F1008R2A Family
Revision 1.0
July 1999
- 4 -
CAPACITANCE
1)
(f=1MHz, TA=25
C)
1. Capacitance is sampled, not 100% tested
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
C
IN
V
IN
=0V
-
8
pF
Input/Output capacitance
C
IO
V
IO
=0V
-
10
pF
DC AND OPERATING CHARACTERISTICS
1. Super low power product=1
A with special handling.
Item
Symbol
Test Conditions
Min Typ Max Unit
Input leakage current
I
LI
V
IN
=Vss to Vcc
-1
-
1
A
Output leakage current
I
LO
CS
1
=V
IH
or CS
2
=V
IL
or OE=V
IH
or WE=V
IL
, V
IO
=Vss to Vcc
-1
-
1
A
Operating power supply current
I
CC
I
IO
=0mA, CS
1
=V
IL
, CS
2
=V
IH,
V
IN
=V
IH
or V
IL
-
-
1
mA
Average operating current
I
CC1
Cycle time=1
s,
100%duty, I
IO
=0mA, CS
1
0.2V, CS
2
Vcc-0.2V, V
IN
0.2V
-
-
2
mA
I
CC2
Cycle time=Min, 100% duty,
I
IO
=0mA, CS
1
=V
IL
, CS
2
=V
IH,
V
IN
=V
IH
or V
IL
-
-
15
mA
Output low voltage
V
OL
I
OL
=0.33mA
-
-
0.2
V
Output high voltage
V
OH
I
OH
=-0.44mA
1.6
-
-
V
Standby Current(TTL)
I
SB
CS
1
=V
IH
, CS2=V
IL
, Other inputs=V
IH
or V
IL
-
-
0.3
mA
Standby Current(CMOS)
I
SB1
CS
1
Vcc-0.2V, CS
2
Vcc-0.2V or CS
2
0.2V, Other inputs=0~Vcc
-
0.5
2
1)
A
RECOMMENDED DC OPERATING CONDITIONS
1)
Note :
1. T
A
=-40 to 85
C, otherwise specified
2. Overshoot: Vcc+1.0V in case of pulse width
20ns.
3. Undershoot: -1.0V in case of pulse width
20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
Item
Symbol
Min
Typ
Max
Unit
Supply voltage
Vcc
1.65
1.8/2.0
2.2
V
Ground
Vss
0
0
0
V
Input high voltage
V
IH
1.4
-
Vcc+0.2
2)
V
Input low voltage
V
IL
-0.2
3)
-
0.4
V
CMOS SRAM
K6F1008R2A Family
Revision 1.0
July 1999
- 5 -
AC CHARACTERISTICS
(Vcc=1.65~2.2V, T
A
=-40 to 85
C)
Parameter List
Symbol
Speed Bins
Units
70ns
100ns
Min
Max
Min
Max
Read
Read cycle time
t
RC
70
-
100
-
ns
Address access time
t
AA
-
70
-
100
ns
Chip select to output
t
CO1
, t
CO2
-
70
-
100
ns
Output enable to valid output
t
OE
-
35
-
50
ns
Chip select to low-Z output
t
LZ
10
-
10
-
ns
Output enable to low-Z output
t
OLZ
5
-
5
-
ns
Chip disable to high-Z output
t
HZ
0
25
0
30
ns
Output disable to high-Z output
t
OHZ
0
25
0
30
ns
Output hold from address change
t
OH
10
-
15
-
ns
Write
Write cycle time
t
WC
70
-
100
-
ns
Chip select to end of write
t
CW
60
-
80
-
ns
Address set-up time
t
AS
0
-
0
-
ns
Address valid to end of write
t
AW
60
-
80
-
ns
Write pulse width
t
WP
55
-
70
-
ns
Write recovery time
t
WR
0
-
0
-
ns
Write to output high-Z
t
WHZ
0
25
0
30
ns
Data to write time overlap
t
DW
30
-
40
-
ns
Data hold from write time
t
DH
0
-
0
-
ns
End write to output low-Z
t
OW
5
-
5
-
ns
DATA RETENTION CHARACTERISTICS
1. CS
1
Vcc-0.2V, CS
2
Vcc-0.2V(CS
1
controlled) or CS
2
0.2V(CS
2
controlled)
Item
Symbol
Test Condition
Min
Typ
Max
Unit
Vcc for data retention
V
DR
CS
1
Vcc-0.2V
1)
1.0
-
2.2
V
Data retention current
I
DR
Vcc=1.2V, CS
1
Vcc-0.2V
1)
-
-
1
A
Data retention set-up time
t
SDR
See data retention waveform
0
-
-
ms
Recovery time
t
RDR
tRC
-
-
C
L
1)
1. Including scope and jig capacitance
R
2
2)
R
1
2)
V
TM
3)
2. R
1
=3070
,
R
2
=3150
3. V
TM
=1.8V
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
Input pulse level: 0.2 to 1.8V
Input rising and falling time: 5ns
Input and output reference voltage: 0.9V
Output load (See right):C
L
= 100pF+1TTL
C
L
=30pF+1TTL
CMOS SRAM
K6F1008R2A Family
Revision 1.0
July 1999
- 6 -
Address
Data Out
Previous Data Valid
Data Valid
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS1=OE=V
IL
, CS2=WE=V
IH
)
t
AA
t
RC
t
OH
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
Data Valid
High-Z
CS
1
Address
OE
Data out
NOTES (READ CYCLE)
1.
t
HZ
and
t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition,
t
HZ
(Max.) is less than
t
LZ
(Min.) both for a given device and from device to device
interconnection.
CS
2
t
OH
t
AA
t
OLZ
t
LZ
t
OHZ
t
HZ(1,2)
t
RC
t
CO2
t
OE
t
CO1
CMOS SRAM
K6F1008R2A Family
Revision 1.0
July 1999
- 7 -
TIMING WAVEFORM OF WRITE CYCLE(1)
(WE Controlled)
Address
CS
1
t
CW(2)
t
WR(4)
TIMING WAVEFORM OF WRITE CYCLE(2)
(CS
1
Controlled)
Address
CS
1
t
WC
t
WR(4)
t
AS(3)
CS
2
t
CW(2)
t
WP(1)
t
DW
t
DH
t
OW
t
WHZ
Data Undefined
Data Valid
WE
Data in
Data out
t
DW
t
DH
Data Valid
WE
Data in
Data out
High-Z
High-Z
CS
2
t
WC
t
AW
t
AS(3)
t
CW(2)
t
WP(1)
t
AW
CMOS SRAM
K6F1008R2A Family
Revision 1.0
July 1999
- 8 -
DATA RETENTION WAVE FORM
CS
1
controlled
V
CC
1.65V
1.4V
V
DR
CS
1
GND
Data Retention Mode
CS
1
V
CC
- 0.2V
t
SDR
t
RDR
TIMING WAVEFORM OF WRITE CYCLE(3)
(CS
2
Controlled)
Address
CS
1
t
AW
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS
1
, a high CS
2
and a low WE. A write begins at the latest transition among CS
1
goes low,
CS
2
going high and WE going low : A write end at the earliest transition among CS
1
going high, CS
2
going low and WE going high,
t
WP
is measured from the begining of write to the end of write.
2. t
CW
is measured from the CS
1
going low or CS
2
going high to the end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end of write to the address change. t
WR1
applied in case a write ends as CS
1
or WE going high t
WR2
applied
in case a write ends as CS
2
going to low.
CS
2
t
CW(2)
WE
Data in
Data Valid
Data out
High-Z
High-Z
t
CW(2)
t
WR(4)
t
WP(1)
t
DW
t
DH
t
AS(3)
t
WC
CS
2
controlled
V
CC
1.65V
0.4V
V
DR
CS
2
GND
Data Retention Mode
t
SDR
t
RDR
CS
2
0.2V
CMOS SRAM
K6F1008R2A Family
Revision 1.0
July 1999
- 9 -
PACKAGE DIMENSIONS
Units: millimeters(inches)
#32
1.00
0.10
0.039
0.004
M
A
X
8
.
4
0
0
.
3
3
1
0
.
0
0
4
0
.
1
0
#1
13.40
0.20
0.528
0.008
#17
#16
+0.10
0.20
-0.05
+0.004
0.008
-0.002
0.50
0.0197
0.25
( )
0.010
MIN
0.05
0.002
MAX
1.20
0.047
8
.
0
0
0
.
3
1
5
M
A
X
0.50
( )
0.020
11.80
0.10
0.465
0.004
0.45~0.75
0.018~0.030
+0.10
0.15
-0.05
+0.004
0.006
-0.002
0~8
TYP
0.25
0.010
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)
CMOS SRAM
K6F1008R2A Family
Revision 1.0
July 1999
- 10 -
C
1
/
2
PACKAGE OUTLINE
6
5
4
3
2
1
A
B
C
D
E
F
G
H
C
B/2
B
C
1
B
C
Bottom View
Top View
D
E
2
E
1
E
C
Side View
0
.
8
5
/
T
y
p
.
0
.
2
5
/
T
y
p
.
A
Y
Detail A
Min
Typ
Max
A
-
0.75
-
B
5.90
6.00
6.10
B1
-
3.75
-
C
6.90
7.00
7.10
C1
-
5.25
-
D
0.30
0.35
0.40
E
-
1.10
1.20
E1
-
0.85
-
E2
0.20
0.25
0.30
Y
-
-
0.08
0.50
0.50
B1
#A1
0
.
3
0
A1 INDEX MARK
Notes.
1. Bump counts: 48(8row x 6column)
2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.)
3. All tolerence are +/-0.050 unless
otherwise specified.
4. Typ : Typical
5. Y is coplanarity: 0.08(Max)
Units: millimeters
48 BALL FINE PITCH BGA(0.75mm ball pitch)
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