Revision 3.0

CMOS SRAM

July 1998

K6F1008V2M, K6F1008S2M, K6F1008R2M Family

Document Title

128K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM

Revision History

Revision No.

0.0

0.1

1.0

2.0

3.0

Remark

Advance

Preliminary

Final

History

Initial draft

Revise
- Erase 100ns from KM68FS1000 Family
- Add 150ns for KM68FS1000 Family
- Add 32-sTSOP1 new package
- Add high power version
I

SB1

=5.0

A(Max)

- Change V

(Min) 1.0 to 1.5V

Finalize
- Concept change high power version to low low power version
I

SB1

.0µ

A(Max)

- Change super low power version with special handling
I

SB1

=1.0

A(Max)

- Icc & Icc1(Read) decrease 10 to 5mA

Revise
- Change datasheet format
- Remove reverse type package from product
- Remove reserved speed bin(100ns)

Revise
- Add CSP type packaged product.
- Improved I

CC2

Draft Date

March 15, 1996

July 7, 1996

December 1, 1996

February 26, 1998

July 29, 1998

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and

products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.

Revision 3.0

CMOS SRAM

July 1998

K6F1008V2M, K6F1008S2M, K6F1008R2M Family

128K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM

GENERAL DESCRIPTION

The K6F1008V2M, K6F1008S2M and K6F1008R2M families
are fabricated by SAMSUNG

s advanced Full CMOS process

technology. The families support various operating temperature

range and have various package types for user flexibility of sys-

tem design. The families also support low data retention voltage

for battery back-up operation with low data retention current.

FEATURES

Process Technology: Full CMOS

Organization: 128K x8 bit

Power Supply Voltage

K6F1008V2M Family: 3.0V ~ 3.6V
K6F1008S2M Family: 2.3V ~ 3.3V
K6F1008R2M Family: 1.8V ~ 2.7V

Low Data Retention Voltage: 1.5V(Min)

Three state output and TTL Compatible

Package Type: 32-SOP-525, 32-TSOP1-0820F,

32-TSOP1-0813.4F, 48-CSP

PIN DESCRIPTION

Name

Function

Name

Function

Name

Function

Name

Function

,CS

Chip Select Input

Output Enable Input

Vcc

Power

I/O

~I/O

Data Inputs/Outputs

N.C.

No Connection

Write Enable Input

Vss

Ground

Address Inputs

FUNCTIONAL BLOCK DIAGRAM

PRODUCT FAMILY

1. The parameter is measured with 30pF test load.
2. 1

A for super low power version with special handling.

Product Family Operating Temperature Vcc Range

Speed(ns)

Power Dissipation

PKG Type

Standby

SB1

, Max)

Operating

CC2

, Max)

K6F1008V2M-C

Commercial(0~70

3.0~3.6V

/85@V

=3.3

0.3V

40mA

32-SOP

32-TSOP1

Forward

32-sTSOP1

Forward

48-CSP

K6F1008S2M-C

2.3~3.3V

/85@V

=3.0

0.3V

35mA

120

/150@V

=2.5

0.2V

30mA

K6F1008R2M-C

1.8~2.7V

300

=2.0

0.2V

15mA

K6F1008V2M-I

Industrial(-40~85

3.0~3.6V

/85@V

=3.3

0.3V

40mA

K6F1008S2M-I

2.3~3.3V

/85/100@V

=3.0

0.3V

35mA

120

/150@V

=2.5

0.2V

30mA

K6F1008R2M-I

1.8~2.7V

300

=2.0

0.2V

15mA

A11

A13

CS2

A15

VCC

N.C
A16
A14
A12

A7
A6
A5
A4

OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3

32-sTSOP

Type1-Forward

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

N.C

A16

A14

A12

I/O1

I/O2

I/O3

VSS

VCC

A15

CS2

A13

A11

A10

CS1

I/O8

I/O7

I/O6

I/O5

I/O4

32-SOP

32-TSOP

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

Precharge circuit.

Memory array
1024 rows
128

8 columns

I/O Circuit

Column select

Clk gen.

Row
select

A10

A11

A13

A15

A16

CS1

CS2

I/O

Data
cont

I/O

A14

A12

Control
logic

I/O

48-CSP - TOP VIEW

Revision 3.0

CMOS SRAM

July 1998

K6F1008V2M, K6F1008S2M, K6F1008R2M Family

PRODUCT LIST

Commercial Temperature Products(0~70

Industrial Temperature Products(-40~85

Part Name

Function

Part Name

Function

K6F1008V2M-GC70
K6F1008V2M-GC85
K6F1008V2M-TC70
K6F1008V2M-TC85

K6F1008S2M-GC12
K6F1008S2M-GC15
K6F1008S2M-TC12
K6F1008S2M-TC15
K6F1008S2M-YC12
K6F1008S2M-YC15

K6F1008R2M-GC30
K6F1008R2M-TC30
K6F1008R2M-YC30

32-SOP, 70ns, 3.3V
32-SOP, 85ns, 3.3V
32-TSOP1 F, 70ns, 3.3V
32-TSOP1 F, 85ns, 3.3V

32-SOP, 120/70ns, 2.5/3.0V
32-SOP, 150/85ns, 2.5/3.0V
32-TSOP1 F, 120/70ns, 2.5/3.0V
32-TSOP1 F, 150/85ns, 2.5/3.0V
32-sTSOP1 F, 120/70ns, 2.5/3.0V
32-sTSOP1 F, 150/85ns, 2.5/3.0V

32-SOP, 300ns, 2.0/2.5V
32-TSOP1 F, 300ns, 2.0/2.5V
32-sTSOP1 F, 300ns, 2.0/2.5V

K6F1008V2M-GI70
K6F1008V2M-GI85
K6F1008V2M-TI70
K6F1008V2M-TI85

K6F1008S2M-GI12
K6F1008S2M-GI15
K6F1008S2M-TI12
K6F1008S2M-TI15
K6F1008S2M-YI12
K6F1008S2M-YI15
K6F1008S2M-ZI15

K6F1008R2M-GI30
K6F1008R2M-TI30
K6F1008R2M-YI30
K6F1008R2M-ZI30

32-SOP, 70ns, 3.3V
32-SOP, 85ns, 3.3V
32-TSOP1 F, 70ns, 3.3V
32-TSOP1 F, 85ns, 3.3V

32-SOP, 120/70ns, 2.5/3.0V
32-SOP, 150/85ns, 2.5/3.0V
32-TSOP1 F, 120/70ns, 2.5/3.0V
32-TSOP1 F, 150/85ns, 2.5/3.0V
32-sTSOP1 F, 120/70ns, 2.5/3.0V
32-sTSOP1 F, 150/85ns, 2.5/3.0V
48-CSP, 150/100ns, 2.5/3.0V

32-SOP, 300ns, 2.0/2.5V
32-TSOP1 F, 300ns, 2.0/2.5V
32-sTSOP1 F, 300ns, 2.0/2.5V
48-CSP, 300ns, 2.0/2.5V

FUNCTIONAL DESCRIPTION

1. X means don

t care. (Must be high or low states)

I/O

Mode

Power

High-Z

Deselected

Standby

High-Z

Deselected

Standby

High-Z

Output Disabled

Active

Dout

Read

Active

Din

Write

Active

ABSOLUTE MAXIMUM RATINGS

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be

restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. V

OUT

=-0.2 to 3.9V for K6F1008V2M Family.

3. Maximum V

=-0.2 to 4.6V for K6F1008V2M Family.

Item

Symbol

Ratings

Unit

Remark

Voltage on any pin relative to Vss

OUT

-0.2 to 3.6V

Voltage on Vcc supply relative to Vss

-0.2 to 4.0V

Power Dissipation

1.0

Storage temperature

STG

-55 to 150

Operating Temperature

0 to 70

K6F1008V2M-C, K6F1008S2M-C, K6F1008R2M-C

-40 to 85

K6F1008V2M-I, K6F1008S2M-I, K6F1008R2M-I

Soldering temperature and time

SOLDER

260

C, 5sec (Lead Only)

Revision 3.0

CMOS SRAM

July 1998

K6F1008V2M, K6F1008S2M, K6F1008R2M Family

RECOMMENDED DC OPERATING CONDITIONS

Note
1 Commercial Product : T

=0 to 70

C, unless otherwise specified

Industrial Product : T

=-40 to 85

C, unless otherwise specified

2. Overshoot : Vcc + 1.0V in case of pulse width

20ns

3. Undershoot : -1.0V in case of pulse width

20ns

4. Overshoot and undershoot are sampled, not 100% tested.

Item

Symbol

Product

Min

Typ

Max

Unit

Supply voltage

Vcc

K6F1008V2M

Family

3.0

3.3

3.6

K6F1008S2M

Family

2.3

2.5/3.0

3.3

K6F1008R2M

Family

1.8

2.0/2.5

2.7

Ground

Vss

All Family

Input high voltage

K6F1008V2M

Family

Vcc=3.3

0.3V

2.2

Vcc+0.2

K6F1008S2M

Family

Vcc=3.0

0.3V

2.2

Vcc=2.5

0.2V

2.0

K6F1008R2M

Family

Vcc=2.5

0.2V

2.0

Vcc=2.0

0.2V

1.6

Input low voltage

All Family

-0.2

0.4

CAPACITANCE

(f=1MHz, T

=25

1. Capacitance is sampled, not 100% tested

Item

Symbol

Test Condition

Min

Max

Unit

Input capacitance

=0V

Input/Output capacitance

=0V

DC AND OPERATING CHARACTERISTICS

1.K6F1008V2M Family = 40mA
2. Super low power product = 1

A with special handling.

Item

Symbol

Test Conditions

Min

Typ

Max

Unit

Input leakage current

=Vss to Vcc

-1

Output leakage current

or CS

OE=V

WE=V

IL,

=Vss to Vcc

-1

Operating power supply current

=0mA, CS

, CS

, V

or V

, Read

Average operating current

CC1

Cycle time=1

, 100% duty, I

=0mA, CS

0.2V,

-0.2V, V

0.2V or V

-0.2V

Read

Write

CC2

Cycle time=Min, 100% duty, I

=0mA,

, CS

IH,

or V

Vcc=3.3V@70ns

Vcc=2.7V@120ns

Vcc=2.2V@300ns

Output low voltage

2.1mA at Vcc=3.0/3.3V

0.4

0.5mA at Vcc=2.5V

0.33mA at Vcc=2.0V

Output high voltage

-1.0mA at Vcc=3.0/3.3V

2.4

-0.5mA at Vcc=2.5V

2.0

-0.44mA at Vcc=2.0V

1.6

Standby Current(TTL)

IL,

Other inputs=V

or V

0.3

Standby Current(CMOS)

SB1

Vcc-0.2V, CS

Vcc-0.2V or CS

0.2V, Other inputs=0~Vcc

Revision 3.0

CMOS SRAM

July 1998

K6F1008V2M, K6F1008S2M, K6F1008R2M Family

AC OPERATING CONDITIONS

TEST CONDITIONS

(Test Load and Test Input/Output Reference)

Input pulse level : 0.4 to 2.2V for Vcc=3.3V, 3.0V, 2.5V

0.4 to 1.8V for Vcc=2.0V

Input rising and falling time : 5ns
Input and output reference voltage : 1.5V for Vcc=3.3V, 3.0V

1.1V for Vcc=2.5V
0.9V for Vcc=2.0V

Output load (See right) :C

=100pF+1TTL

=30pF+1TTL

1. Including scope and jig capacitance

2. R

=3070

=3150

3. V

=2.8V for V

=3.0/3.3V

2.3V for V

=2.5V

1.8V for V

=2.0V

AC CHARACTERISTICS

(Commercial product :T

=0 to 70

C, Industrial product : T

=-40 to 85

K6F1008V2M

Family : Vcc=3.0~3.6V,

K6F1008S2M

Family : Vcc=2.3~3.3V,

K6F1008R2M

Family : Vcc=1.8~2.7V)

Parameter List

Symbol

Speed Bins

Units

70ns

85ns

100ns

120ns

150ns

300ns

Min Max Min Max Min Max Min Max Min Max Min Max

Read

Read cycle time

100

120

150

300

Address access time

100

120

150

300

Chip select to output

CO1

, t

CO2

100

120

150

300

Output enable to valid output

150

Chip select to low-Z output

LZ1

, t

LZ2

Output enable to low-Z output

OLZ

Chip disable to high-Z output

HZ1

, t

HZ2

Output disable to high-Z output

OHZ

Output hold from address change

Write

Write cycle time

100

120

150

300

Chip select to end of write

100

120

300

Address set-up time

Address valid to end of write

100

120

300

Write pulse width

100

200

Write recovery time

Write to output high-Z

WHZ

Data to write time overlap

120

Data hold from write time

End write to output low-Z

DATA RETENTION CHARACTERISTICS

Vcc-0.2V, CS

Vcc-0.2V(CS

controlled) or CS

0.2V(CS

controlled)

2. Super low power product = 1

A with special handling.

Item

Symbol

Test Condition

Min

Typ

Max

Unit

Vcc for data retention

Vcc-0.2V

1.5

3.6

Data retention current

Vcc=3.0V, CS

Vcc-0.2V

5.0

Data retention set-up time

SDR

See data retention waveform

Recovery time

RDR

Revision 3.0

CMOS SRAM

July 1998

K6F1008V2M, K6F1008S2M, K6F1008R2M Family

Address

Data Out

Previous Data Valid

Data Valid

TIMMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1)

(Address Controlled

=OE=V

, WE=V

)

TIMING WAVEFORM OF READ CYCLE(2)

(WE=V

)

Data Valid

High-Z

Address

Data out

NOTES (READ CYCLE)

and

OHZ

are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition,

(Max.) is less than

(Min.) both for a given device and from device to device

interconnection.

OLZ

OHZ

HZ(1,2)

CO2

CO1

Revision 3.0

CMOS SRAM

July 1998

K6F1008V2M, K6F1008S2M, K6F1008R2M Family

DATA RETENTION WAVE FORM

controlled

3.0/2.7/2.3/1.8V

2.2V

GND

Data Retention Mode

-0.2V

SDR

RDR

TIMING WAVEFORM OF WRITE CYCLE(3)

(CS

Controlled)

Address

NOTES (WRITE CYCLE)

1. A write occurs during the overlap of a low CS

, a high CS

and a low WE. A write begins at the latest transition among CS

goes low,

going high and WE going low: A write end at the earliest transition among CS

going high, CS

going low and WE going high,

is measured from the beginning of write to the end of write.

2. t

is measured from the CS

going low or CS

going high to the end of write.

3. t

is measured from the address valid to the beginning of write.

4. t

is measured from the end of write to the address change. t

WR(1)

applied in case a write ends as CS

or WE going high t

WR(2)

applied in case a write ends as CS

going to low.

WP(2)

Data in

Data Valid

Data out

High-Z

CW(2)

WR(4)

WP(1)

AS(3)

controlled

3.0/2.7/2.3/1.8V

0.4V

GND

Data Retention Mode

SDR

RDR

0.2V

Revision 3.0

CMOS SRAM

July 1998

K6F1008V2M, K6F1008S2M, K6F1008R2M Family

32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)

#32

1.00

0.10

0.039

0.004

MAX

8.40

0.331

.
1

.
0

0.50

( )

0.020

18.40

0.10

0.724

0.004

0.45 ~0.75

0.018 ~0.030

20.00

0.20

0.787

0.008

#17

+0.10

0.15

-0.05

+0.004

0.006

-0.002

0~8

+0.10

0.20

-0.05

+0.004

0.008

-0.002

0.50

0.0197

0.25

( )

0.010

MIN

0.05

0.002

MAX

1.20

0.047

.
0

.
3

TYP

0.25

0.010

#16

PACKAGE DIMENSIONS

#32

1.00

0.10

0.039

0.004

.
4

.
3

.
0

.
1

13.40

0.20

0.528

0.008

#17

#16

+0.10

0.20

-0.05

+0.004

0.008

-0.002

0.50

0.0197

0.25

( )

0.010

MIN

0.05

0.002

MAX

1.20

0.047

.
0

.
3

0.50

( )

0.020

11.80

0.10

0.465

0.004

0.45~0.75

0.018~0.030

+0.10

0.15

-0.05

+0.004

0.006

-0.002

0~8

TYP

0.25

0.010

32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)

Units: millimeter(inch)

Revision 3.0

CMOS SRAM

July 1998

K6F1008V2M, K6F1008S2M, K6F1008R2M Family

/
2

B/2

Ball #A1

B/2

Elastomer

SRAM Die

Ball #A1

/
2

Bottom View

Top View

Detail A

Side View

.
5

/
T

.
3

/
T

.
2

/
T

Elastomer

0.3/Typ.

Die

Detail A

Notes.

1. Bump counts : 48(8row x 6column)

2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.)

3. All tolerence are +/-0.050 unless

otherwise specified.

4. Typ : Typical

5. Y is coplanarity: 0.08(Max)

Min

Typ

Max

0.75

5.90

6.00

6.10

3.75

7.90

8.00

8.10

5.25

0.30

0.35

0.40

0.80

0.81

0.55

0.25

0.08

PACKAGE DIMENSIONS

32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)

Units: millimeter(inch)

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: K6F1008S2M-I

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: K6F1008S2M-I