K6F1616T6B Family
Revision 1.0
August 2003
1
CMOS SRAM
Document Title
1M x16 bit Super Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No.
0.0
0.1
1.0
Remark
Preliminary
Preliminary
Final
History
Initial draft
Revised
- Changed Isb1(max.) from 25uA to 15uA
Finalized
- Added Package Type '48-TBGA - 7.00x7.00'
Draft Date
May 21, 2003
June 17, 2003
August 13, 2003
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
K6F1616T6B Family
Revision 1.0
August 2003
2
CMOS SRAM
1M x 16 bit Super Low Power and Low Voltage Full CMOS Static RAM
GENERAL DESCRIPTION
The K6F1616T6B families are fabricated by SAMSUNG
s
advanced full CMOS process technology. The families support
industrial operating temperature ranges. The families also sup-
port low data retention voltage for battery back-up operation
with low data retention current.
FEATURES
Process Technology: Full CMOS
Organization: 1M x16
Power Supply Voltage: 2.7~3.6V
Low Data Retention Voltage: 1.5V(Min)
Three State Outputs
Package Type: 48-TSOP1-1220F, 48-TBGA - 7.00x7.00
Name
Function
Name
Function
CS1, CS2 Chip Select Inputs
Vcc
Power
OE
Output Enable Input
Vss
Ground
WE
Write Enable Input
UB
Upper Byte(I/O
9
~
16
)
A
0
~A
19
Address Inputs
LB
Lower Byte(I/O
1
~
8
)
I/O
1
~I/O
16
Data Inputs/Outputs
NC
No Connection
PRODUCT FAMILY
1. The parameter is measured with 30pF test load.
2. Typical value is measured at V
CC
=3.3V, T
A
=25
C and not 100% tested.
Product Family
Operating Temperature
Vcc Range
Speed
Power Dissipation
PKG Type
Standby
(I
SB1
, Typ.)
Operating
(I
CC1
, Max)
K6F1616T6B-F
Industrial(-40~85
C)
2.7~3.6V
55
1)
/70ns
5
A
2)
5mA
48-TSOP1-1220F
48-TBGA - 7.00x7.00
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
Row
select
I/O
1
~I/O
8
Data
cont
Data
cont
Data
cont
I/O
9
~I/O
16
Vcc
Vss
Precharge circuit.
Memory
Cell
Array
I/O Circuit
Column select
PIN DESCRIPTION
WE
OE
UB
CS1
LB
Control Logic
CS2
Row
Addresses
Column Addresses
48-TSOP1-1220F
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE
NC
UB
LB
A18
A17
A7
A6
A5
A4
A3
A2
A1
A16
NC
Vss
I/O16
I/O8
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
Vcc
I/O12
I/O4
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
OE
Vss
CS1
A0
CS2
48-TBGA: Top View (Ball Down)
LB
OE
A0
A1
A2
CS2
I/O9
UB
A3
A4
CS1
I/O1
I/O10
I/O11
A5
A6
I/O2
I/O3
Vss
I/O12
A17
A7
I/O4
Vcc
Vcc
I/O13
Vss
A16
I/O5
Vss
I/O15
I/O14
A14
A15
I/O6
I/O7
I/O16
A19
A12
A13
WE
I/O8
A18
A8
A9
A10
A11
NC
1
2
3
4
5
6
A
B
C
D
E
F
G
H
K6F1616T6B Family
Revision 1.0
August 2003
3
CMOS SRAM
PRODUCT LIST
Industrial Temperature Products(-40~85
C)
Part Name
Function
K6F1616T6B-TF55
K6F1616T6B-TF70
K6F1616T6B-EF55
K6F1616T6B-EF70
48-TSOP1-1220F, 55ns, 3.0V/3.3V
48-TSOP1-1220F, 70ns, 3.0V/3.3V
48-TBGA, 55ns, 3.0V/3.3V
48-TBGA, 70ns, 3.0V/3.3V
ABSOLUTE MAXIMUM RATINGS
1)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Item
Symbol
Ratings
Unit
Voltage on any pin relative to Vss
V
IN
,V
OUT
-0.2 to V
CC
+0.3V(Max. 4.2V)
V
Voltage on Vcc supply relative to Vss
V
CC
-0.2 to 4.2
V
Power Dissipation
P
D
1.0
W
Storage temperature
T
STG
-65 to 150
C
Operating Temperature
T
A
-40 to 85
C
FUNCTIONAL DESCRIPTION
1. X means don
t care. (Must be low or high state)
CS
1
CS
2
OE
WE
LB
UB
I/O
1~8
I/O
9~16
Mode
Power
H
X
1)
X
1)
X
1)
X
1)
X
1)
High-Z
High-Z
Deselected
Standby
X
1)
L
X
1)
X
1)
X
1)
X
1)
High-Z
High-Z
Deselected
Standby
X
1)
X
1)
X
1)
X
1)
H
H
High-Z
High-Z
Deselected
Standby
L
H
H
H
L
X
1)
High-Z
High-Z
Output Disabled
Active
L
H
H
H
X
1)
L
High-Z
High-Z
Output Disabled
Active
L
H
L
H
L
H
Dout
High-Z
Lower Byte Read
Active
L
H
L
H
H
L
High-Z
Dout
Upper Byte Read
Active
L
H
L
H
L
L
Dout
Dout
Word Read
Active
L
H
X
1)
L
L
H
Din
High-Z
Lower Byte Write
Active
L
H
X
1)
L
H
L
High-Z
Din
Upper Byte Write
Active
L
H
X
1)
L
L
L
Din
Din
Word Write
Active
K6F1616T6B Family
Revision 1.0
August 2003
4
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS
1)
Note:
1. T
A
=-40 to 85
C, otherwise specified
2. Overshoot: V
CC
+2.0V in case of pulse width
20ns.
3. Undershoot: -2.0V in case of pulse width
20ns.
4. Overshoot and Undershoot are sampled, not 100% tested.
Item
Symbol
Min
Typ
Max
Unit
Supply voltage
Vcc
2.7
3.0/3.3
3.6
V
Ground
Vss
0
0
0
V
Input high voltage
V
IH
2.2
-
Vcc+0.2
2)
V
Input low voltage
V
IL
-0.2
3)
-
0.6
V
CAPACITANCE
1)
(f=1MHz, T
A
=25
C)
1. Capacitance is sampled, not 100% tested
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
C
IN
V
IN
=0V
-
8
pF
Input/Output capacitance
C
IO
V
IO
=0V
-
10
pF
DC AND OPERATING CHARACTERISTICS
1. Typical values are measured at V
CC
=3.3V, T
A
=25
C and not 100% tested.
Item
Symbol
Test Conditions
Min
Typ
1)
Max
Unit
Input leakage current
I
LI
V
IN
=Vss to Vcc
-1
-
1
A
Output leakage current
I
LO
CS
1
=V
IH
or CS
2
=V
IL
or OE=V
IH
or WE=V
IL
or LB=UB=V
IH
,
V
IO
=Vss to Vcc
-1
-
1
A
Average operating current
I
CC1
Cycle time=1
s, 100%duty, I
IO
=0mA, CS
1
0.2V, LB
0.2V
or/and UB
0.2V, CS
2
Vcc-0.2V, V
IN
0.2V or V
IN
V
CC
-0.2V
-
-
5
mA
I
CC2
Cycle time=Min, I
IO
=0mA, 100% duty, CS
1
=V
IL
,
CS
2
=V
IH
, LB=V
IL
or/and UB=V
IL
, V
IN
=V
IL
or V
IH
70ns
-
-
25
mA
55ns
-
-
30
Output low voltage
V
OL
I
OL
= 2.1mA
-
-
0.4
V
Output high voltage
V
OH
I
OH
= -1.0mA
2.4
-
-
V
Standby Current (CMOS)
I
SB1
Other input =0~Vcc
1) CS
1
Vcc-0.2V, CS
2
Vcc-0.2V(CS
1
controlled) or
2) 0V
CS
2
0.2V(CS
2
controlled)
-
5.0
15
A
K6F1616T6B Family
Revision 1.0
August 2003
5
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Input/Output Reference)
Input pulse level: 0.2V to Vcc-0.2V
Input rising and falling time: 5ns
Input and output reference voltage:1.5V
Output load(see right): C
L
=100pF+1TTL
C
L
=30pF+1TTL
AC CHARACTERISTICS
(Vcc=2.7~3.6V, T
A
=-40 to 85
C)
Parameter List
Symbol
Speed Bins
Units
55ns
70ns
Min
Max
Min
Max
Read
Read cycle time
t
RC
55
-
70
-
ns
Address access time
t
AA
-
55
-
70
ns
Chip select to output
t
CO
-
55
-
70
ns
Output enable to valid output
t
OE
-
25
-
35
ns
LB, UB valid to data output
t
BA
-
55
-
70
ns
Chip select to low-Z output
t
LZ
10
-
10
-
ns
Output enable to low-Z output
t
OLZ
5
-
5
-
ns
LB, UB enable to low-Z output
t
BLZ
10
-
10
-
ns
Output hold from address change
t
OH
10
-
10
-
ns
Chip disable to high-Z output
t
HZ
0
20
0
25
ns
OE disable to high-Z output
t
OHZ
0
20
0
25
ns
UB, LB disable to high-Z output
t
BHZ
0
20
0
25
ns
Write
Write cycle time
t
WC
55
-
70
-
ns
Chip select to end of write
t
CW
45
-
60
-
ns
Address set-up time
t
AS
0
-
0
-
ns
Address valid to end of write
t
AW
45
-
60
-
ns
Write pulse width
t
WP
40
-
50
-
ns
Write recovery time
t
WR
0
-
0
-
ns
Write to output high-Z
t
WHZ
0
20
0
20
ns
Data to write time overlap
t
DW
25
-
30
-
ns
Data hold from write time
t
DH
0
-
0
-
ns
End write to output low-Z
t
OW
5
-
5
-
ns
LB, UB valid to end of write
t
BW
45
-
60
-
ns
C
L
1)
1. Including scope and jig capacitance
R
2
2)
R
1
2)
V
TM
3)
2. R
1
=3070
,
R
2
=3150
3. V
TM
=2.8V
DATA RETENTION CHARACTERISTICS
1.
1) CS
1
Vcc-0.2V, CS
2
Vcc-0.2V(CS
1
controlled) or
2) 0
CS
2
0.2V(CS
2
controlled)
2. Typical value are measured at T
A
=25
C and not 100% tested.
Item
Symbol
Test Condition
Min
Typ
Max
Unit
Vcc for data retention
VDR
CS
1
Vcc-0.2V
1)
, V
IN
0V
1.5
-
3.6
V
Data retention current
IDR
Vcc=1.5V, CS
1
Vcc-0.2V
1)
, V
IN
0V
-
1.0
2)
10
A
Data retention set-up time
tSDR
See data retention waveform
0
-
-
ns
Recovery time
tRDR
tRC
-
-
K6F1616T6B Family
Revision 1.0
August 2003
6
CMOS SRAM
Address
Data Out
Previous Data Valid
Data Valid
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS
1
=OE=V
IL
, CS
2
=WE=V
IH
, UB or/and LB=V
IL
)
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
Data Valid
High-Z
t
RC
CS
1
Address
UB, LB
OE
Data out
t
AA
t
RC
t
OH
t
OH
t
AA
t
CO
t
BA
t
OE
t
OLZ
t
BLZ
t
LZ
t
OHZ
t
BHZ
t
HZ
NOTES (READ CYCLE)
1.
t
HZ
and
t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition,
t
HZ
(Max.) is less than
t
LZ
(Min.) both for a given device and from device to device
interconnection.
CS
2
K6F1616T6B Family
Revision 1.0
August 2003
7
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(2)
(CS
1
Controlled)
Address
Data Valid
UB, LB
WE
Data in
Data out
High-Z
High-Z
t
WC
t
CW(2)
t
AW
t
BW
t
WP(1)
t
DH
t
DW
t
WR(4)
t
AS(3)
CS
1
CS
2
TIMING WAVEFORM OF WRITE CYCLE(1)
(WE Controlled)
Address
CS
1
Data Undefined
UB, LB
WE
Data in
Data out
t
WC
t
CW(2)
t
WR(4)
t
AW
t
BW
t
WP(1)
t
AS(3)
t
DH
t
DW
t
WHZ
t
OW
High-Z
High-Z
Data Valid
CS
2
K6F1616T6B Family
Revision 1.0
August 2003
8
CMOS SRAM
DATA RETENTION WAVEFORM
V
CC
2.7V
2.2V
V
DR
GND
Data Retention Mode
t
SDR
t
RDR
CS
2
controlled
V
CC
2.7V
0.4V
V
DR
CS
2
GND
Data Retention Mode
t
SDR
t
RDR
CS
2
0.2V
CS
1
controlled
CS
1
CS
1
V
CC
- 0.2V
Address
Data Valid
UB, LB
WE
Data in
Data out
High-Z
High-Z
TIMING WAVEFORM OF WRITE CYCLE(3)
(UB, LB Controlled)
NOTES
(WRITE CYCLE)
1. A wri
t
e occurs during the overlap(t
WP
) of low CS
1
and low WE. A write begins when CS
1
goes low and WE goes low with asserting
UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest tran-
sition when CS
1
goes high and WE goes high. The
t
WP
is measured from the beginning of write to the end of write.
2.
t
CW
is measured from the CS
1
going low to the end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4.
t
WR
is measured from the end of write to the address change.
t
WR
is applied in case a write ends with CS
1
or WE going high.
t
WC
t
CW(2)
t
BW
t
WP(1)
t
DH
t
DW
t
WR(4)
t
AW
t
AS(3)
CS
1
CS
2
K6F1616T6B Family
Revision 1.0
August 2003
9
CMOS SRAM
PACKAGE DIMENSIONS
48-PIN LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220F
Unit :mm/Inch
0.787
0.008
20.00
0.20
#1
#24
0
.
2
0
+
0
.
0
7
-
0
.
0
3
0
.
0
0
8
+
0
.
0
0
3
-
0
.
0
0
1
0
.
5
0
0
.
0
1
9
7
#48
#25
0
.
4
8
8
1
2
.
4
0
M
A
X
1
2
.
0
0
0
.
4
7
2
0
.
1
0
0
.
0
0
4
M
A
X
0
.
2
5
0
.
0
1
0
(
)
0.039
0.002
1.00
0.05
0.002
0.05
MIN
0.047
1.20
MAX
0.45~0.75
0.018~0.030
0.724
0.004
18.40
0.10
0~8'C
0
.
0
1
0
0
.
2
5
T
Y
P
0
.
1
2
5
+
0
.
0
7
5
-
0
.
0
3
5
0
.
0
0
5
+
0
.
0
0
3
-
0
.
0
0
1
0.50
0.020
(
)
K6F1616T6B Family
Revision 1.0
August 2003
10
CMOS SRAM
C
B
C
1
B
B1
C
1
/
PACKAGE DIMENSION
6
5
4
3
2
1
A
B
C
D
E
F
G
H
C
B1/2
Bottom View
Top View
D
E
2
E
1
E
C
Side View
0
.
5
5
/
T
y
p
.
0
.
3
5
/
T
y
p
.
A
Y
Detail A
Min
Typ
Max
A
-
0.75
-
B
6.90
7.00
7.10
B1
-
3.75
-
C
6.90
7.00
7.10
C1
-
5.25
-
D
0.40
0.45
0.50
E
0.80
0.90
1.00
E1
-
0.55
-
E2
0.30
0.35
0.40
Y
-
-
0.1
#A1
Notes.
1. Bump counts: 48(8 row x 6 column)
2. Bump pitch: (x,y)=(0.75 x 0.75)(typ.)
3. All tolerence are
0.050 unless
otherwise specified.
4. Typ: Typical
5. Y is coplanarity: 0.1(Max)
Unit: millimeters
48 BALL TAPE BALL GRID ARRAY(0.75mm ball pitch)
C
1
/
2
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