Revision 1.1
K6F2008V2E Family
1
May 2003
CMOS SRAM
Document Title
256Kx8 bit Super Low Power and Low Voltage Full CMOS Static RAM
Revision History
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
Revision No.
0.0
1.0
1.1
Remark
Preliminary
Final
Final
History
Initial draft
Finalize
Revised
- Added Lead Free(LF) product for 32-TSOP1-0813.4F(LF) package.
Draft Date
July 19 , 2001
September 27, 2001
May 13, 2003
Revision 1.1
K6F2008V2E Family
2
May 2003
CMOS SRAM
256Kx8 bit Super Low Power and Low Voltage Full CMOS Static RAM
GENERAL DESCRIPTION
The K6F2008V2E families are fabricated by SAMSUNG
s
advanced Full CMOS process technology. The families support
industrial temperature ranges for user flexibility of system
design. The families also supports low data retention voltage for
battery back-up operation with low data retention current.
FEATURES
Process Technology: Full CMOS
Organization: 256Kx8
Power Supply Voltage: 3.0 ~ 3.6V
Low Data Retention Voltage: 1.5V(Min)
Three State Outputs
Package Type: 32-TSOP1-0813.4F, 32-TSOP1-0813.4F(LF)
PIN DESCRIPTION
Name
Function
Name
Function
CS
1
, CS
2
Chip Select Input
I/O
1
~I/O
8
Data Inputs/Outputs
OE
Output Enable
Vcc
Power
WE
Write Enable Input
Vss
Ground
A
0
~A
17
Address Inputs
DNU
Do Not Use
FUNCTIONAL BLOCK DIAGRAM
PRODUCT FAMILY
1. The parameter is measured with 30pF test load.
2. Typical values are measured at V
CC
=3.3V, T
A
=25
C and not 100% tested.
Product Family
Operating Temperature
Vcc Range
Speed(ns)
Power Dissipation
PKG Type
Standby
(I
SB1
, Typ)
Operating
(I
CC1
, Max)
K6F2008V2E-F
Industrial(-40~85
C)
3.0~3.6V
55
1)
/70ns
0.5
A
2)
3mA
32-TSOP1-0813.4F
32-TSOP1-0813.4F(LF)
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
Precharge circuit.
Memory array
1024 rows
256x8 columns
I/O Circuit
Column select
Clk gen.
Row
select
A
d
d
r
e
s
s
I/O
1
Data
cont
Data
cont
I/O
8
CS1
CS2
WE
OE
Control
logic
Address
A11
A9
A8
A13
WE
CS2
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
32-sTSOP
Type1-Forward
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Revision 1.1
K6F2008V2E Family
3
May 2003
CMOS SRAM
PRODUCT LIST
Industrial Temperature Products(-40~85
C)
Part Name
Function
K6F2008V2E-YF55
K6F2008V2E-YF70
K6F2008V2E-LF55
K6F2008V2E-LF70
32-sTSOP1-F, 55ns, 3.3V, LL
32-sTSOP1-F, 70ns, 3.3V, LL
32-sTSOP1-F(LF), 55ns, 3.3V, LL
32-sTSOP1-F(LF), 70ns, 3.3V, LL
FUNCTIONAL DESCRIPTION
1. X means don
t care (Must be high or low states)
CS
1
CS
2
OE
WE
I/O
Mode
Power
H
X
1)
X
1)
X
1)
High-Z
Deselected
Standby
X
1)
L
X
1)
X
1)
High-Z
Deselected
Standby
L
H
H
H
High-Z
Output Disable
Active
L
H
L
H
Dout
Read
Active
L
H
X
1)
L
Din
Write
Active
ABSOLUTE MAXIMUM RATINGS
1)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Item
Symbol
Ratings
Unit
Remark
Voltage on any pin relative to Vss
V
IN
,V
OUT
-0.2 to V
CC
+0.5V
V
Voltage on Vcc supply relative to Vss
V
CC
-0.2 to 4.6V
V
Power Dissipation
P
D
1.0
W
Storage temperature
T
STG
-65 to 150
C
Operating Temperature
T
A
-40 to 85
C
K6F2008V2E-F
Revision 1.1
K6F2008V2E Family
4
May 2003
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS
1)
Note:
1. Industrial Product: T
A
=-40 to 85
C, unless otherwise specified.
2. Overshoot: Vcc+2.0V in case of pulse width
20ns.
3. Undershoot: -2.0V in case of pulse width
20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
Item
Symbol
Min
Typ.
Max
Unit
Supply voltage
Vcc
3.0
3.3
3.6
V
Ground
Vss
0
0
0
V
Input high voltage
V
IH
2.2
-
Vcc+0.2
2)
V
Input low voltage
V
IL
-0.2
3)
-
0.6
V
CAPACITANCE
1)
(f=1MHz, T
A
=25
C)
1. Capacitance is sampled, not 100% tested
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
C
IN
V
IN
=0V
-
8
pF
Input/Output capacitance
C
IO
V
IO
=0V
-
10
pF
DC AND OPERATING CHARACTERISTICS
1. Typical value are measured at V
CC
=3.3V, T
A
=25
C, and not 100% tested.
Item
Symbol
Test Conditions
Min
Typ
1)
Max
Unit
Input leakage current
I
LI
V
IN
=Vss to Vcc
-1
-
1
A
Output leakage current
I
LO
CS
1
=V
IH
or CS
2
=V
IL
or
OE=V
IH
or
WE=V
IL,
V
IO
=Vss to Vcc
-1
-
1
A
Average operating current
I
CC1
Cycle time=1
s, 100% duty, I
IO
=0mA, CS
1
0.2V,
CS
2
V
CC
-0.2V, V
IN
0.2V or V
IN
V
CC
-0.2V
-
-
3
mA
I
CC2
Cycle time=Min, 100% duty, I
IO
=0mA, CS
1
=V
IL
,
CS
2
=V
IH
, V
IN
=V
IL
or V
IH
-
-
35
mA
Output low voltage
V
OL
I
OL
=2.1mA
-
-
0.4
V
Output high voltage
V
OH
I
OH
=-1.0mA
2.4
-
-
V
Standby Current(CMOS)
I
SB1
Other inputs=Vss to Vcc
1) CS
1
Vcc-0.2V, CS2
Vcc-0.2V(CS
1
controlled) or
2) 0V
CS
2
0.2V CS
2
controlled)
-
0.5
10
A
Revision 1.1
K6F2008V2E Family
5
May 2003
CMOS SRAM
C
L
1)
1. Including scope and jig capacitance
R
2
3)
R
1
2)
V
TM
3)
2. R
1
=3070
,
R
2
=3150
3. V
TM
=2.8V
AC CHARACTERISTICS
(Vcc=3.0~3.6V, T
A
=-40 to 85
C)
1. The parameter is measured with 30pF test load.
Parameter List
Symbol
Speed Bins
Units
55ns
1)
70ns
Min
Max
Min
Max
Read
Read Cycle Time
t
RC
55
-
70
-
ns
Address Access Time
t
AA
-
55
-
70
ns
Chip Select to Output
t
CO
-
55
-
70
ns
Output Enable to Valid Output
t
OE
-
25
-
35
ns
Chip Select to Low-Z Output
t
LZ
10
-
10
-
ns
Output Enable to Low-Z Output
t
OLZ
5
-
5
-
ns
Chip Disable to High-Z Output
t
HZ
0
20
0
25
ns
Output Disable to High-Z Output
t
OHZ
0
20
0
25
ns
Output Hold from Address Change
t
OH
10
-
10
-
ns
Write
Write Cycle Time
t
WC
55
-
70
-
ns
Chip Select to End of Write
t
CW
45
-
60
-
ns
Address Set-up Time
t
AS
0
-
0
-
ns
Address Valid to End of Write
t
AW
45
-
60
-
ns
Write Pulse Width
t
WP
40
-
50
-
ns
Write Recovery Time
t
WR
0
-
0
-
ns
Write to Output High-Z
t
WHZ
0
20
0
20
ns
Data to Write Time Overlap
t
DW
25
-
30
-
ns
Data Hold from Write Time
t
DH
0
-
0
-
ns
End Write to Output Low-Z
t
OW
5
-
5
-
ns
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load (See right): C
L
=100pF+1TTL
C
L
=30pF+1TTL
DATA RETENTION CHARACTERISTICS
1.
CS
1
Vcc-0.2V, CS
2
Vcc-0.2V(CS
1
controlled) or CS
2
0.2V(CS
2
controlled).
2. Typical values are measured at T
A
=25
C and not 100% tested.
Item
Symbol
Test Condition
Min
Typ
Max
Unit
Vcc for data retention
V
DR
CS
1
Vcc-0.2V
1)
1.5
-
3.6
V
Data retention current
I
DR
Vcc=1.5V, CS
1
Vcc-0.2V
1)
-
0.2
2)
2
A
Data retention set-up time
t
SDR
See data retention waveform
0
-
-
ns
Recovery time
t
RDR
t
RC
-
-
Revision 1.1
K6F2008V2E Family
6
May 2003
CMOS SRAM
Address
Data Out
Previous Data Valid
Data Valid
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS1=OE=V
IL
, WE=V
IH
)
t
AA
t
RC
t
OH
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
Data Valid
High-Z
CS
1
Address
OE
Data out
NOTES (READ CYCLE)
1.
t
HZ
and
t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition,
t
HZ
(Max.) is less than
t
LZ
(Min.) both for a given device and from device to device
interconnection.
CS
2
t
OH
t
AA
t
OLZ
t
LZ
t
OHZ
t
HZ(1,2)
t
RC
t
CO2
t
OE
t
CO1
Revision 1.1
K6F2008V2E Family
7
May 2003
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(2)
(CS
1
Controlled)
Address
CS
1
t
WC
t
WR(4)
t
AS(3)
t
DW
t
DH
Data Valid
WE
Data in
Data out
High-Z
High-Z
CS
2
t
CW(2)
t
WP(1)
t
AW
TIMING WAVEFORM OF WRITE CYCLE(1)
(WE Controlled)
Address
CS
1
t
CW(2)
t
WR(4)
CS
2
t
WP(1)
t
DW
t
DH
t
OW
t
WHZ
Data Undefined
Data Valid
WE
Data in
Data out
t
WC
t
AW
t
AS(3)
Revision 1.1
K6F2008V2E Family
8
May 2003
CMOS SRAM
DATA RETENTION WAVE FORM
CS
1
controlled
V
CC
3.0V
2.2V
V
DR
CS
1
GND
Data Retention Mode
CS
1
V
CC
- 0.2V
t
SDR
t
RDR
CS
2
controlled
V
CC
3.0V
0.4V
V
DR
CS
2
GND
Data Retention Mode
t
SDR
t
RDR
CS
2
0.2V
TIMING WAVEFORM OF WRITE CYCLE(3)
(CS
2
Controlled)
Address
CS
1
t
AW
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS
1
, a high CS
2
and a low WE. A write begins at the latest transition among CS
1
goes low,
CS
2
going high and WE going low : A write end at the earliest transition among CS
1
going high, CS
2
going low and WE going high,
t
WP
is measured from the begining of write to the end of write.
2. t
CW
is measured from the CS
1
going low or CS
2
going high to the end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end of write to the address change.
CS
2
WE
Data in
Data Valid
Data out
High-Z
High-Z
t
CW(2)
t
WR(4)
t
WP(1)
t
DW
t
DH
t
AS(3)
t
WC
Revision 1.1
K6F2008V2E Family
9
May 2003
CMOS SRAM
PACKAGE DIMENSIONS
Units: millimeters(inches)
#32
1.00
0.10
0.039
0.004
M
A
X
8
.
4
0
0
.
3
3
1
0
.
0
0
4
0
.
1
0
#1
13.40
0.20
0.528
0.008
#17
#16
+0.10
0.20
-0.05
+0.004
0.008
-0.002
0.50
0.0197
0.25
( )
0.010
MIN
0.05
0.002
MAX
1.20
0.047
8
.
0
0
0
.
3
1
5
M
A
X
0.50
( )
0.020
11.80
0.10
0.465
0.004
0.45~0.75
0.018~0.030
+0.10
0.15
-0.05
+0.004
0.006
-0.002
0~8
TYP
0.25
0.010
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)
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