Revision 2.0
CMOS SRAM
K6F2008V2M, K6F2008S2M, K6F2008R2M Family
1
March 1998
Document Title
256Kx8 bit Super Low Power and Low Voltage Full CMOS Static RAM
Revision History
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
Revision No.
0.0
0.1
1.0
2.0
Remark
Advance
Preliminary
Final
Final
History
Initial draft
Revise
- Remove sTSOP1 from product
- Rename high power product to low power.
I
SB1
=10.0mA(Max)
- Add super low power version with special handling
I
SB1
=1.0mA(Max)
- Remove 70ns and add 85ns part on KM68F2000 Family
Finalize
Revise
- Change datasheet format
- Remove reverse type package from product
- Remove reseved speed bin(100ns)
Draft Date
October 2, 1996
December 1, 1996
April 11, 1997
March 5, 1998
Revision 2.0
CMOS SRAM
K6F2008V2M, K6F2008S2M, K6F2008R2M Family
2
March 1998
256Kx8 bit Super Low Power and Low Voltage Full CMOS Static RAM
GENERAL DESCRIPTION
The K6F2008V2M, K6F2008S2M and K6F2008R2M families
are fabricated by SAMSUNG
s advanced Full CMOS process
technology. The families support various operating temperature
ranges and have various package types for user flexibility of
system design. The families also supports low data retention
voltage for battery back-up operation with low data retention
current.
FEATURES
Process Technology: Full CMOS
Organization: 256Kx8
Power Supply Voltage
K6F2008V2M Family: 3.0 ~ 3.6V
K6F2008S2M Family: 2.3 ~ 3.3V
K6F2008R2M Family: 1.8 ~ 2.7V
Low Data Retention Voltage: 1.5V(Min)
Three state output and TTL Compatible
Package Type: 32-TSOP1-0820F
PIN DESCRIPTION
Name
Function
Name
Function
CS
1
,CS
2
Chip Select Input
I/O
1
~I/O
8
Data Inputs/Outputs
OE
Output Enable
Vcc
Power
WE
Write Enable Input
Vss
Ground
A
0
~A
17
Address Inputs
N.C.
No Connection
FUNCTIONAL BLOCK DIAGRAM
PRODUCT FAMILY
1. The parameter is measured with 30pF test load.
2. 2
A for super low power version with special handling.
Product Family
Operating Temperature
Vcc Range
Speed(ns)
Power Dissipation
PKG Type
Standby
(I
SB1
, Max)
Operating
(I
CC2
, Max)
K6F2008V2M-C
Commercial(0~70
C)
3.0~3.6V
70
1)
/85@V
CC
=3.3
0.3V
10
A
2)
60mA
32-TSOP1-F
K6F2008S2M-C
2.3~3.3V
85@V
CC
=3.0
0.3V
55mA
120
1)
/150@V
CC
=2.5
0.2V
30mA
K6F2008R2M-C
1.8~2.7V
300
1)
@V
CC
=2.0
0.2V
15mA
K6F2008V2M-I
Industrial(-40~85
C)
3.0~3.6V
70
1)
/85@V
CC
=3.3
0.3V
60mA
K6F2008S2M-I
2.3~3.3V
85@V
CC
=3.0
0.3V
55mA
120
1)
/150@V
CC
=2.5
0.2V
30mA
K6F2008R2M-I
1.8~2.7V
300
1)
@V
CC
=2.0
0.2V
15mA
A11
A9
A8
A13
WE
CS2
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
Type I - Forward
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-TSOP
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
A17
Precharge circuit.
Memory array
1024 rows
2568 columns
I/O Circuit
Column select
Clk gen.
Row
select
A9 A11 A10 A15 A13
A16
A8
A14
A12
A7
A6
A5
A4
A3
I/O
1
Data
cont
Data
cont
I/O
8
A2
A0
A1
CS1
CS2
WE
OE
Control
logic
Revision 2.0
CMOS SRAM
K6F2008V2M, K6F2008S2M, K6F2008R2M Family
3
March 1998
PRODUCT LIST
Commercial Temperature Products(0~70
C)
Industrial Temperature Products(-40~85
C)
Part Name
Function
Part Name
Function
K6F2008V2M-TC70
K6F2008V2M-TC85
K6F2008S2M-TC12
K6F2008S2M-TC15
K6F2008R2M-TC30
32-TSOP F, 70ns, 3.3V, LL
32-TSOP F, 85ns, 3.3V, LL
32-TSOP F, 120/85ns, 2.5/3.0V, LL
32-TSOP F, 150/85ns, 2.5/3.0V, LL
32-TSOP F, 300ns, 2.0/2.5V, LL
K6F2008V2M-TI70
K6F2008V2M-TI85
K6F2008S2M-TI12
K6F2008S2M-TI15
K6F2008R2M-TI30
32-TSOP F, 70ns, 3.3V, LL
32-TSOP F, 85ns, 3.3V, LL
32-TSOP F, 120/85ns, 2.5/3.0V, LL
32-TSOP F, 150/85ns, 2.5/3.0V, LL
32-TSOP F, 300ns, 2.0/2.5V, LL
FUNCTIONAL DESCRIPTION
1. X means don
t care (Must be high or low states)
CS
1
CS
2
OE
WE
I/O
Mode
Power
H
X
1)
X
1)
X
1)
High-Z
Deselected
Standby
X
1)
L
X
1)
X
1)
High-Z
Deselected
Standby
L
H
H
H
High-Z
Output Disable
Active
L
H
L
H
Dout
Read
Active
L
H
X
1)
L
Din
Write
Active
ABSOLUTE MAXIMUM RATINGS
1)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. V
IN
/V
OUT
=-0.2 to 3.9V for K6F2008V2M Family.
3. Maximum V
CC
=-0.2 to 4.6V for K6F2008V2M Family.
Item
Symbol
Ratings
Unit
Remark
Voltage on any pin relative to Vss
V
IN
,V
OU
-0.2 to 3.6V
2)
V
-
Voltage on Vcc supply relative to Vss
V
CC
-0.2 to 4.0V
3)
V
-
Power Dissipation
P
D
1.0
W
-
Storage temperature
T
STG
-55 to 150
C
-
Operating Temperature
T
A
0 to 70
C
K6F2008V2M-C, K6F2008S2M-C, K6F2008R2M-C
-40 to 85
C
K6F2008V2M-I, K6F2008S2M-I, K6F2008R2M-I
Soldering temperature and time
T
SOLDER
260
C, 5sec (Lead Only)
-
-
Revision 2.0
CMOS SRAM
K6F2008V2M, K6F2008S2M, K6F2008R2M Family
4
March 1998
RECOMMENDED DC OPERATING CONDITIONS
1)
Note
1. Commercial Product : T
A
=0 to 70
C, unless otherwise specified
Industrial Product : T
A
=-40 to 85
C, unless otherwise specified
2. Overshoot : Vcc + 1.0V in case of pulse width
20ns
3. Undershoot : -1.0V in case of pulse width
20ns
4. Overshoot and undershoot are sampled, not 100% tested.
Item
Symbol
Product
Min
Typ
2)
Max
Unit
Supply voltage
Vcc
K6F2008V2M Family
K6F2008S2M Family
K6F2008R2M Family
3.0
2.3
1.8
3.3
2.5/3.0
2.0/2.5
3.6
3.3
2.7
V
Ground
Vss
All Family
0
0
0
V
Input high voltage
V
IH
K6F2008V2M Family
Vcc=3.3
0.3V
2.2
-
Vcc+0.2
2)
V
K6F2008S2M Family
Vcc=3.0
0.3V
2.2
Vcc=2.5
0.2V
2.0
K6F2008R2M Family
Vcc=2.5
0.2V
2.0
Vcc=2.0
0.2V
1.6
Input low voltage
V
IL
All Family
-0.2
3)
-
0.4
V
CAPACITANCE
1)
(f=1MHz, T
A
=25
C)
1. Capacitance is sampled, not 100% tested
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
C
IN
V
IN
=0V
-
8
pF
Input/Output capacitance
C
IO
V
IO
=0V
-
10
pF
DC AND OPERATING CHARACTERISTICS
1.The value is measured at Vcc=3.0
0.3V
- ICC2=60mA with 70ns at Vcc=3.3
0.3V, but this value is not 100% tested but obtained statistically.
2. Super low power product = 2
A with special handling.
Item
Symbol
Test Conditions
Min
Typ
Max
Unit
Input leakage current
I
LI
V
IN
=Vss to Vcc
-1
-
1
mA
Output leakage current
I
LO
CS
1
=V
IH
or CS
2
=V
IL
or
OE=V
IH
or
WE=V
IL,
V
IO
=Vss to Vcc
-1
-
1
mA
Operating power supply current
I
CC
I
IO
=0mA, CS
1
=V
IL
, CS
2
=V
IH
, V
IN
=V
IL
or V
IH
, Read
-
-
10
mA
Average operating current
I
CC1
Cycle time=1
s
, 100% duty, I
IO
=0mA, CS
1
0.2V,
CS
2
V
CC
-0.2V, V
IN
0.2V or V
IN
V
CC
-0.2V
Read
-
-
10
mA
Write
-
-
15
I
CC2
Cycle time=Min, 100% duty, I
IO
=0mA,
CS1=V
IL
, CS2=V
IH,
V
IN
=V
IL
or V
IH
Vcc=3.3V@70ns
-
-
55
1)
mA
Vcc=2.7V@120ns
-
-
30
Vcc=2.2V@300ns
-
-
15
Output low voltage
V
OL
I
OL
2.1mA at Vcc=3.0/3.3V
-
-
0.4
V
0.5mA at Vcc=2.5V
-
-
0.4
0.33mA at Vcc=2.0V
-
-
0.4
Output high voltage
V
OH
I
OH
-1.0mA at Vcc=3.0/3.3V
2.4
-
-
V
-0.5mA at Vcc=2.5V
2.0
-
-
-0.44mA at Vcc=2.0V
1.6
-
-
Standby Current(TTL)
I
SB
CS
1
=V
IH
or CS
2
=V
IL,
Other inputs=V
IL
or V
IH
-
-
0.3
mA
Standby Current(CMOS)
I
SB1
CS
1
Vcc-0.2V, CS2
Vcc-0.2V or CS
2
0.2V, Other inputs=0~Vcc
-
-
10
2)
A
Revision 2.0
CMOS SRAM
K6F2008V2M, K6F2008S2M, K6F2008R2M Family
5
March 1998
C
L
1)
1. Including scope and jig capacitance
R
2
3)
R
1
2)
V
TM
3)
2. R
1
=3070W
,
R
2
=3150W
3. V
TM
=2.8V for V
CC
=3.0/3.3V
=2.3V for V
CC
=2.5V
=1.8V for V
CC
=2.0V
AC CHARACTERISTICS
(Commercial product:T
A
=0 to 70
C, Industrial product: T
A
=-40 to 85
C
K6F2008V2M Family: Vcc=3.0~3.6V, K6F2008S2M Family: Vcc=2.3~3.3V,
K6F2008R2M Family: Vcc=1.8~2.7V)
Parameter List
Symbol
Speed Bins
Units
70ns
85ns
120ns
150ns
300ns
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Read
Read cycle time
t
RC
70
-
85
-
120
-
150
-
300
-
ns
Address access time
t
AA
-
70
-
85
-
120
-
150
-
300
ns
Chip select to output
t
CO1
, t
CO2
-
70
-
85
-
120
-
150
-
300
ns
Output enable to valid output
t
OE
-
35
-
45
-
60
-
75
-
150
ns
Chip select to low-Z output
t
LZ1
, t
LZ2
10
-
10
-
10
-
20
-
50
-
ns
Output enable to low-Z output
t
OLZ
5
-
5
-
5
-
10
-
30
-
ns
Chip disable to high-Z output
t
HZ1
, t
HZ2
0
25
0
25
0
35
0
40
0
60
ns
Output disable to high-Z output
t
OHZ
0
25
0
25
0
35
0
40
0
60
ns
Output hold from address change
t
OH
10
-
15
-
15
-
15
-
30
-
ns
Write
Write cycle time
t
WC
70
-
85
-
120
-
150
-
300
-
ns
Chip select to end of write
t
CW
65
-
70
-
100
-
120
-
300
-
ns
Address set-up time
t
AS
0
-
0
-
0
-
0
-
0
-
ns
Address valid to end of write
t
AW
65
-
70
-
100
-
120
-
300
-
ns
Write pulse width
t
WP
55
-
60
-
80
-
100
-
200
-
ns
Write recovery time
t
WR
0
-
0
-
0
-
0
-
0
-
ns
Write to output high-Z
t
WHZ
0
25
0
25
0
35
0
40
0
60
ns
Data to write time overlap
t
DW
30
-
35
-
50
-
60
-
120
-
ns
Data hold from write time
t
DH
0
-
0
-
0
-
0
-
0
-
ns
End write to output low-Z
t
OW
5
-
5
-
5
-
5
-
20
-
ns
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
Input pulse level: 0.4 to 2.2V for Vcc=3.3V, 3.0V, 2.5V
0.4 to 1.8V for Vcc=2.0V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V for Vcc=3.3V, 3.0V
1.1V for Vcc=2.5V
0.9V for Vcc=2.0V
Output load (See right):C
L
=100pF+1TTL
C
L
=30pF+1TTL
DATA RETENTION CHARACTERISTICS
1.
CS
1
Vcc-0.2V, CS
2
Vcc-0.2V(CS
1
controlled) or CS
2
0.2V(CS
2
controlled)
2. Super low power product = 2
A with special handling.
Item
Symbol
Test Condition
Min
Typ
Max
Unit
Vcc for data retention
V
DR
CS
1
Vcc-0.2V
1)
1.5
-
3.6
V
Data retention current
I
DR
Vcc=3.0V, CS
1
Vcc-0.2V
1)
-
-
10
2)
A
Data retention set-up time
t
SDR
See data retention waveform
0
-
-
ns
Recovery time
t
RDR
t
RC
-
-
Revision 2.0
CMOS SRAM
K6F2008V2M, K6F2008S2M, K6F2008R2M Family
6
March 1998
Address
Data Out
Previous Data Valid
Data Valid
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS1=OE=V
IL
, WE=V
IH
)
t
AA
t
RC
t
OH
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
Data Valid
High-Z
CS
1
Address
OE
Data out
NOTES (READ CYCLE)
1.
t
HZ
and
t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition,
t
HZ
(Max.) is less than
t
LZ
(Min.) both for a given device and from device to device
interconnection.
CS
2
t
OH
t
AA
t
OLZ
t
LZ
t
OHZ
t
HZ(1,2)
t
RC
t
CO2
t
OE
t
CO1
Revision 2.0
CMOS SRAM
K6F2008V2M, K6F2008S2M, K6F2008R2M Family
7
March 1998
TIMING WAVEFORM OF WRITE CYCLE(1)
(WE Controlled)
Address
CS
1
t
CW(2)
t
WR(4)
TIMING WAVEFORM OF WRITE CYCLE(2)
(CS
1
Controlled)
Address
CS
1
t
WC
t
WR(4)
t
AS(3)
CS
2
t
CW(2)
t
WP(1)
t
DW
t
DH
t
OW
t
WHZ
Data Undefined
Data Valid
WE
Data in
Data out
t
DW
t
DH
Data Valid
WE
Data in
Data out
High-Z
High-Z
CS
2
t
WC
t
AW
t
AS(3)
t
CW(2)
t
WP(1)
t
AW
Revision 2.0
CMOS SRAM
K6F2008V2M, K6F2008S2M, K6F2008R2M Family
8
March 1998
DATA RETENTION WAVE FORM
CS
1
controlled
V
CC
3.0/2.7/2.3/1.8V
2.2V
V
DR
CS
1
GND
Data Retention Mode
CS
V
CC
- 0.2V
t
SDR
t
RDR
TIMING WAVEFORM OF WRITE CYCLE(3)
(CS
1
Controlled)
Address
CS
1
t
AW
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS
1
, a high CS
2
and a low WE. A write begins at the latest transition among CS
1
goes low,
CS
2
going high and WE going low : A write end at the earliest transition among CS
1
going high, CS
2
going low and WE going high,
t
WP
is measured from the begining of write to the end of write.
2. t
CW
is measured from the CS
1
going low or CS
2
going high to the end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end of write to the address change. t
WR(1)
applied in case a write ends as CS
1
or WE going high t
WR(2)
applied in case a write ends as CS
2
going to low.
CS
2
t
WP(2)
WE
Data in
Data Valid
Data out
High-Z
High-Z
t
CW(2)
t
WR(4)
t
WP(1)
t
DW
t
DH
t
AS(3)
t
WC
CS
2
controlled
V
CC
3.0/2.7/2.3/1.8V
0.4V
V
DR
CS
2
GND
Data Retention Mode
t
SDR
t
RDR
CS
2
0.2V
Revision 2.0
CMOS SRAM
K6F2008V2M, K6F2008S2M, K6F2008R2M Family
9
March 1998
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)
#32
1.00
0.10
0.039
0.004
MAX
8.40
0.331
0
.
0
0
4
M
A
X
1
.
1
0
M
A
X
#1
0.50
( )
0.020
18.40
0.10
0.724
0.004
0.45 ~0.75
0.018 ~0.030
20.00
0.20
0.787
0.008
#17
+0.10
0.15
-0.05
+0.004
0.006
-0.002
0~8
+0.10
0.20
-0.05
+0.004
0.008
-0.002
0.50
0.0197
0.25
( )
0.010
MIN
0.05
0.002
MAX
1.20
0.047
8
.
0
0
0
.
3
1
5
TYP
0.25
0.010
#16
PACKAGE DIMENSIONS
Units: millimeters(inches)
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