CMOS SRAM

K6F2016V3M, K6F2016S3M, K6F2016R3M Family

Revision 2.0

May 1999

ocument Title

128K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM

Revision History

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and

products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.

Revision No.

0.0

0.1

1.0

2.0

Remark

Advance

Preliminary

Final

History

Design target

Initial draft
- Add KM616FV2000 Family
- Erase KM616FU1000 Family and KM616FS1000 Family supprot
2.3~3.3V operating Vcc.
- Concept change high power version to low low power version
I

SB1

=10

A(Max)

- Add super low power version with special handling
I

SB1

=2.0

A(Max)

- Reduce Icc & Icc1
Write : 25mA to 20mA at Vcc=3.6V(Max)

Finalize
- Change datasheet format
- Erase reverse type package

Revise
- Add 48-

BGA type package

Draft Date

October 2, 1996

December 1, 1996

March 4, 1998

May 3, 1999

CMOS SRAM

K6F2016V3M, K6F2016S3M, K6F2016R3M Family

Revision 2.0

May 1999

128Kx16 bit Super Low Power and Low Voltage Full CMOS Static RAM

GENERAL DESCRIPTION

The K6F2016V3M, K6F2016S3M and K6F2016R3M fami-
lies are fabricated by SAMSUNG

s advanced Full CMOS

process technology. The families support various operating

temperature ranges for user flexibility of system design. The

families also support low data retention voltage for battery

back-up operation with low data retention current.

FEATURES

Process Technology: Full CMOS

Organization: 128Kx16

Power Supply Voltage

K6F2016V3M Family: 3.0V ~ 3.6V
K6F2016S3M Family: 2.3V ~ 3.3V
K6F2016R3M Family: 1.8V ~ 2.7V

Low Data Retention Voltage: 1.5V(Min)

Three state output status and TTL Compatible

Package Type: 44-TSOP2-400F, 48-

BGA-6.20x13.75

PIN DESCRIPTION

Name

Function

Name

Function

Chip Select Input

Lower Byte(I/O

)

Output Enable Input

Upper Byte(I/O

)

Write Enable Input

Vcc

Power

Address Inputs

Vss

Ground

I/O

~I/O

Data Inputs/Outputs

N.C.

No Connection

PRODUCT FAMILY

1. The parameter is measured with 30pF test load.
2. Super low power product=2

A with special handling.

3. Availiable parts are 100ns@V

=3.0

0.3V, 150ns@V

=2.5

0.2V and 300ns@V

=2.0

0.2V with 30pF test load.

Product Family

Operating Temperature

Vcc Range

Speed(ns)

Power Dissipation

PKG Type

Standby

SB1

, Max)

Operating

CC2

, Max)

K6F2016V3M-C

Commercial(0~70

3.0~3.6V

/85@V

=3.3

0.3V

80mA

44-TSOP2-
Forward

K6F2016S3M-C

2.3~3.3V

85@V

=3.0

0.3V

80mA

120

/150@V

=2.5

0.2V

50mA

K6F2016R3M-C

1.8~2.7V

300

=2.0

0.2V

20mA

K6F2016V3M-I

Industrial(-40~85

3.0~3.6V

/85@V

=3.3

0.3V

80mA

K6F2016S3M-I

2.3~3.3V

85@V

=3.0

0.3V

80mA

44-TSOP2

Forward

48-

BGA

120

/150@V

=2.5

0.2V

50mA

K6F2016R3M-I

1.8~2.7V

300

=2.0

0.2V

20mA

FUNCTIONAL BLOCK DIAGRAM

I/OI

I/O2

I/O3

I/O4

Vcc

Vss

I/O5

I/O6

I/O7

I/O8

A16

A15

A14

A13

A12

I/O16

I/O15

I/O14

I/O13

Vss

Vcc

I/O12

I/O11

I/O10

I/O9

N.C

A10

A11

N.C

44-TSOP2

Forward

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

Precharge circuit.

Memory array
1024 rows
128

16 columns

I/O Circuit

Column select

Clk gen.

Row
select

A7 A11 A10

A16

A14

A15

I/O

~I/O

A12

Data
cont

I/O

~I/O

Vcc
Vss

A13

Control
logic

N.C

I/O9

I/O1

I/O10

I/O11

I/O2

I/O3

Vss

I/O12

N.C

I/O4

Vcc

I/O13

N.C

A16

I/O5

Vss

I/O15

I/O14

A14

A15

I/O6

I/O7

I/O16

N.C

A12

A13

I/O8

N.C

A10

A11

N.C

48-

BGA Top View

CMOS SRAM

K6F2016V3M, K6F2016S3M, K6F2016R3M Family

Revision 2.0

May 1999

PRODUCT LIST

Commercial Temperature Products(0~70

Industrial Temperature Products(-40~85

Part Name

Function

Part Name

Function

K6F2016V3M-TC70
K6F2016V3M-TC85

K6F2016S3M-TC12
K6F2016S3M-TC15

K6F2016R3M-TC30

44-TSOP2 F, 70ns, 3.3V, LL
44-TSOP2 F, 85ns, 3.3V, LL

44-TSOP2 F, 120/85ns, 2.5/3.0V, LL
44-TSOP2 F, 150/85ns, 2.5/3.0V, LL

44-TSOP2 F, 300ns, 2.0/2.5V, LL

K6F2016V3M-TI70
K6F2016V3M-TI85

K6F2016S3M-TI12
K6F2016S3M-TI15
K6F2016S3M-ZI15

K6F2016R3M-TI30
K6F2016R3M-ZI30

44-TSOP2 F, 70ns, 3.3V, LL
44-TSOP2 F, 85ns, 3.3V, LL

44-TSOP2 F, 120/85ns, 2.5/3.0V, LL
44-TSOP2 F, 150/85ns, 2.5/3.0V, LL
48-

BGA, 2.5V/3.0V, 150/100ns

44-TSOP2 F, 300ns, 2.0/2.5V, LL
48-

BGA, 1.8V/2.5V, 300ns

ABSOLUTE MAXIMUM RATINGS

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be

restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. V

OUT

=-0.2 to 3.9V for

K6F2016V3M

Family.

3. V

=-0.2 to 4.6V for

K6F2016V3M

Family

Item

Symbol

Ratings

Unit

Remark

Voltage on any pin relative to Vss

-0.2 to 3.6V

Voltage on Vcc supply relative to Vss

-0.2 to 4.0V

Power Dissipation

1.0

Storage temperature

STG

-55 to 150

Operating Temperature

0 to 70

K6F2016V3M-C, K6F2016S3M-C, K6F2016R3M-C

-40 to 85

K6F2016V3M-I, K6F2016S3M-I, K6F2016R3M-I

Soldering temperature and time

SOLDER

260

C, 5sec (Lead Only)

FUNCTIONAL DESCRIPTION

1. X means don

t care. (Must be in low or high state)

I/O

1~8

I/O

9~16

Mode

Power

High-Z

Deselected

Standby

High-Z

Output Disabled

Active

High-Z

Output Disabled

Active

Dout

High-Z

Lower Byte Read

Active

High-Z

Dout

Upper Byte Read

Active

Dout

Word Read

Active

Din

High-Z

Lower Byte Write

Active

High-Z

Din

Upper Byte Write

Active

Din

Word Write

Active

CMOS SRAM

K6F2016V3M, K6F2016S3M, K6F2016R3M Family

Revision 2.0

May 1999

RECOMMENDED DC OPERATING CONDITIONS

Note
1 Commercial Product : T

=0 to 70

C, unless otherwise specified

Industrial Product : T

=-40 to 85

C, unless otherwise specified

2. Overshoot : Vcc + 1.0V in case of pulse width

20ns

3. Undershoot : -1.0V in case of pulse width

20ns

4. Overshoot and undershoot are sampled, not 100% tested.

Item

Symbol

Product

Min

Typ

Max

Unit

Supply voltage

Vcc

K6F2016V3M Family

3.0

3.3

3.6

K6F2016S3M Family

2.3

2.5/3.0

3.3

K6F2016R3M Family

1.8

2.0/2.5

2.7

Ground

Vss

All Family

Input high voltage

K6F2016V3M Family

Vcc=3.3

0.3V

2.2

Vcc+0.2

K6F2016S3M Family

Vcc=3.0

0.3V

2.2

Vcc=2.5

0.2V

2.0

K6F2016R3M Family

Vcc=2.5

0.2V

2.0

Vcc=2.0

0.2V

1.6

Input low voltage

All Family

-0.2

0.4

CAPACITANCE

(f=1MHz, T

=25

1. Capacitance is sampled, not 100% tested

Item

Symbol

Test Condition

Min

Max

Unit

Input capacitance

=0V

Input/Output capacitance

=0V

DC AND OPERATING CHARACTERISTICS

1. Super low power product=2

A with special handling.

Item

Symbol

Test Conditions

Min

Typ

Max

Unit

Input leakage current

=Vss to Vcc

-1

Output leakage current

CS=V

or OE=V

or WE=V

, V

=Vss to Vcc

-1

Operating power supply current

=0mA, CS=V

, V

or V

, Read

Average operating current

CC1

Cycle time=1

s, 100% duty, I

=0mA,

0.2V, V

0.2V or V

-0.2V

Read

Write

CC2

Cycle time=Min, 100% duty,
I

=0mA, CS=V

, V

or V

Vcc=3.3V@70ns

Vcc=2.7V@120ns

Vcc=2.2V@300ns

Output low voltage

2.1mA at Vcc=3.0/3.3V

0.4

0.5mA at Vcc=2.5V

0.4

0.33mA at Vcc=2.0V

0.4

Output high voltage

-1.0mA at Vcc=3.0/3.3V

2.4

-0.5mA at Vcc=2.5V

2.0

-0.44mA at Vcc=2.0V

1.6

Standby Current(TTL)

CS=V

, Other inputs=V

or V

0.3

Standby Current(CMOS)

SB1

Vcc-0.2V, Other inputs=0~Vcc

CMOS SRAM

K6F2016V3M, K6F2016S3M, K6F2016R3M Family

Revision 2.0

May 1999

AC OPERATING CONDITIONS

TEST CONDITIONS

(Test Load and Test Input/Output Reference)

Input pulse level : 0.4 to 2.2V for Vcc=3.3V, 3.0V, 2.5V

0.4 to 1.8V for Vcc=2.0V

Input rising and falling time : 5ns
Input and output reference voltage : 1.5V for Vcc=3.3V, 3.0V

1.1V for Vcc=2.5V
0.9V for Vcc=2.0V

Output load (See right) : C

=100pF+1TTL

=30pF+1TTL

1. Including scope and jig capacitance

2. R

=3070

=3150

3. V

=2.8V for V

=3.0/3.3V

=2.3V for V

=2.5V

=1.8V for V

=2.0V

AC CHARACTERISTICS

(Commercial product :T

=0 to 70

C, Industrial product : T

=-40 to 85

K6F2016V3M Family : Vcc=3.0~3.6V, K6F2016S3M Family : Vcc=2.3~3.3V,
K6F2016R3M Family : Vcc=1.8~2.7V)

Parameter List

Symbol

Speed Bins

Units

70ns

85ns

100ns

120ns

150ns

300ns

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Read

Read cycle time

100

120

150

300

Address access time

100

120

150

300

Chip select to output

100

120

150

300

Output enable to valid output

150

UB, LB Access Time

150

Chip select to low-Z output

Output enable to low-Z output

OLZ

, t

BLZ

Chip disable to high-Z output

Output disable to high-Z output

OHZ

, t

BHZ

Output hold from address change

Write

Write cycle time

100

120

150

300

Chip select to end of write

100

120

300

Address set-up time

Address valid to end of write

100

120

300

Write pulse width

100

200

UB, LB Valid to End of Write

100

120

300

Write recovery time

Write to output high-Z

WHZ

Data to write time overlap

120

Data hold from write time

End write to output low-Z

DATA RETENTION CHARACTERISTICS

1. Super low power product=2

A with special handling.

Item

Symbol

Test Condition

Min

Typ

Max

Unit

Vcc for data retention

Vcc-0.2V

1.5

3.6

Data retention current

Vcc=3.0V, CS

Vcc-0.2V

Data retention set-up time

SDR

See data retention waveform

Recovery time

RDR

CMOS SRAM

K6F2016V3M, K6F2016S3M, K6F2016R3M Family

Revision 2.0

May 1999

Address

Data Out

Previous Data Valid

Data Valid

TIMMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1)

(Address Controlled

CS=OE=V

, WE=V

, UB or/and LB=V

)

TIMING WAVEFORM OF READ CYCLE(2)

(WE=V

)

Data Valid

High-Z

Address

UB, LB

Data out

OLZ

BLZ

OHZ

BHZ

NOTES (READ CYCLE)

and

OHZ

are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition,

(Max.) is less than

(Min.) both for a given device and from device to device

interconnection.

CMOS SRAM

K6F2016V3M, K6F2016S3M, K6F2016R3M Family

Revision 2.0

May 1999

Address

Data Valid

UB, LB

Data in

Data out

High-Z

TIMING WAVEFORM OF WRITE CYCLE(3)

(UB, LB Controlled)

NOTES

(WRITE CYCLE)

1. A wri

e occurs during the overlap(t

) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB

or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-
tion when CS goes high and WE goes high. The

is measured from the beginning of write to the end of write.

is measured from the CS going low to end of write.

is measured from the address valid to the beginning of write.

is measured from the end or write to the address change.

applied in case a write ends as CS or WE going high.

CW(2)

WP(1)

WR(4)

DATA RETENTION WAVE FORM

CS controlled

3.0/2.7/2.3/1.8V

2.2V

CS
GND

Data Retention Mode

- 0.2V

SDR

RDR

AS(3)

CMOS SRAM

K6F2016V3M, K6F2016S3M, K6F2016R3M Family

Revision 2.0

May 1999

Units: millimeters

PACKAGE DIMENSIONS

/
2

B/2

Ball #A1

B/2

Elastomer

SRAM Die

Ball #A1

/
2

Bottom View

Top View

Detail A

Side View

.
5

/
T

.
3

/
T

.
2

/
T

Elastomer

0.42/Typ.

Die

Detail A

Notes.

1. Bump counts: 48(8row x 6column)

2. Bump pitch: (x,y)=(0.75 x 0.75)(typ.)

3. All tolerence are +/-0.050 unless otherwise

specified.

4. Typ: Typical

5. Y is coplanarity: 0.08(Max)

Min

Typ

Max

0.75

5.90

6.20

6.10

3.75

7.90

13.75

8010

5.25

0.30

0.35

0.40

0.80

0.81

0.55

0.25

0.08

48 BALL MICRO BALL GRID ARRAY- 0.75mm ball pitch

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