Revision 2.0
April 2000
K6F4008U1C Family
- 1 -
CMOS SRAM
Document Title
512K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
Revision History
Revision No.
0.0
1.0
2.0
Remark
Preliminary
Final
Final
History
Initial draft
Finalize
- Adopt new code.
- Improve V
IN
, V
OUT
max. on
ABSOLUTE MAXIMUM RATINGS
from
3.6V to V
CC
+0.5V.
Change for AC parameter
- Change for tWHZ: 25 to 20ns for 70ns product
- Change for tDW: 20 to 25ns for 55ns product
25 to 30ns for 70ns product
Draft Date
August 30, 1999
March 22, 2000
April 24, 2000
Revision 2.0
April 2000
K6F4008U1C Family
- 2 -
CMOS SRAM
PRODUCT FAMILY
1. The parameter is measured with 30pF test load.
Product Family
Operating Temperature
Vcc Range
Speed
Power Dissipation
PKG Type
Standby
(I
SB1
, Typ.)
Operating
(I
CC1
, Max)
K6F4008U1C-F
Industrial(-40~85
C)
2.7~3.3V
55
1)
/70ns
0.5
A
3mA
32-TSOP1-0813.4F
512K x 8 bit Super Low Power and Low Voltage Full CMOS Static RAM
GENERAL DESCRIPTION
The K6F4008U1C families are fabricated by SAMSUNG
s
advanced full CMOS process technology. The families support
small package type for user flexibility of system design. The
families also supports low data retention voltage for battery
back-up operation with low data retention current.
FEATURES
Process Technology: Full CMOS
Organization: 512K x8 bit
Power Supply Voltage: 2.7~3.3V
Low Data Retention Voltage: 1.5V(Min)
Three state output status and TTL Compatible
Package Type: 32-TSOP1-0813.4F
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice
.
FUNCTIONAL BLOCK DIAGRAM
Precharge circuit.
Memory array
2048 rows
256
8 columns
I/O Circuit
Column select
Clk gen.
Row
select
CS
WE
I/O
1
Data
cont
Data
cont
OE
I/O
8
Control
logic
Name
Function
Name
Function
CS
Chip Select Input
Vcc
Power
WE
Write Enable Input
Vss
Ground
OE
Output Enable Input I/O
1
~I/O
8
Data Inputs/Outputs
A
0
~A
18
Address Inputs
A11
A9
A8
A13
WE
A18
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
OE
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
(Forward)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-
S
TSOP1
PIN DESCRIPTION
Row
Address
Column Address
Revision 2.0
April 2000
K6F4008U1C Family
- 3 -
CMOS SRAM
ABSOLUTE MAXIMUM RATINGS
1)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Item
Symbol
Ratings
Unit
Voltage on any pin relative to Vss
V
IN
, V
OUT
-0.2 to V
CC
+0.5V
V
Voltage on Vcc supply relative to Vss
V
CC
-0.2 to 4.0V
V
Power Dissipation
P
D
1.0
W
Storage temperature
T
STG
-65 to 150
C
Operating Temperature
T
A
-40 to 85
C
PRODUCT LIST
Industrial Temperature Products(-40~85
C)
Part Name
Function
K6F4008U1C-YF55
K6F4008U1C-YF70
32-sTSOP1-F, 55ns, 3.0V
32-sTSOP1-F, 70ns, 3.0V
FUNCTIONAL DESCRIPTION
1. X means don
t care.(Must be in low or high state)
CS
OE
WE
I/O
Mode
Power
H
X
1)
X
1)
High-Z
Deselected
Standby
L
H
H
High-Z
Output Disabled
Active
L
L
H
Dout
Read
Active
L
X
1)
L
Din
Write
Active
Revision 2.0
April 2000
K6F4008U1C Family
- 4 -
CMOS SRAM
DC AND OPERATING CHARACTERISTICS
1. Super low power product=5
A with special handling.
Item
Symbol
Test Conditions
Min
Typ Max Unit
Input leakage current
I
LI
V
IN
=Vss to Vcc
-1
-
1
A
Output leakage current
I
LO
CS=V
IH,
OE=V
IH
or WE=V
IL
, V
IO
=Vss to Vcc
-1
-
1
A
Operating power supply current
I
CC
I
IO
=0mA, CS=V
IL,
WE=V
IH,
V
IN
=V
IL
or V
IH
-
-
2
mA
Average operating current
I
CC1
Cycle time=1
s, 100%duty, I
IO
=0mA, CS
0.2V, V
IN
0.2V or V
IN
V
CC
-0.2V
-
-
3
mA
I
CC2
Cycle time=Min, I
IO
=0mA, 100% duty, CS=V
IL
, VIN=V
IL
or V
IH
-
-
30
mA
Output low voltage
V
OL
I
OL
= 2.1mA
-
-
0.4
V
Output high voltage
V
OH
I
OH
= -1.0mA
2.4
-
-
V
Standby Current(TTL)
I
SB
CS=V
IH
, Other inputs=V
IL
or V
IH
-
-
0.3
mA
Standby Current (CMOS)
I
SB1
CS
Vcc-0.2V, Other input =0~Vcc
-
0.5
12
1)
A
RECOMMENDED DC OPERATING CONDITIONS
1)
Note:
1. T
A
=-40 to 85
C, otherwise specified.
2. Overshoot: Vcc+2.0V in case of pulse width
20ns.
3. Undershoot: -2.0V in case of pulse width
20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
Item
Symbol
Min
Typ
Max
Unit
Supply voltage
Vcc
2.7
3.0
3.3
V
Ground
Vss
0
0
0
V
Input high voltage
V
IH
2.2
-
Vcc+0.3
2)
V
Input low voltage
V
IL
-0.2
3)
-
0.6
V
CAPACITANCE
1)
(f=1MHz, T
A
=25
C)
1. Capacitance is sampled, not 100% tested.
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
C
IN
V
IN
=0V
-
8
pF
Input/Output capacitance
C
IO
V
IO
=0V
-
10
pF
Revision 2.0
April 2000
K6F4008U1C Family
- 5 -
CMOS SRAM
DATA RETENTION CHARACTERISTICS
1. Super low power product=2
A with special handling.
Item
Symbol
Test Condition
Min
Typ
Max
Unit
Vcc for data retention
VDR
CS
Vcc-0.2V
1.5
-
3.3
V
Data retention current
IDR
Vcc=1.5V, CS
Vcc-0.2V
-
0.5
3
1)
A
Data retention set-up time
tSDR
See data retention waveform
0
-
-
ns
Recovery time
tRDR
tRC
-
-
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.1V
Output load (See right): C
L
=100pF+1TTL
C
L
=30pF+1TTL
C
L
1)
1. Including scope and jig capacitance
R
2
2)
R
1
2)
V
TM
3)
2. R
1
=3070
,
R
2
=3150
3. V
TM
=2.8V
AC CHARACTERISTICS
(Vcc=2.7~3.3V, Industrial product: T
A
=-40 to 85
C)
Parameter List
Symbol
Speed Bins
Units
55ns
70ns
Min
Max
Min
Max
Read
Read Cycle Time
t
RC
55
-
70
-
ns
Address Access Time
t
AA
-
55
-
70
ns
Chip Select to Output
t
CO
-
55
-
70
ns
Output Enable to Valid Output
t
OE
-
25
-
35
ns
Chip Select to Low-Z Output
t
LZ
10
-
10
-
ns
Output Enable to Low-Z Output
t
OLZ
5
-
5
-
ns
Chip Disable to High-Z Output
t
HZ
0
20
0
25
ns
Output Disable to High-Z Output
t
OHZ
0
20
0
25
ns
Output Hold from Address Change
t
OH
10
-
10
-
ns
Write
Write Cycle Time
t
WC
55
-
70
-
ns
Chip Select to End of Write
t
CW
45
-
60
-
ns
Address Set-up Time
t
AS
0
-
0
-
ns
Address Valid to End of Write
t
AW
45
-
60
-
ns
Write Pulse Width
t
WP
40
-
50
-
ns
Write Recovery Time
t
WR
0
-
0
-
ns
Write to Output High-Z
t
WHZ
0
20
0
20
ns
Data to Write Time Overlap
t
DW
25
-
30
-
ns
Data Hold from Write Time
t
DH
0
-
0
-
ns
End Write to Output Low-Z
t
OW
5
-
5
-
ns
Revision 2.0
April 2000
K6F4008U1C Family
- 6 -
CMOS SRAM
Address
Data Out
Previous Data Valid
Data Valid
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS=OE=V
IL
, WE=V
IH
)
t
AA
t
RC
t
OH
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
Data Valid
High-Z
CS
Address
OE
Data out
NOTES (READ CYCLE)
1.
t
HZ
and
t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition,
t
HZ
(Max.) is less than
t
LZ
(Min.) both for a given device and from device to device
interconnection.
t
OH
t
AA
t
OLZ
t
LZ
t
OHZ
t
HZ
t
RC
t
OE
t
CO
Revision 2.0
April 2000
K6F4008U1C Family
- 7 -
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1)
(WE Controlled)
Address
CS
t
CW(2)
t
WR(4)
TIMING WAVEFORM OF WRITE CYCLE(2)
(CS
Controlled)
Address
CS
t
WC
t
WR(4)
t
AS(3)
t
WP(1)
t
DW
t
DH
t
OW
t
WHZ
Data Undefined
Data Valid
WE
Data in
Data out
t
DW
t
DH
Data Valid
WE
Data in
Data out
High-Z
High-Z
t
WC
t
AW
t
AS(3)
t
CW(2)
t
WP(1)
t
AW
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE
going low: A write end at the earliest transition among CS going high and WE going high, t
WP
is measured from the begining of write
to the end of write.
2. t
CW
is measured from the CS going low to end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end of write to the address change. t
WR
applied in case a write ends as CS or WE going high.
DATA RETENTION WAVE FORM
CS controlled
V
CC
2.7V
2.2V
V
DR
CS
GND
Data Retention Mode
CS
V
CC
- 0.2V
t
SDR
t
RDR
Revision 2.0
April 2000
K6F4008U1C Family
- 8 -
CMOS SRAM
32 PIN SMALLER THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)
1.00
0.10
0.039
0.004
MAX
8.40
0.331
1
.
1
0
M
A
X
0
.
0
0
4
M
A
X
#1
0.50
( )
0.020
11.80
0.10
0.465
0.004
0.45 ~0.75
0.018 ~0.030
13.40
0.10
0.528
0.008
+0.10
0.15
-0.05
+0.004
0.006
-0.002
0~8
+0.10
0.20
-0.05
+0.004
0.008
-0.002
0.50
0.0197
0.25
( )
0.010
MIN
0.05
0.002
MAX
1.20
0.047
8
.
0
0
0
.
3
1
5
TYP
0.25
0.010
#16
#32
#17
Unit: millimeters(inches)
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