Revision 1.01
October 2001
K6F4008U2D Family
- 1 -
CMOS SRAM
Document Title
512K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
Revision History
Revision No.
0.0
1.0
1.01
Remark
Preliminary
Final
Final
History
Initial Draft
Finalized
- Change for tWHZ : 25 to 20ns for 70ns product
- Change for tDW : 20 to 25ns for 55ns product
25 to 30ns for 70ns product
Errata correction
- Removed 'TTL Compatible' from Features
Draft Date
March 16, 2000
April 24, 2000
October 25, 2001
Revision 1.01
October 2001
K6F4008U2D Family
- 2 -
CMOS SRAM
PRODUCT FAMILY
1. The parameter is measured with 30pF test load.
Product Family
Operating Temperature
Vcc Range
Speed
Power Dissipation
PKG Type
Standby
(I
SB1
, Typ.)
Operating
(I
CC1
, Max)
K6F4008U2D-F
Industrial(-40~85
C)
2.7~3.3V
55
1)
/70ns
0.5
A
3mA
48-FBGA-6.10x8.50
512K x 8 bit Super Low Power and Low Voltage Full CMOS Static RAM
GENERAL DESCRIPTION
The K6F4008U2D families are fabricated by SAMSUNG
s
advanced full CMOS process technology. The families support
industrial temperature range and Chip Scale Package for user
flexibility of system design. The families also supports low data
retention voltage for battery back-up operation with low data
retention current.
FEATURES
Process Technology: Full CMOS
Organization: 512K x8 bit
Power Supply Voltage: 2.7~3.3V
Low Data Retention Voltage: 1.5V(Min)
Three State Outputs
Package Type: 48-FBGA-6.10x8.50
FUNCTIONAL BLOCK DIAGRAM
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice
.
Precharge circuit.
Memory array
1024 rows
512
8 columns
I/O Circuit
Column select
Clk gen.
Row
select
I/O
1
Data
cont
Data
cont
I/O
8
Control
logic
CS1
WE
OE
CS2
PIN DESCRIPTION
A
0
A
1
CS
2
A
3
A
6
A
8
I/O
5
A
2
WE
A
4
A
7
I/O
1
I/O
6
DNU
A
5
I/O
2
V
SS
V
CC
V
CC
V
SS
I/O
7
A
18
A
17
I/O
3
I/O
8
OE
CS
1
A
16
A
15
I/O
4
A
9
A
10
A
11
A
12
A
13
A
14
1
2
3
4
5
6
A
B
C
D
E
F
G
H
48(36)-FBGA
Name
Function
Name
Function
CS
1
, CS
2
Chip Select Inputs
I/O
1
~I/O
8
Data Inputs/Outputs
OE
Output Enable Input
Vcc
Power
WE
Write Enable Input
Vss
Ground
A
0
~A
18
Address Inputs
DNU
Do Not Use
Row
Address
Column Address
Revision 1.01
October 2001
K6F4008U2D Family
- 3 -
CMOS SRAM
ABSOLUTE MAXIMUM RATINGS
1)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Item
Symbol
Ratings
Unit
Voltage on any pin relative to Vss
V
IN
, V
OUT
-0.2 to V
CC
+0.5V
V
Voltage on Vcc supply relative to Vss
V
CC
-0.2 to 4.0V
V
Power Dissipation
P
D
1.0
W
Storage temperature
T
STG
-65 to 150
C
Operating Temperature
T
A
-40 to 85
C
PRODUCT LIST
Industrial Temperature Products(-40~85
C)
Part Name
Function
K6F4008U2D-FF55
K6F4008U2D-FF70
48-FBGA, 55ns, 3.0V
48-FBGA, 70ns, 3.0V
FUNCTIONAL DESCRIPTION
1. X means don
t care (Must be in low or high state)
CS
1
CS
2
OE
WE
I/O
Mode
Power
H
X
1)
X
1)
X
1)
High-Z
Deselected
Standby
X
1)
L
X
1)
X
1)
High-Z
Deselected
Standby
L
H
H
H
High-Z
Output Disabled
Active
L
H
L
H
Dout
Read
Active
L
H
X
1)
L
Din
Write
Active
Revision 1.01
October 2001
K6F4008U2D Family
- 4 -
CMOS SRAM
DC AND OPERATING CHARACTERISTICS
1. Super low power product=5
A with special handling.
Item
Symbol
Test Conditions
Min
Typ
Max
Unit
Input leakage current
I
LI
V
IN
=Vss to Vcc
-1
-
1
A
Output leakage current
I
LO
CS
1
=V
IH,
CS
2
=V
IL
or OE=V
IH
or WE=V
IL
, V
IO
=Vss to Vcc
-1
-
1
A
Operating power supply current
I
CC
I
IO
=0mA, CS
1
=V
IL,
CS
2
=V
IH
, WE=V
IH,
V
IN
=V
IH
or V
IL
-
-
2
mA
Average operating current
I
CC1
Cycle time=1
s, 100%duty, I
IO
=0mA, CS
1
0.2V,
CS
2
Vcc-0.2V, V
IN
0.2V or V
IN
VCC-0.2V
-
-
3
mA
I
CC2
Cycle time=Min, I
IO
=0mA, 100% duty,
CS
1
=V
IL
, CS
2
=V
IH,
V
IN
=V
IL
or V
IH
-
-
30
mA
Output low voltage
V
OL
I
OL
= 2.1mA
-
-
0.4
V
Output high voltage
V
OH
I
OH
= -1.0mA
2.4
-
-
V
Standby Current(TTL)
I
SB
CS
1
=V
IH
, CS
2
=V
IL
, Other inputs=V
IH
or V
IL
-
-
0.3
mA
Standby Current (CMOS)
I
SB1
CS
1
Vcc-0.2V, CS
2
Vcc-0.2V(CS
1
controlled) or
CS
2
0.2V(CS
2
controlled), Other inputs=0~Vcc
-
0.5
12
1)
A
RECOMMENDED DC OPERATING CONDITIONS
1)
Note:
1. T
A
=-40 to 85
C, otherwise specified.
2. Overshoot: Vcc+2.0V in case of pulse width
20ns.
3. Undershoot: -2.0V in case of pulse width
20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
Item
Symbol
Min
Typ
Max
Unit
Supply voltage
Vcc
2.7
3.0
3.3
V
Ground
Vss
0
0
0
V
Input high voltage
V
IH
2.2
-
Vcc+0.2
2)
V
Input low voltage
V
IL
-0.2
3)
-
0.6
V
CAPACITANCE
1)
(f=1MHz, T
A
=25
C)
1. Capacitance is sampled, not 100% tested.
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
C
IN
V
IN
=0V
-
8
pF
Input/Output capacitance
C
IO
V
IO
=0V
-
10
pF
Revision 1.01
October 2001
K6F4008U2D Family
- 5 -
CMOS SRAM
DATA RETENTION CHARACTERISTICS
1. CS
1
Vcc-0.2V,
CS
2
Vcc-0.2V
(CS
1
controlled) or
CS
2
0.2V
(CS
2
controlled).
2. Super low power product=2
A with special handling.
Item
Symbol
Test Condition
Min
Typ
Max
Unit
Vcc for data retention
VDR
CS
1
Vcc-0.2V
1)
1.5
-
3.3
V
Data retention current
IDR
Vcc=1.5V, CS
1
Vcc-0.2V
1)
-
0.5
3
2)
A
Data retention set-up time
tSDR
See data retention waveform
0
-
-
ns
Recovery time
tRDR
tRC
-
-
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load (See right): C
L
= 100pF+1TTL
C
L
=30pF+1TTL
C
L
1)
1. Including scope and jig capacitance
R
2
2)
R
1
2)
V
TM
3)
2. R
1
=3070
,
R
2
=3150
3. V
TM
=2.8V
AC CHARACTERISTICS
(Vcc=2.7~3.3V, Industrial product:T
A
=-40 to 85
C)
Parameter List
Symbol
Speed Bins
Units
55ns
70ns
Min
Max
Min
Max
Read
Read Cycle Time
t
RC
55
-
70
-
ns
Address Access Time
t
AA
-
55
-
70
ns
Chip Select to Output
t
CO
-
55
-
70
ns
Output Enable to Valid Output
t
OE
-
25
-
35
ns
Chip Select to Low-Z Output
t
LZ
10
-
10
-
ns
Output Enable to Low-Z Output
t
OLZ
5
-
5
-
ns
Chip Disable to High-Z Output
t
HZ
0
20
0
25
ns
Output Disable to High-Z Output
t
OHZ
0
20
0
25
ns
Output Hold from Address Change
t
OH
10
-
10
-
ns
Write
Write Cycle Time
t
WC
55
-
70
-
ns
Chip Select to End of Write
t
CW
45
-
60
-
ns
Address Set-up Time
t
AS
0
-
0
-
ns
Address Valid to End of Write
t
AW
45
-
60
-
ns
Write Pulse Width
t
WP
40
-
50
-
ns
Write Recovery Time
t
WR
0
-
0
-
ns
Write to Output High-Z
t
WHZ
0
20
0
20
ns
Data to Write Time Overlap
t
DW
25
-
30
-
ns
Data Hold from Write Time
t
DH
0
-
0
-
ns
End Write to Output Low-Z
t
OW
5
-
5
-
ns
Revision 1.01
October 2001
K6F4008U2D Family
- 6 -
CMOS SRAM
Address
Data Out
Previous Data Valid
Data Valid
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS
1
=OE=V
IL
, CS
2
=WE=V
IH
)
t
AA
t
RC
t
OH
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
Data Valid
High-Z
CS
1
Address
OE
Data out
NOTES (READ CYCLE)
1.
t
HZ
and
t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition,
t
HZ
(Max.) is less than
t
LZ
(Min.) both for a given device and from device to device
interconnection.
CS
2
t
OH
t
AA
t
OLZ
t
LZ
t
OHZ
t
HZ(1,2)
t
RC
t
CO2
t
OE
t
CO1
Revision 1.01
October 2001
K6F4008U2D Family
- 7 -
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(2)
(CS
1
Controlled)
Address
CS
1
t
WC
t
WR(4)
t
AS(3)
t
DW
t
DH
Data Valid
WE
Data in
Data out
High-Z
High-Z
CS
2
t
CW(2)
t
WP(1)
t
AW
TIMING WAVEFORM OF WRITE CYCLE(1)
(WE Controlled)
Address
CS
1
t
CW(2)
t
WR(4)
CS
2
t
CW(2)
t
WP(1)
t
DW
t
DH
t
OW
t
WHZ
Data Undefined
Data Valid
WE
Data in
Data out
t
WC
t
AW
t
AS(3)
Revision 1.01
October 2001
K6F4008U2D Family
- 8 -
CMOS SRAM
DATA RETENTION WAVE FORM
CS
1
controlled
V
CC
2.7V
2.2V
V
DR
CS
1
GND
Data Retention Mode
CS
1
V
CC
- 0.2V
t
SDR
t
RDR
TIMING WAVEFORM OF WRITE CYCLE(3)
(CS
2
Controlled)
Address
CS
1
t
AW
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS
1
, a high CS
2
and a low WE. A write begins at the latest transition among CS
1
goes low,
CS
2
going high and WE going low: A write end at the earliest transition among CS
1
going high, CS
2
going low and WE going high, t
WP
is measured from the begining of write to the end of write.
2. t
CW
is measured from the CS
1
going low or CS
2
going high to the end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end of write to the address change. t
WR
applied in case a write ends as CS
1
or WE going high t
WR2
applied
in case a write ends as CS
2
going to low.
CS
2
t
CW(2)
WE
Data in
Data Valid
Data out
High-Z
High-Z
t
CW(2)
t
WR(4)
t
WP(1)
t
DW
t
DH
t
AS(3)
t
WC
CS
2
controlled
V
CC
2.7V
0.4V
V
DR
CS
2
GND
Data Retention Mode
t
SDR
t
RDR
CS
2
0.2V
Revision 1.01
October 2001
K6F4008U2D Family
- 9 -
CMOS SRAM
PACKAGE DIMENSIONS
Units: millimeters
C
1
/
2
6
5
4
3
2
1
A
B
C
D
E
F
G
H
C
B/2
B
C
1
B
C
Bottom View
Top View
D
E
2
E
1
E
C
Side View
0
.
8
5
/
T
y
p
.
0
.
2
5
/
T
y
p
.
A
Y
Detail A
Min
Typ
Max
A
-
0.75
-
B
6.00
6.10
6.20
B1
-
3.75
-
C
8.40
8.50
8.60
C1
-
5.25
-
D
0.30
0.35
0.40
E
-
1.10
1.20
E1
-
0.85
-
E2
0.20
0.25
0.30
Y
-
-
0.08
0.50
0.50
B1
#A1
0
.
3
0
A1 INDEX MARK
Notes.
1. Bump counts: 48(8 row x 6 column)
2. Bump pitch: (x,y)=(0.75 x 0.75)(typ.)
3. All tolerence are +/-0.050 unless
otherwise specified.
4. Typ: Typical
5. Y is coplanarity: 0.08(Max)
48 BALL FINE PITCH BGA(0.75mm ball pitch)
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