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Электронный компонент: K6F4008U2G

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Revision 0.0
June 2003
K6F4008U2G Family
- 1 -
CMOS SRAM
Preliminary
Document Title
512K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
Revision History
Revision No.
0.0
Remark
Preliminary
History
Initial Draft
Draft Date
June 11, 2003
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Revision 0.0
June 2003
K6F4008U2G Family
- 2 -
CMOS SRAM
Preliminary
PRODUCT FAMILY
1. The parameter is measured with 30pF test load.
2. Typical values are at V
CC
=3.0V, T
A
=25
C and not 100% tested.
Product Family
Operating Temperature
Vcc Range
Speed
Power Dissipation
PKG Type
Standby
(I
SB1
, Typ.)
Operating
(I
CC1
, Max)
K6F4008U2G-F
Industrial(-40~85
C)
2.7~3.3V
55
1)
/70ns
3
A
2)
4mA
48(36)-TBGA-6.00x7.00
512K x 8 bit Super Low Power and Low Voltage Full CMOS Static RAM
GENERAL DESCRIPTION
The K6F4008U2G families are fabricated by SAMSUNG
s
advanced full CMOS process technology. The families support
industrial temperature range and Chip Scale Package for user
flexibility of system design. The families also supports low data
retention voltage for battery back-up operation with low data
retention current.
FEATURES
Process Technology: Full CMOS
Organization: 512K x8 bit
Power Supply Voltage: 2.7~3.3V
Low Data Retention Voltage: 1.5V(Min)
Three State Outputs
Package Type: 48(36)-TBGA-6.00x7.00
FUNCTIONAL BLOCK DIAGRAM
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice
.
Precharge circuit.
Memory
Cell
Array
I/O Circuit
Column select
Clk gen.
Row
select
I/O
1
Data
cont
Data
cont
I/O
8
Control
logic
CS1
WE
OE
CS2
PIN DESCRIPTION
A
0
A
1
CS
2
A
3
A
6
A
8
I/O
5
A
2
WE
A
4
A
7
I/O
1
I/O
6
DNU
A
5
I/O
2
V
SS
V
CC
V
CC
V
SS
I/O
7
A
18
A
17
I/O
3
I/O
8
OE
CS
1
A
16
A
15
I/O
4
A
9
A
10
A
11
A
12
A
13
A
14
1
2
3
4
5
6
A
B
C
D
E
F
G
H
48(36)-TBGA
Name
Function
Name
Function
CS
1
, CS
2
Chip Select Inputs
I/O
1
~I/O
8
Data Inputs/Outputs
OE
Output Enable Input
Vcc
Power
WE
Write Enable Input
Vss
Ground
A
0
~A
18
Address Inputs
DNU
Do Not Use
Row
Address
Column Address
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Revision 0.0
June 2003
K6F4008U2G Family
- 3 -
CMOS SRAM
Preliminary
ABSOLUTE MAXIMUM RATINGS
1)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Item
Symbol
Ratings
Unit
Voltage on any pin relative to Vss
V
IN
, V
OUT
-0.5 to V
CC
+0.3V(Max. 3.6V)
V
Voltage on Vcc supply relative to Vss
V
CC
-0.3 to 3.6
V
Power Dissipation
P
D
1.0
W
Storage temperature
T
STG
-65 to 150
C
Operating Temperature
T
A
-40 to 85
C
PRODUCT LIST
Industrial Temperature Products(-40~85
C)
Part Name
Function
K6F4008U2G-EF55
K6F4008U2G-EF70
48(36)-TBGA, 55ns, 3.0V
48(36)-TBGA, 70ns, 3.0V
FUNCTIONAL DESCRIPTION
1. X means don
t care (Must be in low or high state)
CS
1
CS
2
OE
WE
I/O
Mode
Power
H
X
1)
X
1)
X
1)
High-Z
Deselected
Standby
X
1)
L
X
1)
X
1)
High-Z
Deselected
Standby
L
H
H
H
High-Z
Output Disabled
Active
L
H
L
H
Dout
Read
Active
L
H
X
1)
L
Din
Write
Active
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Revision 0.0
June 2003
K6F4008U2G Family
- 4 -
CMOS SRAM
Preliminary
DC AND OPERATING CHARACTERISTICS
1. Typical value are measured at V
CC
=3.0V, T
A
=25
C, and not 100% tested.
Item
Symbol
Test Conditions
Min
Typ
1)
Max
Unit
Input leakage current
I
LI
V
IN
=Vss to Vcc
-1
-
1
A
Output leakage current
I
LO
CS
1
=V
IH,
CS
2
=V
IL
or OE=V
IH
or WE=V
IL
, V
IO
=Vss to Vcc
-1
-
1
A
Average operating current
I
CC1
Cycle time=1
s, 100%duty, I
IO
=0mA, CS
1
0.2V,
CS
2
Vcc-0.2V, V
IN
0.2V or V
IN
V
CC
-0.2V
-
-
4
mA
I
CC2
Cycle time=Min, I
IO
=0mA, 100% duty,
CS
1
=V
IL
, CS
2
=V
IH,
V
IN
=V
IL
or V
IH
70ns
-
-
15
mA
55ns
-
-
20
Output low voltage
V
OL
I
OL
= 2.1mA
-
-
0.4
V
Output high voltage
V
OH
I
OH
= -1.0mA
2.4
-
-
V
Standby Current (CMOS)
I
SB1
CS
1
Vcc-0.2V, CS
2
Vcc-0.2V(CS
1
controlled) or
0V
CS
2
0.2V(CS
2
controlled), Other inputs=0~Vcc
-
3
10
A
RECOMMENDED DC OPERATING CONDITIONS
1)
Note:
1. T
A
=-40 to 85
C, otherwise specified.
2. Overshoot: Vcc+2.0V in case of pulse width
20ns.
3. Undershoot: -2.0V in case of pulse width
20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
Item
Symbol
Min
Typ
Max
Unit
Supply voltage
Vcc
2.7
3.0
3.3
V
Ground
Vss
0
0
0
V
Input high voltage
V
IH
2.2
-
Vcc+0.3
2)
V
Input low voltage
V
IL
-0.3
3)
-
0.6
V
CAPACITANCE
1)
(f=1MHz, T
A
=25
C)
1. Capacitance is sampled, not 100% tested.
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
C
IN
V
IN
=0V
-
8
pF
Input/Output capacitance
C
IO
V
IO
=0V
-
10
pF
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Revision 0.0
June 2003
K6F4008U2G Family
- 5 -
CMOS SRAM
Preliminary
DATA RETENTION CHARACTERISTICS
1. CS
1
Vcc-0.2V, CS
2
Vcc-0.2V(CS
1
controlled) or 0
CS
2
0.2V(CS
2
controlled).
Item
Symbol
Test Condition
Min
Typ
Max
Unit
Vcc for data retention
VDR
CS
1
Vcc-0.2V
1)
1.5
-
3.3
V
Data retention current
IDR
Vcc=1.5V, CS
1
Vcc-0.2V
1)
, V
IN
0V
-
-
3
A
Data retention set-up time
tSDR
See data retention waveform
0
-
-
ns
Recovery time
tRDR
tRC
-
-
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load (See right): C
L
= 100pF+1TTL
C
L
=30pF+1TTL
C
L
1)
1. Including scope and jig capacitance
R
2
2)
R
1
2)
V
TM
3)
2. R
1
=3070
,
R
2
=3150
3. V
TM
=2.8V
AC CHARACTERISTICS
(Vcc=2.7~3.3V, Industrial product:T
A
=-40 to 85
C)
Parameter List
Symbol
Speed
Units
55ns
70ns
Min
Max
Min
Max
Read
Read Cycle Time
t
RC
55
-
70
-
ns
Address Access Time
t
AA
-
55
-
70
ns
Chip Select to Output
t
CO
-
55
-
70
ns
Output Enable to Valid Output
t
OE
-
25
-
35
ns
Chip Select to Low-Z Output
t
LZ
10
-
10
-
ns
Output Enable to Low-Z Output
t
OLZ
5
-
5
-
ns
Chip Disable to High-Z Output
t
HZ
0
20
0
25
ns
Output Disable to High-Z Output
t
OHZ
0
20
0
25
ns
Output Hold from Address Change
t
OH
10
-
10
-
ns
Write
Write Cycle Time
t
WC
55
-
70
-
ns
Chip Select to End of Write
t
CW
45
-
60
-
ns
Address Set-up Time
t
AS
0
-
0
-
ns
Address Valid to End of Write
t
AW
45
-
60
-
ns
Write Pulse Width
t
WP
40
-
50
-
ns
Write Recovery Time
t
WR
0
-
0
-
ns
Write to Output High-Z
t
WHZ
0
20
0
20
ns
Data to Write Time Overlap
t
DW
25
-
30
-
ns
Data Hold from Write Time
t
DH
0
-
0
-
ns
End Write to Output Low-Z
t
OW
5
-
5
-
ns